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Graph neural network based cell library characterization method for fast design technology co-optimization

INTEGRATION-THE VLSI JOURNAL 2025年 101卷

作者： Ma, Tianliang Fan, Guangxi Sun, Xuguang Low, Kain Lu Shao, Leilai Shanghai Jiao Tong Univ Shanghai Peoples R China

design technology co-optimization (DTco) plays a critical role in achieving optimal power, performance, and area (PPA) for advanced semiconductor process development. Cell library characterization is essential in DTco flow, but traditional methods are time-consuming and costly. To overcome these challenges, we propose a graph neural network (GNN)-based machine learning model for rapid and accurate cell library characterization. Our model incorporates cell structures and demonstrates high prediction accuracy across various process-voltage-temperature (PVT) corners, technology parameters and aging effects. Validation with 512 unseen corners and over one million test data points shows accurate predictions of delay, power, and other cell metrics for 37 types of cells and a speed-up of 100X compared with SPICE simulations. Additionally, we investigate system-level metrics such as worst negative slack (WNS), leakage power, and dynamic power using predictions obtained from the GNN-based model on unseen corners. Our model achieves precise predictions, with absolute error <= 3.0 ps for WNS, percentage errors <= 0.60% for leakage power, and <= 0.99% for dynamic power, when compared to golden reference. With the developed model, we further proposed a fine-grained drive strength interpolation methodology to enhance PPA for small-to-medium-scale designs, resulting in an approximate 1%-3% improvement.

关键词： Cell library characterization design technology co-optimization Aging-aware analysis Graph neural networks Electronic design automation

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Fast Cell Library Characterization for design technology co-optimization Based on Graph Neural Networks 24

Fast Cell Library Characterization for Design Technology Co-...

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29th Asia and South Pacific design Automation conference (ASP-DAC)

作者： Ma, Tianliang Deng, Zhihui Sun, Xuguang Shao, Leilai Shanghai Jiao Tong Univ Shanghai Peoples R China

ISBN: (纸本)9798350393545

design technology co-optimization (DTco) plays a critical role in achieving optimal power, performance, and area (PPA) for advanced semiconductor process development. Cell library characterization is essential in DTco flow, but traditional methods are time-consuming and costly. To overcome these challenges, we propose a graph neural network (GNN)-based machine learning model for rapid and accurate cell library characterization. Our model incorporates cell structures and demonstrates high prediction accuracy across various process-voltage-temperature (PVT) corners and technology parameters. Validation with 512 unseen technology corners and over one million test data points shows accurate predictions of delay, power, and input pin capacitance for 33 types of cells, with a mean absolute percentage error (MAPE) <= 0.95% and a speedup of 100X compared with SPICE simulations. Additionally, we investigate system-level metrics such as worst negative slack (WNS), leakage power, and dynamic power using predictions obtained from the GNN-based model on unseen corners. Our model achieves precise predictions, with absolute error <= 3.0 ps for WNS, percentage errors <= 0.60% for leakage power, and <= 0.99% for dynamic power, when compared to golden reference. With the developed model, we further proposed a fine-grained drive strength interpolation methodology to enhance PPA for small-to-medium-scale designs, resulting in an approximate 1-3% improvement.

关键词： Cell Library Characterization design technology co-optimization Graph Neural Networks Drive Strength Interpolation

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Fast design technology co-optimization Framework for Emerging technology With Hierarchical Graph Embedding

Fast Design Technology Co-Optimization Framework for Emergin...

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2nd International Symposium of Electronics design Automation (ISEDA)

作者： Ma, Tianliang Fan, Guangxi Sun, Xuguang Deng, Zhihui Low, Kain Lu Shao, Leilai Shanghai Jiao Tong Univ Shanghai Peoples R China

ISBN: (纸本)9798350352047;9798350352030

In the rapidly evolving landscape of semiconductor technology, the advent of novel materials and sophisticated device architectures offers both opportunities and challenges for researchers. Efficient optimization of power, performance, and area (PPA) is essential in order to fully take advantages of emerging materials and new device structures. To address aforementioned issues, this paper presents a novel fast design technology co-optimization (DTco) framework for emerging flexible technologies. Simulation results demonstrate the advancement of our fast DTco framework with over 100X speedup in both TCAD simulation and cell library characterization comparing to commercial tools. For a comprehensive DTco iteration, covering TCAD simulation, modeling, cell library characterization and PPA evaluations, our framework achieves a runtime speedup between 1.9X to 14.1X depending on the scale of the evaluated circuits. The fast DTco framework incorporates a graph neural network (GNN)-based TCAD surrogate model, a unified compact model, and a GNN-based cell library characterization model. The developed DTco framework not only supports emerging technologies but can be applied to optimize the traditional silicon designs in advanced technology node.

关键词： design technology co-optimization Graph Neural Networks TCAD Simulation compact Model Cell Library Characterization

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Multi-Source Transfer Learning for design technology co-optimization

Multi-Source Transfer Learning for Design Technology Co-Opti...

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IEEE/ACM International Symposium on Low Power Electronics and design (ISLPED)

作者： Lee, Jakang Lee, Jaeseung Park, Seonghyeon Kang, Seokhyeong Pohang Univ Sci & Technol Dept Elect Engn Pohang South Korea

ISBN: (纸本)9798350311754

In advanced technology nodes, pitch scaling have not kept up with the Moore's Law. To continue progression, the design technology co-optimization (DTco) has been proposed. However, implementing DTco requires significant time cost and resources due to iterative trials. In addition, optimal design and technology option depend on each design, thus it should start from scratch whenever the target design changes. We present a DTco framework based on Bayesian optimization that efficiently explores design feedback for optimization. In addition, our framework incorporates a multi-source transfer Gaussian process (MTGP) that ensures robust optimization even for unseen designs. MTGP significantly improves prediction and generalization performance by integrating multiple single source transfer Gaussian processes. Our framework, on average, reduced the mean absolute error of power and area by 47.3% and 24.1%, respectively, and power and area by 37.3% and 19.9%, respectively, compared to the reference, in 7nm technology nodes.

关键词： design technology co-optimization Bayesian optimization Gaussian Process Transfer Learning

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design technology co-optimization assessment for directed self-assembly-based lithography: design for directed self-assembly or directed self-assembly for design?

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JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS 2017年第1期16卷

作者： Lai, Kafai Liu, Chi-Chun Tsai, Hsinyu Xu, Yongan Chi, Cheng Raghunathan, Ananthan Dhagat, Parul Hu, Lin Park, Oseo Jung, Sunggon Cho, Wooyong Morillo, Jaime Pitera, Jed Schmidt, Kristin Guillorn, Mike Brink, Markus Sanders, Daniel Felix, Nelson Bailey, Todd colburn, Matthew IBM Corp IBM Res Div Yorktown Hts NY 10598 USA GlobalFoundries Inc Hopewell Jct NY USA Samsung Elect Corp Hopewell Jct NY USA

We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTco) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTco flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing. (C) 2017 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： optical lithography computational lithography directed self-assembly optical proximity correction optical extension directed self-assembly model design technology co-optimization design for manufacturing design for directed self-assembly

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A Portable Pattern-based design technology co-optimization Flow to Reduce Optical Proximity correction Runtime 12

A Portable Pattern-based Design Technology Co-optimization F...

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conference on design-Process-technology co-optimization for Manufacturability XII

作者： Chen, Yi-Chieh Li, Tsung-Han Lin, Hung-Yu Chen, Kao-Tun Wu, Chun-Sheng Lai, Ya-Chieh Hurat, Philippe Cadence Design Syst Inc 2Lixing 6th RdHsinchu Sci Pk Hsinchu Taiwan Winbond Elect Corp 8Keya 1st Rd Taichung Taiwan Cadence Design Syst Inc 2655 Seely Ave San Jose CA 95134 USA

ISBN: (数字)9781510616691

ISBN: (纸本)9781510616691

Along with process improvement and integrated circuit (IC) design complexity increased, failure rate caused by optical getting higher in the semiconductor manufacture. In order to enhance chip quality, optical proximity correction (OPC) plays an indispensable rule in the manufacture industry. However, OPC, includes model creation, correction, simulation and verification, is a bottleneck from design to manufacture due to the multiple iterations and advanced physical behavior description in math. Thus, this paper presented a pattern-based design technology co-optimization (PB-DTco) flow in cooperation with OPC to find out patterns which will negatively affect the yield and fixed it automatically in advance to reduce the run-time in OPC operation. PB-DTco flow can generate plenty of test patterns for model creation and yield gaining, classify candidate patterns systematically and furthermore build up bank includes pairs of match and optimization patterns quickly. Those banks can be used for hotspot fixing, layout optimization and also be referenced for the next technology node. Therefore, the combination of PB-DTco flow with OPC not only benefits for reducing the time-to-market but also flexible and can be easily adapted to diversity OPC flow.

关键词： Pattern-Based design technology co-optimization Optical Proximity correction and Yield Ramping

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Advanced fast 3D DSA Model Development and Calibration for design technology co-optimization

Advanced fast 3D DSA Model Development and Calibration for D...

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conference on Emerging Patterning Technologies

作者： Lai, Kafai Meliorisz, Balint Muelders, Thomas Welling, Ulrich Stock, Hans-Jurgen Marokkey, Sajan Demmerle, Wolfgang Liu, Chi-Chun Chi, Cheng Guo, Jing IBM Res TJ Watson Res Ctr Yorktown Hts NY 10598 USA Synopsys GmbH Karl Hammerschmidt Str 34 Aschheim Dornach Germany IBM Res Albany Nano Technol Ctr Albany NY USA

ISBN: (数字)9781510607408

ISBN: (纸本)9781510607392;9781510607408

Direct optimization (DO) of a 3D DSA model is a more optimal approach to a DTco study in terms of accuracy and speed compared to a Cahn Hilliard Equation solver. DO's shorter run time (10X to 100X faster) and linear scaling makes it scalable to the area required for a DTco study. However, the lack of temporal data output, as opposed to prior art, requires a new calibration method. The new method involves a specific set of calibration patterns. The calibration pattern's design is extremely important when temporal data is absent to obtain robust model parameters. A model calibrated to a Hybrid DSA system with a set of device-relevant constructs indicates the effectiveness of using non-temporal data. Preliminary model prediction using programmed defects on chemo-epitaxy shows encouraging results and agree qualitatively well with theoretical predictions from a strong segregation theory.

关键词： Optical Lithography computational Lithography Directed Self Assembly DSA compact model Phase field model design technology co-optimization DSA model calibration Block copolymers Direct optimization

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design technology co-optimization for a robust 10nm Metal1 solution for Logic design and SRAM

Design technology co-optimization for a robust 10nm Metal1 s...

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conference on design-Process-technology co-optimization for Manufacturability VIII

作者： Vandewalle, Boris Chava, Bharani Sakhare, Sushil Ryckaert, Julien Dusa, Mircea IMEC Kapeldreef 75 B-3001 Heverlee Belgium ASML B-3001 Louvain Belgium

ISBN: (纸本)9780819499769

The density requirement expected for the 10nm node continues to increase the pressure on patterning. With the frontend of line adopting a regular layout (mostly unidirectional), most of the complexity needed for a functional chip ends up in the interconnect layer and Metal1. Assuming that Extreme Ultra Violet Lithography (EUVL) will not be ready for the early stage of 10nm production but only for high volume manufacturing, we have studied how ArF immersion lithography can be extended for Metal1 to sustain the development of the technology as well as the early production phase, while at the same time remaining compatible with an EUVL single patterning solution. We show how close interaction between design, process and computational lithography leads to a Metal1 triple patterning solution using Negative Tone Development (NTD), and how the same design solution can be supported by EUVL single patterning. Particular attention will be paid to line end printability performance, both tip to tip and tip to line, as we believe it is a key parameter to define the best compromise between lithography performance and design density.

关键词： triple patterning negative tone development source mask optimization design technology co-optimization

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Sub-20 nm design technology co-optimization for Standard Cell Logic 33

Sub-20 nm Design Technology Co-Optimization for Standard Cel...

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33rd IEEE/ACM International conference on computer-Aided design (ICCAD)

作者： Vaidyanathan, Kaushik Liebmann, Lars Strojwas, Andrzej Pileggi, Larry Carnegie Mellon Univ Pittsburgh PA 15213 USA IBM Corp East Fishkill NY 12533 USA

ISBN: (纸本)9781479962785

Efficiency and manufacturability of standard cell logic is critical for an IC, as standard cells are at the heart of the nexus between technology definition, circuit design and physical synthesis. conventional standard cell design techniques are increasingly ineffective as we scale to patterning restricted sub-20 nm CMOS nodes. To meet the constraints and leverage the features of future technology offerings, we propose a holistic design technology co-optimization (DTco) for standard cell logic. In our holistic DTco we co-optimize the standard cell architecture to balance manufacturability and efficiency at the cell level while taking into account block level considerations such as pin accessibility and power rail robustness. Our DTco in a foundry 14 nm CMOS resulted in two standard cell architectures, namely, 10T_BiDir and 10T_UniDir. We evaluated these cell libraries with physically synthesized blocks and ring oscillator test structures in IBM 14SOI process. We observed that 10T_BiDir emerges as the preferred alternative at 14 nm CMOS, with 10T_UniDir promising better scalability to future nodes.

关键词： Standard cell logic 14 nm CMOS design technology co-optimization FinFET device Multiple patterning

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Sub-20 nm design technology co-optimization for standard cell logic 14

Sub-20 nm design technology co-optimization for standard cel...

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Proceedings of the 2014 IEEE/ACM International conference on computer-Aided design

作者： Kaushik Vaidyanathan Lars Liebmann Andrzej Strojwas Larry Pileggi Carnegie Mellon University Pittsburgh PA IBM East Fishkill NY

ISBN: (纸本)9781479962778

关键词： FinFET device design technology co-optimization 14 nm CMOS multiple patterning standard cell logic

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