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Skew compensation in energy recovery clock distribution networks

IET COMPUTERS AND DIGITAL TECHNIQUES 2010年第1期4卷 56-72页

作者： Esmaeili, S. E. Farhangi, A. M. Al-Khalili, A. J. Cowan, G. E. R. Concordia Univ Dept Elect & Comp Engn Montreal PQ H3G 1M8 Canada

In this study a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. The STMicroelectronics 90 nm technology allows the use of devices with different threshold voltages, namely: high threshold voltage (HVT), standard threshold voltage (SVT) and low threshold voltage (LVT). Three types of flip-flops of equal input load: 'fast', 'standard' and 'slow' are used. Timing parameters of the flip-flops are adjusted by manipulating the switching threshold of the clock port of the flip-flops. A fast/slow flip-flops has a shorter/longer T-DQ delay, compared with a standard flip-flops for the same setup time (T-DCLK). Distributing flip-flops according to their delay requirements would reduce the effect of the clock's skew on the outputs of sequentially adjacent flip-flops. Owing to the slow rise time of the sinusoidal clock signal used in energy recovery clock distribution networks compared to the conventional square-wave clock, the skew that can be compensated for in energy recovery clock distribution networks using this approach would be much higher than in square-wave clock distribution networks. This approach increases the skew bounds required by algorithms to balance the skew in the clock tree leading to reduced design complexity. Theoretical analysis and simulation results using STMicroelectronics 90 nm technology at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% of the clock period can be compensated for in the example used. In addition, constructing clock trees using the skew slack provided in the proposed technique in a new modified differed merge embedding (DME) algorithm on five benchmarks have shown that the proposed technique enables an average reduction of 11.5% in total wire length and 53.2% reduction in the number of wire elongations. Balancing the skew in the clock tree using buffers was not considered here

关键词： switching threshold differed merge embedding algorithm Logic and switching circuits timing parameters design complexity Other digital circuits delay requirements distributing flip-flops size 90 nm Logic circuits energy recovery property square-wave clock distribution networks Logic design methods Elmore delay model wire elongations frequency 500 MHz skew compensation energy recovery flip-flop clocks skew bounds Digital circuit design, modelling and testing clock tree sinusoidal clock signal skew slack logic design flip-flops clock port energy recovery clock distribution networks

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The implementation of a direct search approach for the resolution of complex and changing rule-based problems

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ENGINEERING WITH COMPUTERS 2011年第2期27卷 105-115页

作者： Medland, Anthony John Matthews, Jason Univ Bath Dept Mech Engn Bath BA2 7AY Avon England

During the evolution of constraint modeling approaches, they have increased in their ability to resolve more and more complex problems. They all rely upon their ability to define the design problem by a set of constraint rules, which are true when the problem is solved, by the manipulation of selected free variables. However, as they have advanced differing techniques, they have been applied to address problems of increasing complexity. This study has been directed toward addressing those that are not only complex but also ill structured and evolving. In order to address such problems, an approach has been developed that employs sensitivity analysis and problem strategies to form an evolving direct search technique. While this is generic approach, which has been applied to a range of engineering problems, it is illustrated here through its use in a study into the posture modeling of humans. In this, it was recognized that such a new approach was required due to the complex description, limits, and postures possible in the human body.

关键词： design complexity Sensitivity Constraint resolution Human modeling

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Rapid manufactured textiles

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INTERNATIONAL JOURNAL OF COMPUTER INTEGRATED MANUFACTURING 2007年第1期20卷 96-105页

作者： Bingham, G. A. Hague, R. J. M. Tuck, C. J. Long, A. C. Crookston, J. J. Sherburn, M. N. Univ Loughborough Wolfson Sch Mech & Mfg Engn Rapid Mfg Res Grp Leicester Leics England Univ Nottingham Sch Mech Mat & Mfg Engn Polymer Composites Res Grp Nottingham NG7 2RD England

Rapid Manufacturing (RM) is increasingly becoming a viable manufacturing process due to dramatic advantages that are achievable in the area of design complexity. Through the exploration of the design freedom afforded by RM, this paper introduces the concept and novel research area of RM textiles. The paper highlights the design and manufacturing possibilities applied to textiles when considering additive manufacturing techniques, the current limitations of conventional Computer Aided design (CAD) software when creating RM textile three-dimensional (3D) data and the potential use of dedicated 'textile CAD'. A methodology for the generation of 3D conformal RM textile articles is presented in addition to the initial investigation of 'efficient manufacture' by the collapsing of RM textile structures into their lowest potential energy state. The work concludes that through the utilization of RM it is entirely possible to manufacture a structure that incorporates drape and free movement properties directly comparable with conventional textiles.

关键词： rapid manufacturing textiles smart textile design complexity

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A LOW complexity APPROACH FOR FAULT-DETECTION IN C-TESTABLE ORTHOGONAL VLSI ARRAYS

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1988年第4期22卷 277-299页

作者： HUANG, WK LOMBARDI, F UNIV COLORADO DEPT ELECT & COMP ENGNBOULDERCO 80309

This paper presents an extension to existing approaches for fault detection and C-testability of orthogonal iterative arrays. C-testability is given by a testing process whose complexity is independent of the dimensions of the arrays and the erroneous states of the cells. The state transition table of a basic cell is analyzed. Five new states are added to it. These states are used to internally reproduce the test input and propagate the faulty state to the output pins of a chip. The testing process is exhaustively analyzed. The characteristics of the additional states are presented. complexity of the testing process (number of test vectors) is discussed. It is proved that even though the number of additinal states in the proposed approach is greater than previous approaches (five states compared with four), the required number of test vectors is considerably reduced. Illustrative examples are given. An approach to implement the proposed C-testability approach into logic design is also presented. complexity of this implementation is analyzed. A conjecture about a possible relation between the number of additional states and the complexity of the testing process is postulated.

关键词： C-testability design for testability Testing Fault detection Cellular automata Array design complexity

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A method for comparing panel complexity to traditional material and production cost estimating techniques

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OCEAN ENGINEERING 2013年 70卷 61-71页

作者： Rigterink, Douglas Collette, Matthew Singer, David J. Univ Michigan Dept Naval Architecture & Marine Engn Ann Arbor MI 48109 USA

In this paper a metric for assessing the producibility of a stiffened grillage structure in the early stage design is presented. This metric is comprised of seven separate producibility drivers that are dependent on the properties of the panel. The new producibility metric is compared with a traditional costing method in a two-objective genetic algorithm to show that there is a competition between the two methods, meaning that the new metric gives a designer additional information at the early design stage. The estimated costs versus producibility scores for several grillage sizes show that large gains in producibility can be made without large increases in estimated costs up until a critical point where a knee in the Pareto front occurs. Furthermore, it was found that the individual producibility elements are highly dependent on the size of the panel tested and the constraints the panel must meet. In general, producibility is a key factor to be considered in structural design and should be accounted for in any structural optimization. (C) 2013 Elsevier Ltd. All rights reserved.

关键词： Producibility Genetic optimization Early stage design Stiffened panel design complexity Cost assessment

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Extensibility of a linear rapid robust design methodology

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ENGINEERING OPTIMIZATION 2016年第5期48卷 792-810页

作者： Steinfeldt, Bradley A. Braun, Robert D. Georgia Inst Technol Guggenheum Sch Aerosp Engn Atlanta GA 30332 USA

The extensibility of a linear rapid robust design methodology is examined. This analysis is approached from a computational cost and accuracy perspective. The sensitivity of the solution's computational cost is examined by analysing effects such as the number of design variables, nonlinearity of the CAs, and nonlinearity of the response in addition to several potential complexity metrics. Relative to traditional robust design methods, the linear rapid robust design methodology scaled better with the size of the problem and had performance that exceeded the traditional techniques examined. The accuracy of applying a method with linear fundamentals to nonlinear problems was examined. It is observed that if the magnitude of nonlinearity is less than 1000 times that of the nominal linear response, the error associated with applying successive linearization will result in [GRAPHICS] errors in the response less than 10% compared to the full nonlinear error.

关键词： perturbation analysis robust design multidisciplinary design optimization design complexity

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Fault tolerant architecture design using quad-gate-transistor redundancy

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IET CIRCUITS DEVICES & SYSTEMS 2015年第3期9卷 152-160页

作者： Mukherjee, Atin Dhar, Anindya Sundar Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

In the current era of speed and recent trend of device miniaturisation, failure rates have been increased with the increase in the design complexity and the density of transistors in chip and hence reliability issues at circuit level have become more prominent and challenging. In this study, the authors propose a new static fault tolerant method called quad-gate-transistor, which uses quadded-transistor output logic with gate level quad implementation of the given circuitry to make the system defect tolerant. Such combination of gate and transistor level redundancy provides significantly higher reliability over classical triple modular redundancy and other existing static approaches as supported by extensive simulation results using some of the ISCAS 85 benchmark and other standard circuits. The proposed method also takes care of most of the limitations that restrict the use of the existing static methods in practical applications.

关键词： ISCAS 85 benchmark fault tolerant architecture design circuit level transistor-transistor logic failure rates triple modular redundancy device miniaturisation system defect tolerant circuit reliability redundancy transistor circuits logic design quadded-transistor output logic design complexity transistor level redundancy failure analysis reliability quad-gate-transistor redundancy static approaches fault tolerance

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Development and application of a model-based collaborative analysis and design framework for microgrid power systems

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IET GENERATION TRANSMISSION & DISTRIBUTION 2016年第13期10卷 3201-3210页

作者： Zhu, Wanlu Shi, Jian Liu, Sheng Abdelwahed, Sherif Harbin Engn Univ Coll Automat Harbin 15001 Peoples R China Mississippi State Univ Dept Elect & Comp Engn Starkville MS 39762 USA

Microgrids have been recognised as essential components of the smart grid. However, recent advances on communication, control, and other intelligent techniques have also significantly increased the design complexity of the microgrids. This calls for attention for the microgrid community to be aware of the latest design challenges and develop visionary approaches to re-evaluate the legacy power system design concepts and analysis tools that are currently utilised for microgrid studies. This study proposes a novel model-based analysis and design framework tailored specifically for microgrids based on the concept of model-integrated computing. The proposed framework aims to provide a flexible and extensible integrated environment to facilitate rapid modelling and simulation of microgrids as well as the implementation of other control, analysis, and microgrid design applications. In this study, the authors focus on demonstrating and examining how the adoption of the proposed framework can effectively reduce the duration and costs of the design process, enhance the experience of the end-users, and improve the overall quality and efficiency of the microgrid study activities. Case studies under various microgrid operating scenarios are presented to validate the effectiveness of the proposed framework.

关键词： distributed power generation smart power grids model-based collaborative analysis design framework microgrid power systems smart grid intelligent techniques design complexity microgrid community visionary approaches legacy power system design concepts analysis tools model-integrated computing microgrid management applications

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A proposal to improve the competence of students within the unnecessarily complex mechanical engineering design environment

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INTERNATIONAL JOURNAL OF TECHNOLOGY AND design EDUCATION 2021年第4期31卷 741-770页

作者： Geren, Necdet Uzay, Cagri Bayramoglu, Melih Cukurova Univ Dept Mech Engn Fac Engn TR-01330 Adana Turkey

It is well accepted that many mechanical engineering (ME) design processes are complex. We believe that many ME design approaches include unnecessary complexity, intended to assist the teaching of engineering knowledge. This technical complexity has contributed to many critical issues in ME education, including decreased enrolments in many countries;diminished pre-existing skills amongst University entrants and increasing numbers of students abandoning courses. This has resulted in fewer fully competent graduate engineers, amongst whom a reduced understanding of essential knowledge leads to a consequent reduction in their capability. Unnecessarily complicated theoretical knowledge is taught to students of mechanical engineering design. Empirical evidence is provided to demonstrate this, along with the difficulty experienced by students when they attempt to apply their theoretical knowledge to gear design exercises. A proposed remedy for this issue has been thoroughly evaluated for the ME design and machine design project courses taught in Turkey. The findings indicate that most of the students cannot cope with excessively complex design approaches, and are reluctant to use them. This paper proposes an alternative solution, a generic method for the reductive, simplified problem-solving of typical design problems, without materially sacrificing accuracy. The basic implementation of the method is provided as a road map to show its application. If academics continue the efforts to extend the implementation of the method, in particular for machine components, this would reduce the issue of reduced numbers of capable graduate engineers. The method can also improve the self-confidence of students, as opposed to limiting their professional capacity.

关键词： Mechanical engineering Quality of graduates design simplification Student recruitment design complexity

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Defect proneness estimation and feedback approach for software design quality improvement

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INFORMATION AND SOFTWARE TECHNOLOGY 2012年第3期54卷 274-285页

作者： Nair, T. R. Gopalakrishnan Selvarani, R. Dayananda Sagar Inst Res & Ind Incubat Ctr Bangalore 560078 Karnataka India

Context: Modern software engineering demands professionals and researchers to proactively and collectively work towards exploring and experimenting viable and valuable mechanisms in order to extract all kinds of degenerative bugs, security holes, and possible deviations at the initial stage. Having understood the real need here, we have introduced a novel methodology for the estimation of defect proneness of class structures in object oriented (OO) software systems at design stage. Objective: The objective of this work is to develop an estimation model that provides significant assessment of defect proneness of object oriented software packages at design phase of SDLC. This frame work enhances the efficiency of SDLC through design quality improvement. Method: This involves a data driven methodology which is based on the empirical study of the relationship existing between design parameters and defect proneness. In the first phase, a mapping of the relationship between the design metrics and normal occurrence pattern of defects are carried out. This is represented as a set of non linear multifunctional regression equations which reflects the influence of individual design metrics on defect proneness. The defect proneness estimation model is then generated by weighted linear combination of these multifunctional regression equations. The weighted coefficients are evaluated through GQM (Goal Question Metric) paradigm. Results: The model evaluation and validation is carried out with a selected set of cases which is found to be promising. The current study is successfully dealt with three projects and it opens up the opportunity to extend this to a wide range of projects across industries. Conclusion: The defect proneness estimation at design stage facilitates an effective feedback to the design architect and enabling him to identify and reduce the number of defects in the modules appropriately. This results in a considerable improvement in software design leading to cost

关键词： Object-oriented design Structural properties design complexity Defect proneness CK metrics Quality factors

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