检索结果-内蒙古大学图书馆

29th IEEE VLSI Test Symposium (VTS)/Workshop on design for Reliability and Variability (DRV)

作者： Sinha, Arani Natarajan, Suriyaprakash AMD USA

ISBN: (纸本)9781612846552

Today's electronic systems and those envisioned for the near future exploit significant integration of devices on a chip with incredibly shrinking device/interconnect geometries. Such systems operate very close to their power/performance margins to achieve maximum profitability. The increase in the design complexity of such systems that now include digital and analog components, coupled with the race to reach the market faster severely constrains the resources and time to validate and test them. Furthermore, products can also fail to operate correctly in the field prior to their expected end-of-life due to transient errors or aging.

关键词： Energy efficiency Manufacturing Radio frequency Reliability engineering Servers Signal design Tuning aging analog components design complexity device geometries digital components electronic systems integrated circuit design integrated circuit yield integrated circuit yield interconnect geometries mixed analogue-digital integrated circuits performance margins power margins transient errors

来源：评论

学校读者我要写书评

暂无评论

Recent Research and Emerging Challenges in design and Optimization for Digital Microfluidic Biochips

Recent Research and Emerging Challenges in Design and Optimi...

引用

24th IEEE International System-on-Chip Conference (SOCC)

作者： Huang, Tsung-Wei Lin, Yan-You Chang, Jia-Wen Ho, Tsung-Yi Natl Cheng Kung Univ Dept Comp Sci & Informat Engn Tainan 70101 Taiwan Duke Univ Dept Elect & Comp Engn Durham NC USA

ISBN: (纸本)9781457716171

Advances in droplet-based digital microfluidic biochips (DMFBs) have led to the emergence of biochips for automating laboratory procedures in biochemistry and molecular biology. These devices enable the precise control of microliter of nanoliter volumes of biochemical samples and reagents. They combine electronics with biology, and integrate various bioassay operations, such as sample preparation, analysis, separation, and detection. To meet the challenges of increasing design complexity, computer-aided-design (CAD) tools have been involved to build DMFBs efficiently. This paper provides an overview of DMFBs and describes emerging CAD tools for the automated synthesis and optimization of DMFB designs, from fluidic-level synthesis to chip-level design. design automations are expected to relieve the design burden of manual optimization of bioassays, time-consuming chip designs, and costly testing and maintenance procedures. With the assistance of CAD tools, users can concentrate on the development and abstraction of nanoscale bioassays while leaving chip optimization and implementation details to CAD tools.

关键词： CAD Performance evaluation Wires automated synthesis bioMEMS bioassay operations biochemical reagents biochemistry computer-aided-design tools design complexity droplet-based digital microfluidic biochips electronics lab-on-a-chip laboratory procedure aut

来源：评论

学校读者我要写书评

暂无评论

SoCGuard: A Runtime Verification Solution for the Functional Correctness of SoCs

SoCGuard: A Runtime Verification Solution for the Functional...

引用

18th IEEE/IFIP International Conference on VLSI and System-on-Chip

作者： Abdel-Khalek, Rawan Bertacco, Valeria Univ Michigan Dept Comp Sci & Engn Ann Arbor MI 48109 USA

ISBN: (纸本)9781424464708

The system-on-chip design methodology is characterized by delivering a very high level of design complexity in a short development time. While this aspect is precisely what makes SoCs appealing, it also creates a unique challenge for their verification, requiring the system to be validated as a whole, besides checking the correctness of each of its components. In this paper, we propose a runtime correctness solution for SoCs where we equip each component with two modes of operation: a default high performance one, where all components capabilities are active, and a basic mode where only baseline modules are in operation, so that all basic functionality can be delivered, but performance is not optimized. By alternating between these two modes of execution on individual components, or on all components together, we can carefully sidestep both component and integration bugs that have escaped into the manufactured product. Our experimental evaluation on a LEON3 SoC shows that this solution incurs only 4% area overhead and less than 5% performance impact in most cases.

关键词： LEON3 SoC SoCGuard circuit complexity design complexity functional correctness integrated circuit design integration bugs runtime verification solution system-on-chip system-on-chip design methodology

来源：评论

学校读者我要写书评

暂无评论

How to Construct a Mixed Methods Research design

引用

KOLNER ZEITSCHRIFT FUR SOZIOLOGIE UND SOZIALPSYCHOLOGIE 2017年第2-Sup期69卷 107-131页

作者： Schoonenboom, Judith Johnson, R. Burke Univ Wien Inst Bildungswissensch Sensengasse 3a A-1090 Vienna Austria Univ S Alabama Dept Profess Studies UCOM 3700 Mobile AL 36688 USA

This article provides researchers with knowledge of how to design a high quality mixed methods research study. To design a mixed study, researchers must understand and carefully consider each of the dimensions of mixed methods design, and always keep an eye on the issue of validity. We explain the seven major design dimensions: purpose, theoretical drive, timing (simultaneity and dependency), point of integration, typological versus interactive design approaches, planned versus emergent design, and design complexity. There also are multiple secondary dimensions that need to be considered during the design process. We explain ten secondary dimensions of design to be considered for each research study. We also provide two case studies showing how the mixed designs were constructed.

关键词： Methods of social research Mixed methods Qualitative methods Quantitative methods Research design Mixed methods design Mixing purpose Timing of mixing Point of integration design complexity

来源：评论

学校读者我要写书评

暂无评论

A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 μm Technology 15th

A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate...

引用

15th IFIP WG 6.2 International Conference on Wired/Wireless Internet Communications (WWIC)_

作者： Zhang, Yinhang Hu, Qingsheng Zhan, Yongzheng Southeast Univ Inst RF & OE ICs Nanjing 210096 Jiangsu Peoples R China

ISBN: (纸本)9783319613826;9783319613819

This paper presents a 20 Gb/s receive equalizer including an adaptive continuous time linear equalizer (CTLE) and a 2-tap half-rate decision feedback equalizer (DFE) in 0.13 mu m BiCMOS technology for high speed serial link. The CTLE can adjust the ratio of high frequency and low frequency components adaptively by detecting the energy at both ends of a slicer and then generating a control signal by an integrator. Following the CTLE is a half-rate DFE which can get a better trade-off between the working speed and design complexity especially for the case of 20 Gb/s or above. The chip area including pads and chip guarding is about 0.72 x 0.86 mm(2) and the power consumption is about 528 mW. Post simulation results show that the horizontal eye opening of the equalized data can be up to 0.9 UI at 20 Gb/s.

关键词： CTLE DFE Serial link design complexity

来源：评论

学校读者我要写书评

暂无评论

A Distributed AXI-based Platform for Post-Silicon Validation

A Distributed AXI-based Platform for Post-Silicon Validation

引用

29th IEEE VLSI Test Symposium (VTS)/Workshop on design for Reliability and Variability (DRV)

作者： Neishaburi, M. H. Zilic, Zeljko McGill Univ Montreal PQ H3A 2A7 Canada

ISBN: (纸本)9781612846552

With a significant increase in the design complexity of cores and associated communication among them, post-silicon validation has become a demanding task in System on Chips (SoCs) design. To ensure that final products are fault-free and ready for market, the post-silicon validation goal is to catch bugs and pinpoint the root causes of errors that could escape from pre-silicon verification tools. Post-silicon validation involves running a hardware prototype in an environment that is similar to its final platform with its expected workload. As new SoCs tend to have many cores, the interactions among these cores are becoming so complex that post-silicon debug techniques should address not only validation of the functional aspects of a design but such techniques have to "bulletproof" the communication and synchronization among cores inside an SoC. In this paper, we propose an AXI based environment for post-silicon validation. The proposed environment involves Local Debugging Unit (LDU) and Shared Debugging Unit (SDU). LDU monitors trace of transactions issued by the hardware prototype and detect undesired conditions on bus. SDU combines debug traces from different LDUs. We embed the proposed SDU inside an AXI configurable interconnect. Major benefits of using our proposed debug platform over traditional techniques for silicon validation are as follows: 1) it detects and bypasses real time severe faulty conditions such as deadlocks resulting from design errors or electrical faults 2) there is no need for internal trace memory because SDU can communicate to the external memory through slave ports 3) it enables online monitoring of the trace buffer.

关键词： AXI configurable interconnect Debugging Hardware Monitoring Prototypes SDRAM Si System-on-a-chip advanced extensible interface communication computer debugging design complexity distributed AXI-based platform electrical faults elemental semiconductors hardware prototype integrated circuit design integrated circuit interconnections internal trace memory local debugging unit peripheral interfaces post-silicon debug techniques post-silicon validation pre-silicon verification tools shared debugging unit silicon synchronization system on chips design system-on-chip

来源：评论

学校读者我要写书评

暂无评论

Testing and prevention of head-in-pillow

Testing and prevention of head-in-pillow

引用

2010 5th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2010 and International 3D IC Conference

作者： Liu, Yan Fiacco, Pamela Lee, Ning-Cheng Indium Corporation Clinton NY United States

The electronic industry is moving toward smaller, faster, and cheaper. In the case of CSP or BGA, the components are reducing in pitch and ball size but increasing in package size. Due to the high complexity in design... 详细信息

ISBN: (纸本)9781424497836

关键词： BGA CSP HIP defect ball grid arrays chip scale packaging design complexity electrical continuity electronic industry head-in-pillow prevention head-in-pillow testing mechanical contact solder joint solder paste coalescence solder paste selection phase sol

来源：评论

学校读者我要写书评

暂无评论

Novel distributed UEP rateless coding scheme for data transmission in deep space networks

引用

Science China(Information Sciences) 2018年第4期61卷 87-96页

作者： Shuang WU Dezhi LI Zhenyong WANG Qing GUO School of Electronics and Information Engineering Harbin Institute of Technology Shenzhen Academy of Aerospace Technology

In deep space data transmission systems, deep space networks can be constructed on different orbits, and the data from each orbit are always associated with the different reliability requirements. In this study, a novel UEP(unequal error protection) transmission scheme based on distributed LT codes is proposed in order to ensure that all the data can be transmitted according to their own reliability requirements and obtain high transmission efficiency property. In the proposed scheme, the sub-codes on each node(orbits) were performed by a classic LT encoding process. By assigning different degree distributions to the sub-codes, all types of data can be transmitted with better transmission efficiency in comparison to the traditional scheme,and can be recovered at the destination with their own reliability requirements. Moreover, the design of the proposed scheme is much easier than that of the traditional scheme, and is also suitable to the strictly limited processing capacity property of deep space networks. By carrying out asymptotic analysis on the proposed scheme, and by obtaining the numerical and simulation results, it can be seen that the proposed scheme can approximately achieve the same UEP property and much better transmission efficiency than the traditional scheme. Additionally, the results demonstrate that the proposed scheme is much more suitable to deep space network data transmission, in comparison to the traditional scheme.

关键词： deep space networks distributed rateless codes UEP encoding overhead asymptotic analysis design complexity

来源：评论

学校读者我要写书评

暂无评论

Assembly process analysis and system design for deep in-situ fidelity corer

引用

ADVANCED ENGINEERING INFORMATICS 2024年第PartA期62卷

作者： Yang, Xun Xie, Heping Chen, Ling Gao, Mingzhong Li, Cunbao Li, Jianan Sichuan Univ Sch Mech Engn Chengdu 610065 Peoples R China Shenzhen Univ Coll Civil & Transportat Engn Shenzhen 518060 Peoples R China Sichuan Univ Coll Water Resource & Hydropower State Key Lab Hydraul & Mt River Engn Chengdu 610065 Peoples R China Sichuan Univ State Key Lab Intelligent Construct & Hlth Operat Chengdu 610065 Peoples R China

The deep in-situ corer is an essential tool for exploring the physical and mechanical behaviours of rocks at varying depths. Corers are multi-part products, encompassing extensive redundant assembly information stemming from the intricate assembly processes and numerous components. Thus, designing assembly systems for corers poses complexity challenges. This paper proposes an automated assembly system design framework, comprising assembly process analysis and system development. The proposed framework offers comprehensive design processes for multi-part product assembly systems, emphasizing managing information amount and complexity during the design phase. Specially, design principles and methods for minimizing information amount are analysed. And the directed graph is utilized to express the assembly information. Building upon this foundation, automated assemblability assessment and assembly process modular clustering is proposed to amalgamate and streamline assembly information, thus reducing design complexity. Leveraging pre-processed assembly information, the sub-functional solutions for assembly system are solved and optimized with AD (Axiomatic design) and TRIZ (the Theory of Inventive Problem Solving). A case study of the deep-sea gas hydrate corer validated the effectiveness of the proposed methods in reducing information amount and yielding subfunctional solutions, thereby facilitating overall system design realization. Assembly experiments verified the designed system accomplished functional requirements. This study serves as a valuable reference for automated assembly analysis and system development for multi-part products, offering technical insights into developing deep in-situ cores from an assembly perspective.

关键词： Deep in -situ fidelity corer Assembly system design Information amount design complexity Assembly process analysis

来源：评论

学校读者我要写书评

暂无评论

Supply network design for mass personalization in Industry 4.0 era

引用

INTERNATIONAL JOURNAL OF PRODUCTION ECONOMICS 2022年第0期244卷 108349-108349页

作者： Katoozian, Hoora Zanjani, Masoumeh Kazemi Concordia Univ Dept Mech Ind & Aerosp Engn 1515 St Catherine St W Montreal PQ H3G 1M8 Canada Interuniv Res Ctr Enterprise Networks Logist & Tr Montreal PQ Canada

The manufacturing industry is confronted with the growing demand of personalized products of small batch sizes. In other words, the producers are faced with the satisfaction of heterogeneous customer needs through individualization and the realization of scale effects along the value chain. This study is among the first that proposes a mixed-integer programming model to obtain the optimal configuration of a supply network comprising of a pool of suppliers to satisfy the demand of highly-customized and modular-structured products. The product individualization is incorporated into the model by considering different design complexity levels for the components/sub-assemblies in the bill-of-material. Furthermore, the impact of batch size is modeled by considering piece-wise production cost functions in different echelons of the network. Our numerical results inspired by the case of tunable lasers indicate that the configuration of supply network varies as a function of the demand at different design complexity levels. Whereas, the profitability of supply network is closely tied to the market condition as well as the production capacity, flexibility of processes, and cost structure of manufacturers.

关键词： Supply network design Mass personalization Industry 4 0 design complexity Mixed-integer-programming Tunable lasers

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：