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Verification of Periodicity of Exons in DNA using digital signal processor (TMS320C6748)

Procedia Computer Science 2025年 259卷 1612-1618页

作者： Neelapala Anil Kumar Ankita Manjayya Naik Chirayu P Krithika Deepa J Shetty Gnane Swarnadh Satapathi Manisa Panda G S Pradeep Ghantasala 1Department of Electronics and Communication Engineering Alliance University Karnataka India 562 106 Department of Electronics and Communication Engineering A J Institute of Engineering and Technology Karnataka India 575 006

The periodicities present in genomic sequences are mainly responsible for the structure and function of DNA signals. It is primarily a three-base periodicity that has had to be intrinsic to protein-coding regions, as it is used for the placement of exons in eukaryotic DNA sequences. digital signal processing (DSP) methods used are Discrete Fourier Transform (DFT) and Artificial Neural Network (ANF)-based techniques, that detect the exons and introns within the gene by utilizing its three-base periodicity property in the spectral domain. Various other methods, which are also based upon this peculiar feature, have grown during the last two decades. Yet, their validity has not, though, been demonstrated in a DSP processor. This paper compares base-3 periodicity in the exons of DNA by using different values of Electron-ion interaction pseudopotential (EIIP), proved by the implementation on digital signal processor (TMS320C6748) and are compared with Ryzen 5 processor results.

关键词： DNA digital signal processor Exons Fourier transform

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digital signal processor-based real-time optical Doppler tomography system

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JOURNAL OF BIOMEDICAL OPTICS 2004年第3期9卷 454-463页

作者： Yan, SK Piao, DQ Chen, YL Zhu, Q Univ Connecticut Elect & Comp Enmgn Dept Storrs CT 06269 USA

We present a real-time data-processing and display unit based on a custom-designed digital signal processor (DSP) module for imaging tissue structure and Doppler blood flow. The DSP module is incorporated into a conventional optical coherence tomography system. We also demonstrate the flexibility of embedding advanced Doppler processing algorithms in the DSP module. Two advanced velocity estimation algorithms previously introduced by us are incorporated in this DSP module. Experiments on Intralipid flow demonstrate that a pulsatile flow of several hundred pulses per minute can be faithfully captured in M-scan mode by this DSP system. In vivo imaging of a rat's abdominal blood flow is also presented. (C) 2004 Society of Photo-Optical Instrumentation Engineers.

关键词： optical Doppler tomography digital signal processor

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digital signal processor against field programmable gate array implementations of space-code correlator beamformer for smart antennas

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IET MICROWAVES ANTENNAS & PROPAGATION 2010年第5期4卷 593-599页

作者： Dikmese, S. Kavak, A. Kucuk, K. Sahin, S. Tangel, A. Dincer, H. Tampere Univ Technol Dept Commun Engn FIN-33101 Tampere Finland Kocaeli Univ Wireless Commun & Informat Syst Res Ctr Dept Comp Engn Kocaeli Turkey Kocaeli Univ Dept Elect & Comp Educ Kocaeli Turkey Kocaeli Univ Dept Elect & Commun Engn Kocaeli Turkey

Software radio implementations of beamformers on programmable processors such as digital signal processor (DSP) and field programmable gate array (FPGA) still remain as a challenge for the integration of smart antennas into existing wireless base stations for 3G systems. This study presents the comparison of DSP- and FPGA-based implementations of space–code correlator (SCC) beamformer, which is practical to use in CDMA2000 systems. Implementation methodology is demonstrated and results regarding beamforming accuracy, weight vector computation time (execution time) and resource utilisation are presented. The SCC algorithm is implemented on Texas Instruments (TI) TMS320C6713 floating-point digital signal processors (DSPs) and Xilinx's VirtexIV family FPGA. In signal modelling, CDMA2000 reverse link format is employed. The results show that beamformer weights can be obtained within less than 10 ms via implementation on c6713 DSP with direction-of-arrival (DOA) search resolution of Δthetas=2°, whereas it can be achieved within less than 25 µs on VirtexIV FPGA for five-element uniform linear array (ULA). These results demonstrate that FPGA implementation achieves weight vector computation in much smaller time (nearly 500 times) as compared to DSP implementation in this study.

关键词： smart antennas weight vector computation time Logic circuits space-code correlator beamformer signal processing and detection uniform linear array direction-of-arrival search Mobile radio systems wireless base stations adaptive antenna arrays Microprocessors and microcomputers field programmable gate arrays 3G mobile communication digital signal processor Antenna arrays array signal processing digital signal processing chips beamforming accuracy CDMA2000 reverse link format 3G systems direction-of-arrival estimation linear antenna arrays Semiconductor integrated circuits software radio

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digital signal processor-Based Broad Null Beamforming for Interference Reduction

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CIRCUITS SYSTEMS AND signal PROCESSING 2016年第1期35卷 211-231页

作者： Venkataramana, D. Sanyal, S. K. Misra, Iti Saha Jadavpur Univ Dept Elect & Telecommun Engn Kolkata 700032 India

Shaping the radiation pattern of an antenna array to null the reception (or radiation in the case of transmitting antenna) in the direction of undesired interferences has become essential in the environment of electromagnetic interferences. This paper proposes a digital signal processor-based method using space-selective digital filter with Blackman window to nullify the broad interferences of a linear array along with its implementation. Convolution between array weight vector and filter coefficients of digital filter is performed to obtain the desired beam pattern. The cutoff points of the filter and hence the array weight vector are updated adaptively so as to obtain the desired attenuation in the vicinity of mean broad interfering direction . The even symmetry of the modified weight vector about its center is utilized to minimize the computational burden. The proposed model offers advantages such as more than 80-dB attenuation to broad interferences and lesser computational time with respect to conventional processor. Numerical results are presented to justify the performance of the proposed method for nullifying the interferences that are arriving over a nulling range between and . The vicinity considered in the proposed model varies between and . Exhaustive performance analysis is also provided with different directions of arrivals and desired attenuations for effective suppression of interference.

关键词： Discrete space fourier transform (DSFT) Linear convolution digital filter digital signal processor Array factor Broad nulling

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digital signal processor controlled auxiliary commutated pole converter for high-performance motor drives applications

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POWER ENGINEERING JOURNAL 2000年第1期14卷 5-11页

作者： Pickert, V Johnson, CM Univ Newcastle Upon Tyne Dept Elect & Elect Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England Volkswagen AG Wolfsburg Germany

Resonant and soft-switched inverter drives offer the potential for increased switching frequencies, reduced weight and lower levels of electromagnetic interference when compared to conventional hard-switched drives. Regrettably, low-cost, soft-switching topologies such as resonant link designs suffer from poor control performance while others, such as the ACPI, have a high component count and relatively complex control structures. A low-cost commutation control scheme is proposed for the ACPI, which uses a digital signal processor to determine the optimum switching instants for both auxiliary and main devices. Results are presented comparing the performance of the DSP controlled ACPI with an equivalent hard-switched converter.

关键词： digital signal processor a.c. machines digital signal processing chips soft-switching inverter drives Microprocessors and microcomputers voltage control AC motor drives Power convertors and power supplies to apparatus PWM power convertors Power engineering computing digital signal processing chips Drives digital control applications Voltage control high-performance motor drives auxiliary commutated pole converter commutation Control of electric power systems Optimal control switching frequencies power engineering computing electromagnetic interference optimum switching instants switching circuits optimal control AC-AC power convertors Control engineering computing machine control AC/AC power conversion

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digital signal processor implementation and performance evaluation of split capacitor, four-leg and three H-bridge-based three-phase four-wire shunt active filters

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IET POWER ELECTRONICS 2011年第4期4卷 463-470页

作者： Khadkikar, V. Chandra, A. Singh, B. Masdar Inst Elect Power Engn Program Abu Dhabi U Arab Emirates Univ Quebec Dept Elect Engn Ecole Technol Super Montreal PQ H3C 3P8 Canada Indian Inst Technol Delhi Dept Elect Engn New Delhi 110016 India

In this paper a comprehensive study on the three-phase four-wire (3P4W) shunt active power filter (APF) is carried out on the basis of three system configurations. These three two-level voltage source inverter topologies are compared for 3P4W shunt APF, namely, split capacitor (2C), four-leg (4L) and three single-phase H-bridges (3HB). The performance of all three topologies, under an unbalanced non-linear load condition, is evaluated with a detailed digital signal processor (DSP)-based experimental investigation. The steady-state as well as dynamic performance of APF is studied to compensate for current harmonics, reactive power, current unbalance and neutral current. The advantages and limitations offered by each of the topologies are also discussed in brief.

关键词： Other power apparatus and electric machines unbalanced nonlinear load condition 3P4W shunt APF Power supply quality and harmonics power harmonic filters invertors reactive power four-leg H-bridge-based three-phase four-wire shunt active filters digital signal processing chips active filters power capacitors two-level voltage source inverter topology Power convertors and power supplies to apparatus digital signal processor load (electric) digital signal processing chips current harmonics neutral current split capacitor performance evaluation

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Total Ionizing Dose Effect and Failure Mechanism of digital signal processor

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Chinese Journal of Electronics 2021年第5期30卷 986-990页

作者： YU Xin LU Wu LI Xiaolong LIU Mohan WANG Xin SUN Jing GUO Qi Xinjiang Technical Institute of Physics and Chemistry Laboratory of Solid State Radiation Physics

Ionizing radiation effect and failure mechanism of digital signal processor(DSP) is studied through test-board and automatic test equipment to find the relationship between system function failure and parameter degradation. Static bias is more sensitive than dynamic bias when DSP is tested on-line during radiation. Core current, high-Z leakage current and timing parameter are sensitive to ionizing radiation. No enhanced low-dose-rate sensitivity is found by comparing experiment results under high and low dose rate *** memory interface and Timer are deduced to be the sensitive module by step radiation and analysis basing full parameter test in Verigy 93000. The timing parameter degradation have a strong correlation to these module functions. And the degeneration mechanism is analysed on inverter through Hspice simulation which indicate the leakage circuit caused by radiation can lead a delay to the digital signal propagating. The parasitical capacitance among long connections make it worse to the data transmission around DSP, field programmable gate array and memory. Then an early function failure occurs in test board than Verigy 93000. This work provide support to systematic radiation hardness design and hardness assurance/lot acceptance testing in space applications.

关键词： Verigy 93000 analysis basing full parameter test digital signal propagating radiation effect radiation effects DSP external memory interface leakage currents early function failure leakage circuit test board sensitive module system function failure high dose rate radiation static bias automatic test equipment timing parameter degradation low dose rate radiation field programmable gate array enhanced low-dose-rate sensitivity digital signal processor degeneration mechanism systematic radiation hardness design radiation hardening (electronics) field programmable gate arrays integrated circuit testing ionizing radiation dynamic bias module functions step radiation digital signal processing chips failure mechanism test-board

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An intelligent detector based on temperature modulation of a gas sensor with a digital signal processor

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SENSORS AND ACTUATORS B-CHEMICAL 2001年第1-3期78卷 32-39页

作者： Ortega, A Marco, S Perera, A Sundic, T Pardo, A Samitier, J Univ Barcelona Instrumentat & Commun Lab Barcelona 08028 Spain

An intelligent detector based on a hot-plate gas sensor and a digital signal processor (DSP) is presented. The work comprises sensor measurements and Ps identification with a pattern recognition (PARC) system along with a systematic verification of both stages, thanks to clustering validity methods and performance tests. Commercial silicon micromachined tin-oxide sensors have been used to capture dynamic measurements modulating the sensor heater at different temperatures, waveforms and frequencies. Feature extraction is based on the spectral and transient analysis of the sensor output signals. The PARC systems are based on self-organizing maps (SOM) and recent variations of these well-known neural networks. The proposed hardware is in charge of the whole system: the sensor temperature modulation and signal processing. (C) 2001 Elsevier Science B.V. All rights reserved.

关键词： gas detection hot-plate sensors temperature modulation clustering validation digital signal processor

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An optical tomography system using a digital signal processor

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SENSORS 2008年第4期8卷 2082-2103页

作者： Rahim, Ruzairi Abdul Thiam, Chiam Kok Rahiman, Mohd Hafiz Fazalul Univ Teknol Malaysia Fac Elect Engn Control & Instrumentat Engn Dept Skudai 81310 Johor Bahru Malaysia Univ Malaysia Perlis Sch Mechatron Engn Arau 02600 Perlis Malaysia

The use of a personal computer together with a Data Acquisition System ( DAQ) as the processing tool in optical tomography systems has been the norm ever since the beginning of process tomography. However, advancements in silicon fabrication technology allow nowadays the fabrication of powerful digital signal processors ( DSP) at a reasonable cost. This allows this technology to be used in an optical tomography system since data acquisition and processing can be performed within the DSP. Thus, the dependency on a personal computer and a DAQ to sample and process the external signals can be reduced or even eliminated. The DSP system was customized to control the data acquisition process of 16x16 optical sensor array, arranged in parallel beam projection. The data collected was used to reconstruct the cross sectional image of the pipeline conveyor. For image display purposes, the reconstructed image was sent to a personal computer via serial communication. This allows the use of a laptop to display the tomogram image besides performing any other offline analysis.

关键词： optical tomography digital signal processor image reconstruction

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RNS-enabled digital signal processor design

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ELECTRONICS LETTERS 2002年第6期38卷 266-268页

作者： Ramírez, J García, A López-Buedo, S Lloris, A Dept Elect & Tecnol Comp E-18071 Granada Spain Univ Autonoma Madrid Dept Ingn Informat E-28049 Madrid Spain

Residue number system (RNS) is explored for implementation of fast digital signal processors with the design of an RNS-based SIMD RISC processor. Simulations conducted on programmable logic show a I sustained advantage over commercial chips for a representative set of applications, while prospective results on VLSI technology are also promising.

关键词： digital signal processor integrated circuit design programmable logic devices VLSI reduced instruction set computing residue number systems digital arithmetic methods programmable logic SIMD RISC processor Microprocessors and microcomputers digital circuit design, modelling and testing digital signal processing chips parallel architectures digital signal processing chips residue number system design simulation VLSI technology

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