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23rd Chinese Control and Decision Conference

作者： Xu, Cong Dong, Feng Zhang, Zhiqiang Tianjin Univ Tianjin Key Lab Proc Measurement & Control Sch Elect Engn & Automat Tianjin 300072 CO Peoples R China

ISBN: (纸本)9781424487363

The digital FIR filter is widely used in electronic instruments. It is the time delay of the filter that affects the real-time performance of the conventional ERT system. This paper discusses the advantages of applying the distributed digital FIR filter in ERT system. Compared with the traditional filter, both the SNR and the channel consistence were improved to some extent. More importantly, the real-time performance has been improved;especially the data acquisition rate is increased from 600 frames per second to 1040 frames per second for the sixteen electrode system.

关键词： Digital filter FIR distributed arithmetic ERT

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distributed arithmetic Based Filters for Satellite Video Signals Demodulation

Distributed Arithmetic Based Filters for Satellite Video Sig...

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2nd IEEE International Conference on Communications and Signal Processing (ICCSP)

作者： Srividya, P. Nataraj, K. R. Rekha, K. R. Visvesvaraya Technol Univ Belgaum Karnataka India

ISBN: (纸本)9781467348669;9781467348652

the paper proposes a method to use distributed arithmetic (DA) based filters to demodulate video signals on satellites. The demodulator uses a mixer, carrier recovery circuit, symbol recovery circuit and a Root raised cosine filter designed on DA based technique to implement the algorithm. Typical binary digital rates for digitized video are 3-4Mbps. To demodulate such signals, the number of MAC operations required by the filter is more. DA usage eliminates the need of multipliers when implementing MAC. This increases the operational speed and results in high filter throughput. The basic blocks of the demodulator are designed using VHDL and synthesized using Xilinx ISE 10.1.

关键词： Demodulation Digital filters distributed arithmetic On board processing satellites

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distributed arithmetic based implementation of Fourier transform targeted at FPGA architectures

Distributed arithmetic based implementation of Fourier trans...

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14th International Conference on Mixed Design of Integrated Circuits and Systems

作者： Rawski, M. Wojtynski, M. Wojciechowski, T. Majkowski, P. Warsaw Univ Technol PL-00661 Warsaw Poland

ISBN: (纸本)9788392263241

Discrete Fourier transform is recognized as one of the basic digital signal processing operations. One of the most efficient methods of performing this transformation is fast Fourier transform (FFT). It has been showed that no algorithm for computing the DFT could have a smaller complexity than the FFT. Thus most FPGA implementations are based on this approach. With the introduction of specialized DSP blocks embedded into programmable architectures the efficiency of FFT is limited by the speed of hardware multipliers of DSP modules. However, programmable architectures provide possibility to increase the performance of digital system by exploitation of parallelisms of implemented algorithms. In this paper application of distributed arithmetic concept to DFT implementation is described. Results showing the performance improvement in comparison to FFT implementation is shown.

关键词： Fourier transform distributed arithmetic logic synthesis FPGA technology mapping

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Versatile Quaternion Multipliers Based on distributed arithmetic

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2018年第11期37卷 4880-4906页

作者： Parfieniuk, Marek Park, Sang Yoon Bialystok Tech Univ Dept Digital Media & Comp Graph Wiejska 45A PL-15351 Bialystok Poland Myongji Univ Dept Elect Engn Yongin 17058 South Korea

This paper introduces the idea of versatile circuits for multiplying 4-dimensional hypercomplex numbers in hardware. Depending on the settings of such a device, a variable quaternion can be left- or right-multiplied by aconstant coefficient or by its conjugate, as various operations are useful in transform-type algorithms. Multiplierless circuits based on distributed arithmetic (DA) are reviewed that compute quaternion products by additions and bit shifts. It is shown that they can be made versatile by extending memory of partial results, but a better solution is our method for preprocessing bits used to address this memory. The method allows for using the same partial results to compute different inner products that are related to a quaternion multiplication. So versatile multipliers can be implemented with memory optimized so as to save area or to speed up reprogramming compared to the basic DA-based circuit. This has been demonstrated by hardware design experiments, which show that 13-69% area can be saved in a case of ASIC implementation, while for FPGA implementation, spending only 11% more logic resources allows a multiplier to be reprogrammed 75% faster. Additionally, it has been explained how versatile multipliers can be used to realize low-area analysis/synthesis filter banks.

关键词： Quaternion Hypercomplex Multiplier distributed arithmetic FPGA Circuit

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Efficient Real-Time Digital Subcarrier Cross-Connect (DSXC) Based on distributed arithmetic DSP Algorithm

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2020年第13期38卷 3495-3505页

作者： Xu, Tong Fumagalli, Andrea Hui, Rongqing Univ Kansas Dept Elect Engn & Comp Sci Lawrence KS 66044 USA Univ Texas Dallas Erik Jonsson Sch Engn & Comp Sci Richardson TX 75083 USA

Two real-time functions of digital subcarrier cross-connect (DSXC) are experimentally demonstrated for the first time using distributed arithmetic (DA) in a field programmable gate array (FPGA) platform. Both frequency translation and channel selection in DSXC are implemented using DA-based resampling filters, achieving flexible modulation format and fine data-rate granularity of many concurrent subcarrier channels. Compared with traditional resampling filters that leverage multipliers, the DA-based approach eliminates the need for DSP slices in the FPGA implementation and significantly reduces the hardware cost. By requiring only a few clock periods, the DA-based resampling filter is also significantly faster when compared to conventional FIR filters, whose overall latency is proportional to the filter order. The DA-based DSXC is therefore able to achieve improved spectral efficiency and programmability of multiple orthogonal subcarrier channels, while keeping low cross-connection latency and requiring low cost hardware resources when implemented in a FPGA platform.

关键词： Finite impulse response filters Optical filters Field programmable gate arrays OFDM Real-time systems Table lookup distributed arithmetic DSXC FPGA frequency translation resampling filter

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Unified systolic-Like architecture for DCT and DST using distributed arithmetic

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2006年第12期53卷 2656-2663页

作者： Meher, Pramod Kumar Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

A common computing-core representation of the discrete cosine transform and discrete sine transform is derived and a reduced-complexity algorithm is developed for computation of the proposed computing-core. A parallel architecture based on the principle of distributed arithmetic is designed further for the computation of these transforms using the common-core algorithm. The proposed scheme not only leads to a systolic-like regular and modular hardware for computing these transforms, but also offers significant improvement in area-time efficiency over the existing structures. The structure proposed here is devoid of complicated input/output mapping and does not involve any complex control. Unlike the convolution-based structures, it does not restrict the transform length to be a prime or multiple of prime and can be utilized as a reusable core for cost-effective, memory-efficient, high-throughput implementation of either of these transforms.

关键词： digital signal processing chip discrete cosine transform (DCT) discrete sine transform (DST) distributed arithmetic systolic array VLSI

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FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures

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MICROELECTRONICS JOURNAL 2010年第6期41卷 365-370页

作者： Xie, Jiafeng He, Jianjun Tan, Guanzheng Cent S Univ Sch Informat Sci & Engn Changsha 410083 Hunan Peoples R China

This paper presents the design optimization of fully pipelined architectures for area-time-power-efficient implementation of finite impulse response (FIR) filter. The architectures are designed to obtain a suitable area-time tradeoff. Analysis of the performance of different filter orders and different address lengths of partial tables indicate the choice of four input partial tables presents the best of area-time-power-efficient realizations of FIR filter compared with the existing LUT-less DA-based implementations of FIR filters in both high-speed and medium-speed. Moreover, a number of further experiments not only shows the pipeline register's significant influence to the maximum frequency of the FIR filters but also indicates it also has area usage. Final experiment shows that with the help of using pipeline register, the choice of 4-bits-per-clock (4BPC) of the architecture for word-length N=8 with four input partial table yields the best cost-effective when comparing with other different cases in both highspeed and medium-speed implementations. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： distributed arithmetic Field programmable gate arrays (FPGA) Finite impulse response (FIR) filter Modified solution

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A modular approach to the computation of convolution sum using distributed arithmetic principles

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 1999年第1期46卷 92-96页

作者： Lim, KP Premkumar, AB Nanyang Technol Univ Sch Appl Sci Singapore 2263 Singapore

Inner product evaluation can be considered to be basic to all digital signal processing algorithms. distributed arithmetic (DA) is a bit serial memory-oriented method that implements inner products. In DA, memory increases exponentially as the number of coefficients increases, This deters the use of DA in the implementation of DSP algorithms. This paper explores the possibility of combining DA principles with the residue number system (RNS) to exploit the advantages of both. ii new technique for the computation of the inner product in the RNS domain using modular multipliers and DA principles is proposed, The resulting architecture is elegant, uses minimum memory and adders, and hence is VLSI efficient, The proposed architecture is extremely efficient in terms of speed and does not involve conversion of data into residues although computation is performed in residue domain.

关键词： distributed arithmetic modular multiplier residue number system

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A cost-efficient error-resilient approach to distributed arithmetic for signal processing

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MICROELECTRONICS RELIABILITY 2019年 93卷 16-21页

作者： Lu, Yue Duan, Shengyu Halak, Basel Kazmierski, Tom J. Univ Southampton Elect & Comp Sci Southampton SO17 1BJ Hants England

distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, a new error resilient technique for DA computation is proposed to improve robustness against process, voltage, and temperature variations. The proposed approach mitigates the effect of timing violations by first providing a guardband for significant (most significant bit) computations. This guardband is initially achieved by modifying the order of DA serial operations and borrowing time from the least significant bit (ISB) group. Therefore, LSB computation can correspond to the critical path, and timing error can be tolerated at the cost of acceptable accuracy loss. Moreover, the shifted-phase clock signals are applied on the end-point registers, thereby increasing the global guardband without any effect on system sampling rate. Our approach is demonstrated on a 16-tap FIR filter using the 65 nm CMOS process. The simulation results demonstrate that this design can maintain error-free operation without worst case timing margin, and achieve up to 42% power savings by voltage scaling when the worst case margin is considered. This is at the cost of a 6.3% delay and 7.3% overhead.

关键词： Error-resilience distributed arithmetic Digital signal processing Timing violation

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A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic

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INTEGRATION-THE VLSI JOURNAL 2016年 54卷 37-46页

作者： Mohanty, Basant Kumar Meher, Pramod Kumar Singhal, Subodh Kumar Swamy, M. N. S. Jaypee Univ Engn & Technol Raghogarh Madhya Pradesh India Nanyang Technol Univ Sch Comp Engn Nanyang Ave Singapore 639798 Singapore Concordia Univ Dept Elect & Comp Engn Montreal PQ H3G 2W1 Canada

In this paper, we have analyzed the register complexity of direct-form and transpose-form structures of FIR filter and explored the possibility of register reuse. We find that direct-form structure involves significantly less registers than the transpose-form structure, and it allows register reuse in parallel implementation. We analyze further the LUT consumption and other resources of DA-based parallel FIR filter structures, and find that the input delay unit, coefficient storage unit and partial product generation unit are also shared besides LUT words when multiple filter outputs are computed in parallel. Based on these finding, we propose a design approach, and used that to derive a DA-based architecture for reconfigurable block-based FIR filter, which is scalable for larger block-sizes and higher filter-lengths. Interestingly, the number of registers of the proposed structure does not increase proportionately with the block-size. This is a major advantage for area-delay and energy efficient high-throughput implementation of reconfigurable FIR filters of higher block-sizes. Theoretical comparison shows that the proposed structure for block-size 8 and filter-length 64 involves 60% more flip-flops, 6.2 times more adders, 3.5 times more AND-OR gates, and offers 8 times higher throughput. ASIC synthesis result shows that the proposed structure for block-size 8 and filter-length 64 involves 1.8 times less area-delay product (ADP) and energy per sample (EPS) than the existing design, and it can support 8 times higher throughput. The proposed structure for block sizes 4 and 8, respectively, consumes 38% and 50% less power than the exiting structure for the same throughput rates on average for different supply voltages. (C) 2016 Elsevier B.V. All rights reserved.

关键词： Reconfigurable architecture Block processing distributed arithmetic VLSI

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