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Optimizing the matrix multiplication parallel algorithms on a distributed-memory MIMD multiprocessor

Parallel Algorithms and Applications 1994年第4期2卷 291-303页

作者： Garg, Sharad Sholl, Howard A. Ammar, Reda A. Department of Computer Science and Engineering University of Connecticut Storrs CT 06269 United States

In the past few years, there have been significant developments in the area of distributed and parallel processing. More powerful and new hardware architectures are being produced at a rapid rate, such as distributed-memory MIMD computers, which have provided enormous computing power to the software engineers. These multiprocessors may provide a significant speed-up over the serial execution of an algorithm. However, this requires careful partitioning and allocation of data and control to the processor set. Matrix multiplication is a fundamental parallel algorithm which can be effectively executed on a distributed-memory multiprocessor and can show significant improvement in the speed-up over the serial execution. Ideally, we should be able to achieve a linear speed up with increase in the number of processors, but in practice the speed up is much less, and in fact increasing the number of processors beyond a certain number may result in degradation of the completion time. This degradation is caused by increased communications between modules. Therefore, the optimum speed-up is a function of the number of processors and the communication cost. To find the optimum performance, a user need to experiment with all the available processors on a multiprocessor. In this paper, we studied the detailed performance of the parallel matrix multiplication algorithm. The study defines the factors that control the performance of this class of algorithms and shows how to use these factors to optimize the algorithm’s execution time. Also, an analytic approach is described which can eliminate a trial and effort method to actually determine the size of processor set. © 1994, Taylor & Francis Group, LLC. All rights reserved.

关键词： distributed-memory multiprocessor finest granularity message passing parallel algorithms

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AN EFFICIENT MAPPING OF BOLTZMANN MACHINE COMPUTATIONS ONTO distributed-memory multiprocessorS

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1992年第4期33卷 223-236页

作者： OH, DH NANG, JH YOON, H MAENG, SR KOREA ADV INST SCI & TECHNOL DEPT COMP SCIYUSUNG KUTAEJON 305701SOUTH KOREA KOREA ADV INST SCI & TECHNOL CTR ARTIFICIAL INTELLIGENCE RESYUSUNG KUTAEJON 305701SOUTH KOREA

In this paper, an efficient mapping scheme of Boltzmann Machine computations onto a distributed-memory multiprocessor, which exploits the synchronous spatial parallelism, is presented. In this scheme, the neurons in the Boltzmann Machine are partitioned into p disjoint sets, and each set is mapped on a processor of a p-processor system. A parallel convergence and learning algorithms of Boltzmann Machine, necessary communication pattern among the processors, and their time complexities when neurons are partitioned and mapped onto a distributed-memory multiprocessor are investigated. An expected p-processor speed-up of the parallelizing scheme over a single processor is also analyzed theoretically. It can be used as a basis in determining the most cost-effective or optimal number of processors with respect to the communication capabilities and interconnection topologies of given distributed-memory multiprocessor.

关键词： NEURAL NETWORK BOLTZMANN MACHINE PARALLEL CONVERGENCE ALGORITHM PARALLEL LEARNING ALGORITHM PARALLEL PROCESSING distributed-memory multiprocessor SPEED-UP ANALYSES

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PARALLEL SIMULATION OF MULTILAYERED NEURAL NETWORKS ON distributed-memory multiprocessorS

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1990年第3期29卷 185-195页

作者： YOON, H NANG, JH MAENG, SR KOREA INST SCI & TECHNOL DEPT COMP SCI SEOUL 130650 SOUTH KOREA

In this paper, we present a parallel simulation of a fully connected multilayered neural network using the backpropagation learning algorithm on a distributed-memory multiprocessor system. In our system, the neurons on each layer are partitioned into p disjoint sets and each set is mapped on a processor of a p -processor system. A fully distributed backpropagation algorithm, necessary communication pattern among the processors, and their time/space complexities are investigated. The p -processor speed-up of the backpropagation algorithm over a single processor is also analyzed theoretically which can be used as a basis in determining the most cost-effective or optimal number of processors. The experimental results with a network of Transputers are also presented to demonstrate the usefulness of our system.

关键词： Neural network Parallel processing Backpropagation algorithm distributed-memory multiprocessor Performance analysis

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Parallelization of Multilevel ILU Preconditioners on distributed-memory multiprocessors

Parallelization of Multilevel ILU Preconditioners on Distrib...

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10th Nordic International Conference on Applied Parallel Computing - State of the Art in Scientific and Parallel Computing (PARA)

作者： Aliaga, Jose I. Bollhoefer, Matthias Martin, Alberto F. Quintana-Orti, Enrique S. Univ Jaume 1 Dpto Ingn & Ciencia Computadores Castellon de La Plana Spain TU Braunschweig Inst Computat Math Braunschweig Germany

ISBN: (纸本)9783642281501;9783642281518

In this paper we investigate the parallelization of the ILUPACK library for the solution of sparse linear systems on distributed-memory multiprocessors. The parallelization approach employs multilevel graph partitioning algorithms in order to identify a set of concurrent tasks and their dependencies, which are then statically mapped to processors. Experimental results on a cluster of Intel QuadCore processors report remarkable speed-ups.

关键词： Sparse linear system iterative solver preconditioner ILU decomposition MPI distributed-memory multiprocessor

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A framework for integrating data alignment, distribution, and redistribution in distributed memory multiprocessors

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IEEE TRANSACTIONS ON PARALLEL AND distributed SYSTEMS 2001年第4期12卷 416-431页

作者： Garcia, J Ayguadé, E Labarta, J Univ Politecn Cataluna Comp Architecture Dept ES-08034 Barcelona Spain

Parallel architectures with physically distributed memory provide a cost-effective scalability to solve many large scale scientific problems. However, these systems are very difficult to program and tune. In these systems, the choice of a good data mapping and parallelization strategy can dramatically improve the efficiency of the resulting program. In this paper, we present a framework for automatic data mapping in the context of distributed memory multiprocessor systems. The framework is based on a new approach that allows the alignment, distribution, and redistribution problems to be solved together using a single graph representation. The Communication Parallelism Graph (CPG) is the structure that holds symbolic information about the potential data movement and parallelism inherent to the whole program. The CPG is then particularized for a given problem size and target system and used to find a minimal cost path through the graph using a general purpose linear 0-1 integer programming solver. The data layout strategy generated is optimal according to our current cost and compilation models.

关键词： automatic data mapping alignment distribution redistribution performance prediction distributed-memory multiprocessor loop parallelization linear 0-1 integer programming

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THE COST OF EIGENVALUE COMPUTATION ON distributed-memory MIMD multiprocessorS

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PARALLEL COMPUTING 1995年第3期21卷 401-422页

作者： CRIVELLI, S JESSUP, ER UNIV COLORADO DEPT COMP SCI BOULDER CO 80309 USA

In [20], Simon proves that bisection is not the optimal method for computing an eigenvalue on a single vector processor. In this paper, we show that his analysis does not extend in a straightforward way to the computation of an eigenvalue on a distributed-memory MIMD multiprocessor. In particular, we show how the optimal number of sections (and processors) to use for multisection depends on variables such as the matrix size and the ratio of communication and computation costs. We also show that parallel multisection outperforms the variant of parallel bisection called polysection proposed by Swarztrauber in [22] for this problem on a distributed-memory MIMD multiprocessor. We present the results of experiments on the 64-processor Intel iPSC/2 hypercube and the 512-processor Intel Touchstone Delta mesh multiprocessor.

关键词： LINEAR ALGEBRA EIGENVALUE COMPUTATION distributed-memory multiprocessor BISECTION MULTISECTION POLYSECTION INTEL IPSC/2 INTEL TOUCHSTONE DELTA

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IMPLEMENTATION OF A MULTIGRID ALGORITHM ON SUPRENUM AND OTHER SYSTEMS

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PARALLEL COMPUTING 1994年第10-11期20卷 1547-1557页

作者： ALEF, M Kernforschungszentrum Karlsruhe GmbH Hauptabteilung Daten- und Informationsverarbeitung Postfach 36 40 D-76021 Karlsruhe Germany

In this paper the implementation of a multigrid algorithm on massively parallel computers and on a workstation cluster is described. The model problem discussed in this paper is the solution of the Poisson equation in boundary-fitted coordinates using a 9-point difference operator with variable coefficients. In principle, these ideas are also valid for other multigrid method. Measurements of the multiprocessor efficiency and experiences are presented for SUPRENUM, for the Intel iPSC/2, and for a cluster of workstations.

关键词： distributed-memory multiprocessor HYPERCUBE MIMD MULTICOLOR RELAXATION MULTIGRID METHOD multiprocessor EFFICIENCY PVM SUPRENUM WORKSTATION CLUSTER

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A TRIDIAGONAL SOLVER FOR MASSIVELY PARALLEL COMPUTER-SYSTEMS

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PARALLEL COMPUTING 1990年第2-3期16卷 361-368页

作者： REALE, F Osservatorio Astronomico di Palermo Palermo Italy

This paper describes a parallel solver of tridiagonal systems appropriate for distributed memory computers and implemented on an array of chain-connected T800 Transputers. Each processor in the chain uses the same program to solve its own subset of equations. This implementation is suited, for instance, for solving the heat conduction equation in one-dimensional hydrodynamic codes. The procedure performs a parallel cyclic reduction, a recursive Gaussian elimination on a reduced number of equations and a parallel backward unfolding scheme, with a direct substitution in the reduced equations. The code has been written in Occam2 language. A one-way communication of values between adjacent processors is required at each cycle of both the reduction and the unfolding steps. Due to the number of floating point operations and the amount of communications the implementation described here works efficiently on arrays with more than 4 processors and for more than approximately 15 equations per processor.

关键词： TRIDIAGONAL LINEAR SYSTEMS PARALLEL CYCLIC REDUCTION IMPLEMENTATION FEATURES distributed-memory multiprocessor TRANSPUTER ARRAY

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An integrated performance analysis tool for SPMD data-parallel programs

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PARALLEL COMPUTING 1997年第8期23卷 1089-1112页

作者： Singh, A VanDongen, V CTR RECH INFORMAT MONTREAL PARALLEL ARCHITECTURE GRP MONTREAL PQ H3A 2N4 CANADA

A new generation of data parallel languages have been proposed whereby a user specifies how data structures are to be distributed amongst the processor nodes of a distributed-memory machine. Based on this information, the compiler then generates code for the parallel application. Although this approach significantly simplifies the development of the initial version of a parallel application, selection of good data distributions leading to efficient computations is often quite difficult. Therefore, performance debuggers are needed to yield insights into the data distribution effects. On the other hand, most of the existing approaches to performance debugging are very general and thus do not provide the user feedback in terms of the high level programming model or the source code of the parallel application. In this paper, we describe a novel approach to performance debugging of data parallel programs. The design and implementation of a visual performance debugger is described that is specifically targeted to meet the performance debugging requirements of a data-parallel programming model based on user-specified data distributions. The performance debugger is part of an integrated programming environment, called EPPP, which also supports a data parallel compiler and a parallel architecture simulator. Thus development and performance debugging of an application may be done either on the real hardware or by using the simulator. The code for EPPP can be obtained free of cost (contact web address, http://***/apar).

关键词： parallel programming distributed-memory multiprocessor data distribution performance debugger programming environment

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CONCEPTS FOR EFFICIENT MULTIGRID IMPLEMENTATION ON SUPRENUM-LIKE ARCHITECTURES

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PARALLEL COMPUTING 1991年第1期17卷 1-16页

作者： ALEF, M Kernforschungszentrum Karlsruhe GmbH Abteilung Numerische Physik (HDI 3) Postfach 36 40 W-7500 Karlsruhe 1 Germany

The implementation of algorithms on distributed-memory multiprocessors requires regular exchange of certain intermediate results between the parallel processes. The less data that must be moved the more efficient the parallelization is. In this paper, concepts for efficient implementation of multigrid methods with regular grid structure are presented for the example of the SUPRENUM supercomputer. The main idea is the introduction of an optimized 'multicolor' relaxation scheme, combined with an adapted agglomeration technique. The speedup to be expected on SUPRENUM is discussed for the example of the solution of the Poisson equation in boundary-fitted coordinates.

关键词： AGGLOMERATION distributed-memory multiprocessor MIMD MULTICOLOR RELAXATION MULTIGRID METHOD multiprocessor EFFICIENCY PARALLELIZATION SUPRENUM

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