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AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded Applications 10

AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded A...

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10th Nordic Circuits and Systems Conference

作者： Othman, Ahmad Kamaleldin, Ahmed Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany

ISBN: (纸本)9798331517663;9798331517670

The rapid expansion of the Internet of Things, wireless sensor networks, and robotics applications have established embedded systems as a fundamental component of modern computing. Despite this growth, optimizing power consumption and computing resources remains critical. Traditional embedded platforms often struggle with fixed hardware configurations that limit their adaptability and efficiency. To address these issues, this paper presents a novel adaptive processor architecture based on RISC-V ISA which introduces reconfigurable execution regions capable of supporting mixed-precision operations (16/8/4-bit). These reconfigurable execution regions execute and continuously adapt to varying precision and operational demands triggered by custom RISC-V instructions that activate the desired region at specific precision levels. The reconfiguration process is managed through dynamic function exchange (DFX) targeting AMD/Xilinx XCZU7EV FPGA device. The evaluation demonstrates that the modified core efficiently utilizes FPGA resources, with 6,396 LUTs and 2,679 FFs allocated, and operates with a dynamic power consumption of 24 mW at 50 MHz. The reconfiguration time is 76 ms for each reconfiguration execution region, incorporating the overhead required for reconfiguration management and control. These results highlight the core's potential to allow the realization of RISC-V-based reconfigurable cores without degrading performance and energy efficiency for embedded applications.

关键词： Embedded Systems RISC-V Processor Architecture dynamic function exchange FPGAs

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FPGA based Adaptive Hardware Acceleration for Multiple Deep Learning Tasks 14

FPGA based Adaptive Hardware Acceleration for Multiple Deep ...

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14th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip (MCSoC)

作者： Lu, Yufan Zhai, Xiaojun Saha, Sangeet Ehsan, Shoaib McDonald-Maier, Klaus D. Univ Essex Sch Comp Sci & Elect Engn Colchester Essex England

ISBN: (纸本)9781665438605

Machine learning, and in particular deep learning (DL), has seen strong success in a wide variety of applications, e.g. object detection, image classification and self-driving. However, due to the limitations on hardware resources and power consumption, there are many challenges to deploy deep learning algorithms on resource-constrained mobile and embedded systems, especially for systems running multiple DL algorithms for a variety of tasks. In this paper, an adaptive hardware resource management system, implemented on field-programmable gate arrays (FPGAs), is proposed to dynamically manage the on-chip hardware resources (e.g. LUTs, BRAMs and DSPs) to adapt to a variety of tasks. Using dynamic function exchange (DFX) technology, the system can dynamically allocate hardware resources to deploy deep learning units (DPUs) so as to balance the requirements, performance and power consumption of the deep learning applications. The prototype is implemented on the Xilinx Zynq UltraScale+ series chips. The experiment results indicate that the proposed scheme significantly improves the computing efficiency of the resourceconstrained systems under various experimental scenarios. Compared to the baseline, the proposed strategy consumes 38% and 82% of power in low working load cases and high working load cases, respectively. Typically, the proposed system can save approximately 75.8% of energy.

关键词： Deep learning processing unit dynamic function exchange DFX deep learning partial reconfiguration embedded systems

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