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IEEE International Symposium on Nanoelectronic and Information Systems

作者： Venkatesan, Varun Ponpandi, Swamy D. Tyagi, Akhilesh Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA

ISBN: (纸本)9781467396929

Processor hardware has been architected with the assumption that most data access patterns would be linearly spatial in nature. But, most applications involve algorithms that are designed with optimal efficiency in mind, which results in non-spatial, multi-dimensional data access. Moreover, this data view or access pattern changes dynamically in different program phases. This results in a mismatch between the processor hardware's view of data and the algorithmic view of data, leading to significant memory access bottlenecks. This variation in data views is especially more pronounced in applications involving large datasets, leading to significantly increased latency and user response times. Previous attempts to tackle this problem were primarily targeted at execution time optimization. We present a dynamic technique piggybacked on the classical dynamic binary optimization (DBO) to shape the data view for each program phase differently resulting in program execution time reduction along with reductions in access energy. Our implementation rearranges non-adjacent data into a contiguous dataview. It uses wrappers to replace irregular data access patterns with spatially local dataview. HDTrans, a runtime dynamic binary optimization framework has been used to perform runtime instrumentation and dynamic data optimization to achieve this goal. This scheme not only ensures a reduced program execution time, but also results in lower energy use. Some of the commonly used benchmarks from the SPEC 2006 suite were profiled to determine irregular data accesses from procedures which contributed heavily to the overall execution time. Wrappers built to replace these accesses with spatially adjacent data led to a significant improvement in the total execution time. On average, 20% reduction in time was achieved along with a 5% reduction in energy.

关键词： dynamic binary optimization Data Shapers Spatial locality Performance optimization Time and Energy

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Shaping data for application performance and energy optimization in dynamic data view framework

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INTEGRATION-THE VLSI JOURNAL 2017年 58卷 311-319页

作者： Venkatesan, Varun Ponpandi, Swamy D. Tyagi, Akhilesh Intel Corp Bellevue WA USA Iowa State Univ Dept Elect & Comp Engn Ames IA 50011 USA

Memory access bottlenecks are often due to the result of mismatch between the processor hardware's view of data and the algorithmic/logical view of data. This variation in data views is especially more pronounced in applications involving large datasets, leading to significantly increased latency and user response times. Previous attempts to tackle this problem were primarily targeted at execution time optimization. We present a dynamic technique piggybacked on the classical dynamic binary optimization (DBO) to shape the data view for each program phase differently resulting in program execution time reduction along with reductions in access energy. Our implementation rearranges non-adjacent data into a contiguous dataview. It uses wrappers to replace irregular data access patterns with spatially local dataview. DDV (dynamic data view), a runtime dynamic binary translation and optimization framework has been used to perform runtime instrumentation and dynamic data optimization to achieve this goal. This scheme not only ensures a reduced program execution time, but also results in lower cache access energy. Some of the commonly used benchmarks from the SPEC 2006 and SPLASH-2 suite were profiled to determine irregular data accesses from procedures which contributed heavily to the overall execution time. Wrappers built to replace these accesses with spatially adjacent data led to a significant improvement in the total execution time. On average, 20% reduction in time was achieved along with a 5% reduction in energy for SPEC 2006 and 11% reduction in time was achieved along with a 6% reduction in energy for SPLASH-2.

关键词： dynamic binary optimization Data shapers Spatial locality Performance optimization Time and energy

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Runtime Vectorization Transformations of binary Code

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2017年第6期45卷 1536-1565页

作者： Hallou, Nabil Rohou, Erven Clauss, Philippe INRIA Rennes France Univ Strasbourg ICube Lab INRIA Strasbourg France

In many cases, applications are not optimized for the hardware on which they run. Several reasons contribute to this unsatisfying situation, such as legacy code, commercial code distributed in binary form, or deployment on compute farms. In fact, backward compatibility of ISA guarantees only the functionality, not the best exploitation of the hardware. In this work, we focus on maximizing the CPU efficiency for the SIMD extensions. The first contribution was originally published in the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS XV, July 2015, Agios Konstantinos, Greece. It is a binary-to-binary optimization framework where loops vectorized for an older version of the processor SIMD extension are automatically converted to a newer one. It is a lightweight mechanism that does not include a vectorizer, but instead leverages what a static vectorizer previously did. We show that many loops compiled for x86 SSE can be dynamically converted to the more recent and more powerful AVX;as well as, how correctness is maintained with regards to challenges such as data dependencies and reductions. We obtain speedups in line with those of a native compiler targeting AVX. The second contribution is the runtime vectorization of loops in binary codes that were not originally vectorized. For this purpose, we use open source frameworks that we have tuned and integrated to (1) dynamically lift the x86 binary into the Intermediate Representation form of the LLVM compiler, (2) abstract hot loops in the polyhedral model, (3) use the power of this mathematical framework to vectorize them, and (4) finally compile them back into executable form using the LLVM Just-In-Time compiler. In most cases, the obtained speedups are close to the number of elements that can be simultaneously processed by the SIMD unit. The re-vectorizer and auto-vectorizer are implemented inside a dynamic optimization platform;it is completely transparent to the us

关键词： Performance Runtime optimization binary code dynamic binary optimization Vectorization Polyhedral model

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DDGacc: Boosting dynamic DDG-based binary optimizations through Specialized Hardware Support 12

DDGacc: Boosting Dynamic DDG-based Binary Optimizations thro...

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8th ACM SIGPLAN-SIGOPS Conference on Virtual Execution Environments

作者： Pavlou, Demos Gibert, Enric Latorre, Fernando Gonzalez, Antonio Univ Politecn Cataluna Dept Comp Architecture E-08028 Barcelona Spain

ISBN: (纸本)9781450311762

dynamic binary Translators (DBT) and dynamic binary optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualization. However, the software layer in such systems introduces non-negligible overheads which affect performance and user experience. Hence, reducing DBT/DBO overheads is of paramount importance. In addition, reduced overheads have interesting collateral effects in the rest of the software layer, such as allowing optimizations to be applied earlier. A cost-effective solution to this problem is to provide hardware support to speed up the primitives of the software layer, paying special attention to automate DBT/DBO mechanisms and leave the heuristics to the software, which is more flexible. In this work, we have characterized the overheads of a DBO system using DynamoRIO implementing several basic optimizations. We have seen that the computation of the Data Dependence Graph (DDG) accounts for 5%-10% of the execution time. For this reason, we propose to add hardware support for this task in the form of a new functional unit, called DDGacc, which is integrated in a conventional pipeline processor and is operated through new ISA instructions. Our evaluation shows that DDGacc reduces the cost of computing the DDG by 32x, which reduces overall execution time by 5%-10% on average and up to 18% for applications where the DBO optimizes large code footprints.

关键词： Algorithms Design Performance Co-designed processors hardware acceleration dynamic binary optimization start-up overhead

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Enabling Cross-ISA Offloading for COTS Binaries 17

Enabling Cross-ISA Offloading for COTS Binaries

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15th ACM Annual International Conference on Mobile Systems, Applications, and Services (MobiSys)

作者： Wang, Wenwen Yew, Pen-Chung Zhai, Antonia McCamant, Stephen Wu, Youfeng Bobba, Jayaram Univ Minnesota St Paul MN 55455 USA Intel Labs Pittsburgh PA USA

ISBN: (纸本)9781450349284

Work offloading allows a mobile device, i.e., the client, to execute its computation-intensive code remotely on a more powerful server to improve its performance and to extend its battery life. However, the difference in instruction set architectures (ISAs) between the client and the server poses a great challenge to work offloading. Most of the existing solutions rely on language-level virtual machines to hide such differences. Therefore, they have to tie closely to the specific programming languages. Other approaches try to recompile the mobile applications to achieve the specific goal of offloading, so their applicability is limited to the availability of the source code. To overcome the above limitations, we propose to extend the capability of dynamic binary translation across clients and servers to offload the identified computation-intensive binary code regions automatically to the server at runtime. With this approach, the native binaries on the client can be offloaded to the server seamlessly without the limitations mentioned above. A prototype has been implemented using an existing retargetable dynamic binary translator. Experimental results show that our system achieves 1.93X speedup with 48.66% reduction in energy consumption for six real-world applications, and 1.62X speedup with 42.4% reduction in energy consumption for SPEC CINT2006 benchmarks.

关键词： Computation Offloading dynamic binary Translation dynamic binary optimization Offloading Target Selection

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Modeling and performance evaluation of TSO-preserving binary optimization

Modeling and performance evaluation of TSO-preserving binary...

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20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011

作者： Wang, Cheng Wu, Youfeng Programming Systems Lab. Microprocessor and Programming Research Intel Labs. 2200 Mission College Blvd. Santa Clara CA 95052 United States

ISBN: (纸本)9780769545660

Program optimization on multi-core systems must preserve the program memory consistency. This paper studies TSO-preserving binary optimization. We introduce a novel approach to formally model TSO-preserving binary optimization based on the formal TSO memory model. The major contribution of the modeling is a sound and complete algorithm to verify TSO-preserving binary optimization with O(N2) complexity. We also developed a dynamic binary optimization system to evaluate the performance impact of TSO-preserving optimization. We show in our experiments that, dynamic binary optimization without memory optimizations can improve performance by 8.1%. TSOpreserving optimizations can further improve the performance by 4.8% to a total 12.9%. Without considering the restriction for TSO-preserving optimizations, the dynamic binary optimization can improve the overall performance to 20.4%. © 2011 IEEE.

关键词： binary optimization Heuristic algorithms Instruction sets Load modeling Memory management optimization TSO-preserving binary optimization TSO-preserving optimization Total Store Ordering dynamic binary optimization formal TSO memory model multicore system

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