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Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework

IEEE ACCESS 2024年 12卷 124081-124094页

作者： Pudi, Dhilleswararao Malviya, Shivam Boppu, Srinivas Yang, Yu Hemani, Ahmed Cenkeramaddi, Linga Reddy Indian Inst Technol Bhubaneswar Sch Elect Sci Bhubaneswar 752050 India KTH Royal Inst Technol Div Elect & Embedded Syst Stockholm S-11428 Sweden Univ Agder Dept ICT N-4630 Grimstad Norway

Coarse-Grained reconfigurable array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variables on registers, is a daunting problem. SiLago is a recently developed VLSI design framework comprising two large-scale reconfigurable fabrics: dynamically reconfigurable resource array (DRRA) and Distributed Memory Architecture (DiMArch). It uses the Vesyla compiler to map applications on these fabrics. The present version of Vesyla executes binding and scheduling sequentially, with binding first, followed by scheduling. In this paper, we proposed an Integer Linear Programming (ILP)-based exact method to solve scheduling and binding simultaneously that delivers better solutions while mapping applications on these fabrics. The proposed ILP combines two objective functions, one for scheduling and one for binding, and both of these objective functions are coupled with weightage factors $\alpha $ and $\beta $ so that the user can have the flexibility to prioritize either scheduling or binding or both based on the requirements. We determined the binding and execution time of image processing tasks and various routines of the Basic Linear Algebraic Subprogram (BLAS) using the proposed ILP for multiple combinations of weightage factors. Furthermore, a comparison analysis has been conducted to compare the latency and power dissipation of several benchmarks between the existing and proposed approaches. The experimental results demonstrate that the proposed method exhibits a substantial reduction in power consumption and latency compared to the existing method.

关键词： Random access memory Radio frequency Registers Switches Dynamic scheduling reconfigurable architectures Distributed management Memory management Integer linear programming Scheduling Power demand Coarse-grain reconfigurable architecture dynamically reconfigurable resource array distributed memory architecture integer linear programming high-level synthesis scheduling binding

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Automating functional unit and register binding for synchoros CGRA platform

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2024年第2期28卷 155-186页

作者： Pudi, Dhilleswararao Tiwari, Utsav Boppu, Srinivas Yang, Yu Hemani, Ahmed Indian Inst Technol Bhubaneswar IITBBS Sch Elect Sci Bhubaneswar 752050 Odisha India Royal Inst Technol KTH Sch Elect Engn & Comp Sci Kistagangen 16 S-16440 Stockholm Sweden

Coarse-grain reconfigurable architectures, which provide high computing throughput, low cost, scalability, and energy efficiency, have grown in popularity in recent years. SiLago is a new VLSI design framework comprised of two coarse-grain reconfigurable fabrics: a dynamically reconfigurable resource array and a distributed memory architecture. It employs the Vesyla compiler to map streaming applications on these fabrics. Binding is a critical step in the high-level synthesis that maps operations and variables to functional units and storage elements in the design. It influences design performance metrics such as power, latency, area, etc. The current version of Vesyla does not support automatic binding, and it has to be specified manually through pragmas, which makes it less flexible. This paper proposes various approaches to automate the binding in Vesyla. We present a list scheduling-based approach to automate functional unit binding and an integer linear programming approach to automate register binding. Furthermore, we determine the binding of various basic linear algebraic subprogram and image processing tasks using the proposed approaches. Finally, a comparative analysis has been made between the automatic and manual binding concerning the power dissipation and latency for various benchmarks. The experimental results show that the proposed automatic binding consumes significantly less power for nearly the same latency as manual binding.

关键词： High-level synthesis Coarse-grain reconfigurable architecture Binding SiLago Vesyla Integer linear programming dynamically reconfigurable resource array Distributed memory architecture

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Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures 23

Efficient Implementation of 2-D Convolution on DRRA and DiMA...

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13th International Symposium on Highly Efficient Accelerators and reconfigurable Technologies (HEART)

作者： Pudi, Dhilleswararao Ryansh, Rajeev Boppu, Srinivas Yang, Yu Hemani, Ahmed Indian Inst Technol Bhubaneswar Odisha India Royal Inst Technol KTH Kista Sweden

ISBN: (纸本)9798400700439

Convolution has been widely employed in image processing and computer vision applications such as picture augmentation, smoothing, and structure extraction. In addition, convolution operations are the most prevalent computing patterns in machine learning domains. Convolutions, for example, are used in a substantial chunk of state-of-the-art convolutional neural network operations. Therefore, effectively mapping convolution operations onto hardware architectures is crucial for achieving superior performance while accelerating convolutional neural networks. In this paper, we proposed various algorithms to efficiently map the 2-D convolution operation onto a dynamically reconfigurable resource array and distributed memory architecture. Furthermore, we have discussed the mapping of 2-D convolution on the target architecture for an input matrix of arbitrary size, as well as the generalization of the proposed approaches for multi-column DRRA architectures.

关键词： Convolution Coarse Grain reconfigurable Architectures dynamically reconfigurable resource array Distributed Memory Architecture Machine Learning Convolutional Neural Networks FPGA

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Implementation of Image Averaging on DRRA and DiMArch Architectures 36

Implementation of Image Averaging on DRRA and DiMArch Archit...

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36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Pudi, Dhilleswararao Goudu, Vamsi Boppu, Srinivas Ratnu, Ritika Hemani, Ahmed Indian Inst Technol Bhubaneswar Bhubaneswar India KTH Royal Inst Technol Stockholm Sweden

ISBN: (纸本)9798350318340

Image averaging is a technique used in image processing to reduce the noise present in an image. Image averaging is computationally intensive, particularly when dealing with images with high resolutions and large sizes. Thus, employing specialized hardware, such as field programmable gate arrays and coarse-grained reconfigurable architectures, becomes essential for efficient implementations, surpassing the capability of general-purpose processors. This paper proposes various approaches for implementing image averaging using two coarse-grain reconfigurable fabrics: dynamically reconfigurable resource array and distributed memory architecture. Furthermore, we have discussed the implementation of image averaging on the target architecture for an input matrix of arbitrary size. Finally, the proposed approaches were compared with a field-programmable gate array-based implementation in terms of power dissipation. The experimental results show that the proposed approaches consume considerably less power than a field-programmable gate array-based implementation.

关键词： Image averaging Coarse-grained reconfigurable architectures dynamically reconfigurable resource array Distributed memory architecture

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Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures 26

Implementation of Sobel Edge Detection on DRRA and DiMArch A...

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26th Euromicro Conference on Digital System Design (DSD) / 49th Euromicro Conference on Software Engineering and Advanced Applications (SEAA)

作者： Pudi, Dhilleswararao Ryansh, Rajeev Goudu, Vamsi Boppu, Srinivas Hemani, Ahmed Indian Inst Technol Bhubaneswar Sch Elect Sci Bhubaneswar India KTH Royal Inst Technol Sch EECS Stockholm Sweden

ISBN: (纸本)9798350344196

Edge detection is a fundamental operation in image processing, serving as a crucial step in various applications such as object recognition, image segmentation, and scene understanding. The Sobel edge detection algorithm has emerged as a widely used method for detecting vertical and horizontal edges in digital images. However, performing edge detection on high-resolution images with large dimensions can be computationally intensive and time-consuming. Specialized hardware solutions such as Field Programmable Gate arrays (FPGAs) and Coarse-Grained reconfigurable arrays (CGRAs) offer significant advantages over general-purpose processors for implementing edge detection algorithms. This paper proposes algorithms for implementing the Sobel edge detection algorithm using two CGRA fabrics: dynamically reconfigurable resource array and distributed memory architecture. Furthermore, we discuss the implementation of Sobel edge detection on the target architecture for an input matrix of arbitrary size. Finally, the proposed approaches were compared with other CGRA-based implementations in terms of latency. The experimental results show that the proposed approaches exhibit significantly lower latency compared to other CGRA-based implementations.

关键词： Sobel edge detection Coarse-grained reconfigurable array Field programmable gate array dynamically reconfigurable resource array Distributed memory architecture

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