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A new high speed and low power decoder/encoder for Radix-4 Booth multiplier

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2021年第7期49卷 2199-2213页

作者： Ghasemi, Mir Majid Fathi, Amir Mousazadeh, Morteza Khoei, Abdollah Urmia Univ Microelect Res Lab Orumiyeh 57159 Iran

The proposed booth decoder/encoder unit is an ultrahigh-speed unit among the reported ones which was designed by modifying and creating a new format truth table with 0.18 mu m CMOS technology. According to the modified truth table, four cases are defined, and a proper circuit for each case is designed. The proposed structure is discussed considering the possible problems such as the swing and discharge problems. The gate-level delay of the proposed structure and other related works have been calculated and are compared. The propagation delay of the proposed structure has been calculated and simulated to validate the data. To justify the comparisons, other related works have been simulated again with the same condition. The propagation delay of the proposed structure is 226 ps, which is minimum compared to previous related works. The proposed structure reduces the delay by 30-200% comparing related works and also improves the delay of the multiplier 4-21%. The power consumption and the area of the structure are 477 mu w and 20 x 18 mu m(2), respectively. In this paper, Hspice software for simulating, MATLAB for numerical calculations, and Cadence for designing the layout of the proposed structure have been used.

关键词： Booth algorithm delay digital multiplier encoder decoder

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Question Answering over Knowledge Base with Variational Auto-encoder 8

Question Answering over Knowledge Base with Variational Auto...

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8th IEEE International Conference on Multimedia Big Data (BigMM)

作者： Sharath, Japa Sai Sarah, Green Southern Illinois Univ Sch Comp Carbondale IL 62901 USA AT&T Inc AVP Technol Dallas TX USA

ISBN: (数字)9781665459631

ISBN: (纸本)9781665459631

Knowledge Base is a semantic data repository made available over the web. Knowledge bases are multi-relational graphs consisting of entities and relations representing facts about the world. These facts follow a controlled vocabulary that drives the knowledge base, often called ontology. Entities are the graph nodes, while relations are the edges connecting the nodes. While knowledge base attention proliferates, extracting information from these resources is challenging. One of the promising approaches is Question Answering systems. The Question Answering over Knowledge Base(KB-QA) system aims to provide a natural language interface to pose a query to the KB. QA systems use embeddings to map the posed Question to the facts stored in the knowledge bases. QA systems can be effectively improved using large transformer models. These transformer models are computationally expensive, which prevents their use in real-world applications. To solve this, we started our study with the use-case of Knowledge Base Question Answering systems. In KB-QA systems, representing the entities and relationships play a pivotal role in extracting the answer to the posed query. Traditional KB embedding techniques represent entities/relations as vectors, mapping them in different semantic spaces and ignoring the subtle correlation. A pre-training language model for encoding the KB facts will preserve the semantic and contextual correlation. While learning linguistic knowledge, these models also store relational knowledge in the training data. These Language Models are often trained on a massive corpus addressing the Out-Of-Vocabulary problem. In this paper, we incorporate a co-embedding model for knowledge base embedding, which learns low-dimensional representations of entities and relations in the same semantic space. We propose a Variational Auto-encoder, an efficient transformer architecture that represents knowledge base representations as Gaussian distributions to address the issue of ne

关键词： knowledge base question answering Bert Language Model KBQA Multi-Head Attention VAE encoder Transformers

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Memristive self-learning logic circuit with application to encoder and decoder

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NEURAL COMPUTING & APPLICATIONS 2021年第10期33卷 4901-4913页

作者： Hong, Qinghui Shi, Zirui Sun, Jingru Du, Sichun Hunan Univ Coll Comp Sci & Elect Engn Changsha 410082 Peoples R China

Different logic circuits based on memristors have been extensively investigated. However, most of these circuits require accurate initialization. A self-learning logic circuit based on mermristors that can achieve various logic gates without initialization is proposed in this paper. Three functional blocks, including a sum block, a learning block, and a compare block, are elaborately designed in the proposed logic circuit. Programmable switches in the sum and compare blocks enable the circuit to perform various logic gates, such as Boolean, IMPLY, and random logical combinations. In these various logical operations, the learning block can automatically obtain different memristance states. The aforementioned logic operations can easily be extended to multi-fan-in logic and logical cascade operations. Circuit designs of an encoder and decoder are considered as application examples. Finally, PSpice simulation results of the logic circuits and extended applications are provided. Simulation results indicate that the proposed circuit can effectively perform different logic operations and exhibits excellent robustness to circuit device variations.

关键词： Memristor Logic circuit Self-learning Boolean logic encoder

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Design of thermally tuned micro-ring resonator based 4 x 2 encoder 17

Design of thermally tuned micro-ring resonator based 4 x 2 e...

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Conference on Silicon Photonics XVII Part of SPIE Photonics West OPTO Conference

作者： Lee, Arman Nakarmi, Bikash Ukaegbu, Ikechi Augustine Nazarbayev Univ Sch Engn & Digital Sci 53 Kabanbay Batyr Ave Nur Sultan Kazakhstan Nanjing Univ Aeronaut & Astronaut Nanjing 211106 Peoples R China

ISBN: (纸本)9781510648845;9781510648838

In this paper, we design and demonstrate the optical encoder circuit. This device performs the function of encoding a 4-bit electrical signal into a 2-bit optical signal. The encoder structure is based on micro-ring resonator (MRRs) structures. A constant light (COS) is applied into an input port of the circuit, and depending on the electrical signals fed to heaters in MRRs;the input light is directed to different output ports. The performance of the proposed encoder is verified with the static and dynamic responses. The dynamic response of the encoder is tested up to 500Kbps. The proposed encoder is CMOS-compatible and can be manufactured using existing technologies that can be used for photonics computing and control.

关键词： encoder micro-ring resonator thermal tuning

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Visual-inertial odometry based on tightly-coupled encoder 9

Visual-inertial odometry based on tightly-coupled encoder

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Conference on Optoelectronic Imaging and Multimedia Technology IX

作者： Hu, Zhangfang Guo, Zhenqian Luo, Yuan Chen, Jian Chongqing Univ Posts & Telecommun Chongqing Municipal Level Key Lab Photoelect Info Chongqing 400065 Peoples R China

ISBN: (纸本)9781510657014;9781510657007

In order to solve the problem of inaccurate scale optimization of visual inertial odometer (VIO) algorithm under uniform motion, this paper presents a Visual-Inertial-encoder Tightly-Coupled Odometry (VIETO) algorithm, and describes VIETO initialization as an optimal estimation problem in the sense of maximum-a-posteriori (MAP) estimation. Firstly, the pre-integration theory of encoder is introduced in this paper so that the scale and velocity information can be obtained by using the encoder to measure the pre-integration during the visual MAP estimation, which provides a good initial value for the optimal estimation of IMU parameters. Secondly, the encoder error term and random plane constraint are introduced into the visual inertia optimization framework to further constrain pose estimation. Finally, we apply VIETO to the monocular inertial ORB-SLAM3 system. By comparing the algorithm with other similar algorithms on the DS dataset, the results prove the effectiveness of the system.

关键词： encoder visual-inertial odometry multi-data fusion ORB-SLAM3

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Improving Incremental encoder Measurement: Variable Acquisition Window and Quadrature Phase Compensation to Minimize Acquisition Errors

Improving Incremental Encoder Measurement: Variable Acquisit...

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IEEE International Conference on Autonomous Robot Systems and Competitions (ICARSC)

作者： Lima, Jose Pinto, Vitor H. Moreira, A. Paulo Costa, Paulo Inst Politecn Braganca Res Ctr Digitalizat & Intelligent Robot CeDRI Campus Santa Apolonia P-5300253 Braganca Portugal INESC Technol & Sci Porto Portugal SYSTEC DIGI2 Res Ctr Syst & Technol Digital & Intelligent Ind Lab Porto Portugal Univ Porto Fac Engn Porto Portugal

ISBN: (纸本)9781665482172

Motion control is an important task in several areas, such as robotics where the angular position and speed should be acquired, usually with encoders. For slow angular speeds, an error is introduced spoiling the measurement. In this paper there will be proposed two new methodologies, that when combined allow to increase the precision whereas reducing the error, even on transient velocities. The two methodologies Variable Acquisition Window and a Quadrature Phase Compensation are addressed and combined simultaneously. A real implementation of the proposed algorithms is performed on a real hardware, with a DC motor and a low resolution encoder based on hall effect. The results validate the proposed approach since the errors are reduced compared with the standard Quadrature encoder Reading.

关键词： encoder speed measurement positioning measurement.

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A Fast CU Partition Algorithm for VVenC encoder in Intra Configuration 36

A Fast CU Partition Algorithm for VVenC Encoder in Intra Con...

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36th IEEE Workshop on Signal Processing Systems (SiPS)

作者： Taabane, Ibrahim Menard, Daniel Mansouri, Anas Ahaitouf, Ali Univ Rennes INSA Rennes CNRS IETR UMR 6164 Rennes France Sidi Mohamed Ben Abdellah Univ SIGER Lab Rennes France Sidi Mohamed Ben Abdellah Univ ENSA Fez SIGER Lab Fes Morocco Sidi Mohamed Ben Abdellah Univ FST Fez SIGER Lab Fes Morocco

ISBN: (数字)9781665485241

ISBN: (纸本)9781665485241

Versatile Video Coding (VVC) has been recently finalized by the Joint Video Experts Team (JVET). It provides various advanced coding tools, that allow great improvement in coding efficiency by a gain up to 50% in bitrate reduction when compared to the current standard, High Efficiency Video Coding (HEVC). However, this improvement costs relatively high computational complexity. In this context, this paper focuses on the Quad Tree with nested Multi-Type Tree (QTMTT) partition block in intra prediction mode in VVC. Therefore, a fast Coding Unit (CU) partition algorithm is proposed to directly predict the most probable split mode, ignore remain splits and early terminate CU partitioning process. Thus, our newly designed method is implemented on the Fraunhofer Versatile Video encoder (VVenC) and tested on the Common Test Conditions (CTC) sequences. The experimental results confirmed that our proposed technique achieves up to 27.02% of encoding time reduction in average, for different test video sequences with a negligible increase in Bjontegaard Delta Bitrate (BDBR) of 0.37% as compared to the original VVenC encoder under its All Intra (AI) configuration mode.

关键词： Versatile Video Coding VVC VVenC encoder Partitioning Block Intra Coding LightGBM Machine Learning

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Wafer Pattern Counting, Detection and Classification Based on encoder-Decoder CNN Structure 2

Wafer Pattern Counting, Detection and Classification Based o...

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2nd Annual Intermountain Conference on Engineering, Technology, and Computing (IETC)

作者： Lin, Yu Int Technol Univ Dept Comp Sci Santa Clara CA 95054 USA

ISBN: (纸本)9781665486538

This paper designs an automatic wafer pattern counting pipeline based on a convolutional neural network (CNN) based structure, also called the WPCCNN network pipeline. The study will utilize deep learning algorithms to detect, binary classify and count wafer patterns. In the sample dataset, over two hundred wafers have been scanned by industrial computed tomography, containing 11 different patterns for the dataset images. Each image includes three processed steps. Moreover, it utilizes the lightweight CNN structure to demonstrate detection, classification, and estimated counting [1, 3]. Besides, the study also uses encoder and decoder structure on the CNN algorithm to obtain the closest expected output. Compared to traditional object counting methods, such as localization and density estimation, using this new method to count objects will be more accurate, faster, and more accessible [1-3]. The experiment results indicate that our algorithm is highly accurate with the paring between the original patterns and the labeled markers. The average counting accuracy is 99.6% in a single wafer.

关键词： Deep learning Convolutional neural network (CNN) encoder Decoder Image classification Detection Pattern Counting Wafer GPU

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4K 120 fps HEVC encoder with Multi-Chip Configuration

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IEICE TRANSACTIONS ON COMMUNICATIONS 2021年第7期E104B卷 749-759页

作者： Omori, Yuya Nakamura, Ken Onishi, Takayuki Kobayashi, Daisuke Osawa, Tatsuya Iwasaki, Hiroe NTT Corp NTT Media Intelligence Labs Yokosuka Kanagawa 2390847 Japan NTT Elect Corp Yokohama Kanagawa 2210031 Japan

This paper describes a novel 4K 120 fps (frames per second) real-time HEVC (High Efficiency Video Coding) encoder for high-frame-rate video encoding and transmission. Motion portrayal problems such as motion blur and jerkiness may occur in video scenes containing fast-moving objects or quick camera panning. A high-frame-rate solves such problems and provides a more immersive viewing experience that can express even the fast-moving scenes without discomfort. It can also be used in remote operation for scenes with high motion, such as VAR (Video Assistant Referee) systems in sports. Real-time encoding of high-frame-rate videos with low latency and temporal scalability is required for providing such high-frame-rate video services. The proposed encoder achieves full 4K/120 fps real-time encoding, which is twice the current 4K service frame rate of 60 fps, by multichip configuration with two encoder LSI. Exchange of reference picture data near a spatially divided slice boundary provides cross-chip motion estimation, and maintains the coding efficiency. The encoder supports temporal-scalable coding mode, in which it output stream with temporal scalability transmitted over one or two transmission paths. The encoder also supports the other mode, low-delay coding mode, in which it achieves 21.8 msec low-latency processing through motion vector restriction. Evaluation of the proposed encoder's multichip configuration shows that the BD-bitrate (the average rate of bitrate increase), compared to simple slice division without inter-chip transfer, is 2:86% at minimum and 2:41% on average in temporal-scalable coding mode. The proposed encoder system will open the door to the next generation of high-frame-rate UHDTV (ultra-high-definition television) services.

关键词： HEVC encoder high frame rate low delay temporal scalability

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A Novel encoder for DC-Balanced SpaceWire 9

A Novel Encoder for DC-Balanced SpaceWire

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9th International SpaceWire and SpaceFibre Conference (ISC)

作者： Rose, Christopher M. Cho, Steve S. Gile, Matthew M. Volland, Kirk N. Wehle, Jarrett T. Johns Hopkins Univ Appl Phys Lab Laurel MD 20723 USA

ISBN: (纸本)9780995453029

A DC-balanced encoding for SpaceWire traffic offers several advantages in flight hardware design. Conventionally, block encoding techniques have been used. In this paper, a novel cycle-stretching method is described which takes advantage of SpaceWire's feature of embedding clock in data. This feature allows variable-length periods to be used opportunistically to perform DC-balancing of a SpaceWire stream, without using block encoders or relying on excursions from SpaceWire protocol. Such period-adjusting encoders can show high efficiencies for randomly generated SpaceWire traffic, particularly when paired with lookahead methods. An encoder whose output can be decoded by conventional SpaceWire receivers is presented. Such an encoder produces a data stream which, while being DC-balanced, can be analyzed by conventional test equipment (e.g. link analyzers) without additional hardware. The efficiencies of multiple encoders are characterized. Several worst cases are considered. An encoder is tested with flightlike data from integration testing of DART (Double Asteroid Redirection Test) a NASA spacecraft which uses a SpaceWire network.

关键词： SpaceWire encoder Cycle-Stretching DC-Balanced AC-Coupled.

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