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Enhanced Framework for Lossless Image Compression Using Image Segmentation and a Novel Dynamic Bit-Level encoding algorithm

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APPLIED SCIENCES-BASEL 2025年第6期15卷 2964-2964页

作者： Erdal, Erdal Onal, Alperen Kirikkale Univ Fac Engn & Nat Sci Dept Comp Engn TR-71450 Kirikkale Turkiye Kirikkale Univ Grad Sch Nat & Appl Sci Dept Comp Engn TR-71450 Kirikkale Turkiye

This study proposes a dynamic bit-level encoding algorithm (DEA) and introduces the S+DEA compression framework, which enhances compression efficiency by integrating the DEA with image segmentation as a preprocessing step. The novel approaches were validated on four different datasets, demonstrating strong performance and broad applicability. A dedicated data structure was developed to facilitate lossless storage and precise reconstruction of compressed data, ensuring data integrity throughout the process. The evaluation results showed that the DEA outperformed all benchmark encoding algorithms, achieving an improvement percentage (IP) value of 45.12, indicating its effectiveness as a highly efficient encoding method. Moreover, the S+DEA compression algorithm demonstrated significant improvements in compression efficiency. It consistently outperformed BPG, JPEG-LS, and JPEG2000 across three datasets. While it performed slightly worse than JPEG-LS in medical images, it remained competitive overall. A dataset-specific analysis revealed that in medical images, the S+DEA performed close to the DEA, suggesting that segmentation alone does not enhance compression in this domain. This emphasizes the importance of exploring alternative preprocessing techniques to enhance the DEA's performance in medical imaging applications. The experimental results demonstrate that the DEA and S+DEA offer competitive encoding and compression capabilities, making them promising alternatives to existing frameworks.

关键词： image compression encoding algorithm data structure image segmentation adaptive and self-organizing algorithm

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Construction and encoding algorithm for Maximum Run-Length Limited Single Insertion/Deletion Correcting Code

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2022年第1期E105A卷 35-43页

作者： Takemoto, Reona Nozaki, Takayuki Yamaguchi Univ Div Fundamental Sci Grad Sch Sci & Technol Innovat Dept Informat Yamaguchi 7538512 Japan Yamaguchi Univ Res Inst Time Studies Yamaguchi 7538511 Japan

Maximum run-length limited codes are constraint codes used in communication and data storage systems. Insertion/deletion correcting codes correct insertion or deletion errors caused in transmitted sequences and are used for combating synchronization errors. This paper investigates the maximum run-length limited single insertion/deletion correcting (RLL-SIDC) codes. More precisely, we construct efficiently encodable and decodable RLL-SIDC codes. Moreover, we present its encoding and decoding algorithms and show the redundancy of the code.

关键词： single insertion/deletion correcting codes maximum run-length limited codes encoding algorithm decoding algorithm

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A Low Complexity encoding algorithm for Systematic Polar Codes

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IEEE COMMUNICATIONS LETTERS 2016年第7期20卷 1277-1280页

作者： Chen, Guo Tai Zhang, Zhaoyang Zhong, Caijun Zhang, Liang Fujian Normal Univ Fuqing Branch Fuqing 350300 Peoples R China Zhejiang Univ Hangzhou 310027 Peoples R China Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Peoples R China

Arikan has shown that systematic polar codes (SPC) outperform non-SPC (NSPC). However, the performance gain comes at the price of elevated encoding complexity, i.e., compared with NSPC, the available encoding methods for SPC require higher memory and computation. In this letter, we propose an efficient encoding algorithm requiring only N bits of memory and having (N/2) log(2) N XOR operations. Moreover, the auxiliary variables in the algorithm can share the memory to reduce extra memory requirement. Furthermore, a parallel 2-bit encoding algorithm is also presented to improve the encoding throughput. Remarkably, we show that parallel encoding can be implemented with the same number of XOR operations and memory bits. Finally, the proposed encoding algorithm can be directly used for NSPC with the same complexity.

关键词： Polar codes systematic polar codes encoding algorithm parallel encoding

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An optimized encoding algorithm for systematic polar codes

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EURASIP JOURNAL ON WIRELESS COMMUNICATIONS AND NETWORKING 2019年第1期2019卷 1页

作者： Wang, Xiumin Zhang, Zhihong Li, Jun Wang, Yu Cao, Haiyan Li, Zhengquan Shan, Liang China Jiliang Univ Coll Informat Engn Hangzhou 310018 Zhejiang Peoples R China Nanjing Univ Informat Sci & Technol Binjiang Coll Wuxi 214105 Jiangsu Peoples R China New York City Coll Technol Dept Comp Engn Technol Brooklyn NY 11201 USA Hangzhou Dianzi Univ Coll Commun Engn Hangzhou 310018 Zhejiang Peoples R China Jiangnan Univ Sch IoT Engn Wuxi 214122 Jiangsu Peoples R China

Many different encoding algorithms for systematic polar codes (SPC) have been introduced since SPC was proposed in 2011. However, the number of the computing units of exclusive OR (XOR) has not been optimized yet. According to an iterative property of the generator matrix and particular lower triangular structure of the matrix, we propose an optimized encoding algorithm (OEA) of SPC that can reduce the number of XOR computing units compared with existing non-recursive algorithms. We also prove that this property of the generator matrix could extend to different code lengths and rates of the polar codes. Through the matrix segmentation and transformation, we obtain a submatrix with all zero elements to save computation resources. The proportion of zero elements in the matrix can reach up to 58.5% from the OEA for SPC when the code length and code rate are 2048 and 0.5, respectively. Furthermore, the proposed OEA is beneficial to hardware implementation compared with the existing recursive algorithms in which signals are transmitted bidirectionally.

关键词： encoding algorithm Low complexity Computing units Systematic polar codes Generator matrix transformation

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Implementation of high speed data transfer serialized 128/130bit encoding algorithm using 90nm technology 5

Implementation of high speed data transfer serialized 128/13...

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5th International Conference on Advanced Computing and Communication Systems (ICACCS)

作者： Mhaboobkhan, F. Fathimaparveen, M. Gokila, K. Logapriya, P. PA Coll Engn & Technol Dept Elect & Commun Engn Coimbatore Tamil Nadu India

ISBN: (纸本)9781538695333

In the world of big data there has been a steady shift from parallel to high speed serial digital communication buses which requires devices with much higher data throughput. Serializing the data and sending at a faster rate, reduces the pin counts which in turn lead to much smaller devices in an integrated circuit compared to parallel communication. Line coding can potentially help in high data transfers. In this paper 128b/130b line coding algorithm has been proposed which has the double the payload of conventional 64b/66b encoding technique, with same number of preamble bits. This increases the data transfer rate drastically. The polynomial for the scrambler has been used from IEEE clause. The proposed 128b/130b encoding algorithm has been coded using Verilog and simulated using Quartus II 9.0v. The parameters such as Setup time, Hold time, Maximum frequency, power and slack for 8b/10b, 64b/66b and 128b/130b has been compared and tabulated. The layout has been designed for 128b/130b using Cadence Encounter 14.26 tool. The comparison shows that proposed algorithm has higher data rate at the expense of increase in hardware utilization.

关键词： Digital communication encoding algorithm 8b/10b overhead 64b/66b scrambling Linear Feedback Shift Register (LFSR)

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FPGA-Based Quasi-Cyclic LDPC encoding algorithm

FPGA-Based Quasi-Cyclic LDPC Encoding Algorithm

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Asia Communications and Photonics Conference (ACP) / International Conference on Information Photonics and Optical Communications (IPOC)

作者： Ding, Zhuo Wang, Liqian Cai, Shanyong Zhu, Miao Chang, Yunfan Zhang, Zhiguo Beijing Univ Posts & Telecommun BUPT State Key Lab Informat Photon & Opt Commun Beijing Peoples R China

ISBN: (纸本)9781665481557

In this paper, an algorithm for quasi-cyclic low-density parity-check code (QC-LDPC) encoding is proposed. The correctness of the algorithm is validated on the FPGA evaluation board. Experimental results show that the encoding delay can be reduced by 3.3 times compared to the conventional encoding algorithm based on generator matrix. In addition, the algorithm also reduces the complexity of hardware implementation.

关键词： encoding algorithm hardware architecture QC-LDPC codes FPGA

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An encoding algorithm Based on the Shortest Path Problem 14

An Encoding Algorithm Based on the Shortest Path Problem

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14th International Conference on Computational Intelligence and Security (CIS)

作者： Liu, Fanghan Tang, Xiaobing Yang, Zhaohui Shandong Jianzhu Univ Shandong Jigang Senior High Sch Jinan 250101 Shandong Peoples R China Shandong Jianzhu Univ Sch Comp Sci & Technol Jinan 250101 Shandong Peoples R China

ISBN: (纸本)9781728101699

The transportation network of the city is dynamic and stochastic, The problem of dynamic stochastic shortest path is NP-hard. the optimal problem of path is widely used in the fields of transportation, communication and computer network An improved self adaptive genetic algorithm is proposed by encoding the chromosomal *** paper investigates the shortest path problem based on the genetic algorithm principle, and improved genetic algorithm by adjusting the encoding parameters. Mny experiments indicate that the improved genetic algorithm could adapt to new transportation rapidly in global optimization than A* algorithm and Dijkstra algorithm and obtain the better solutions in the shortest path problem in the fields of transportation and computer network

关键词： Shortest path problem encoding algorithm chromosome encoding mode optimization problems

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RESEARCH ON OPTIMIZATION OF encoding algorithm OF PDF417 BARCODES 2nd

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2nd IFIP International Conference on Computer and Computing Technologies in Agriculture

作者： Sun, Ming Fu, Longsheng Han, Shuqing China Agr Univ Coll Informat & Elect Engn Beijing 100083 Peoples R China

ISBN: (纸本)9781441902108

The purpose of this research is to develop software to optimize the data compression of a PDF417 barcode using VC++6.0. According to the different compression mode and the particularities of Chinese, the relevant approaches which optimize the encoding algorithm of data compression such as spillage and the Chinese characters encoding are proposed, a simple approach to compute complex polynomial is introduced. After the whole data compression is finished, the number of the codeword is reduced and then the encoding algorithm is optimized. The developed encoding system of PDF 417 barcodes will be applied in the logistics management of fruits, therefore also will promote the fast development of the two-dimensional bar codes.

关键词： Two-dimensional barcode PDF417 encoding algorithm visual C++6.0

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Novel generic concept hierarchy encoding algorithm

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Jisuanji Gongcheng/Computer Engineering 2006年第12期32卷 17-18+21页

作者： Yuan, Junpeng Chen, Keng Huang, Jin Li, Lianhong Yang, Yu Zhu, Donghua Li, Junfeng School of Public Policy and Management Tsinghua University Beijing 100084 China School of Management and Economics Beijing Institute of Technology Beijing 100081 China

As one of the useful background knowledge, concept hierarchies organize data or concepts in hierarchical forms or in certain partial order, which are used for expressing knowledge in concise, high-level terms, and facilitating mining knowledge at multiple levels of abstraction. To incorporate the concept hierarchies into a data mining system, encoding plays a key role. A novel generic encoding algorithm is proposed which can be treated as a generic purpose encoding strategy suitable for any data mining functionalities. The partial order of the hierarchy is exactly represented by the codes so that it only needs to manipulate the codes when processing mining tasks.

关键词： Concept hierarchy Data mining encoding algorithm

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A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm

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IEICE ELECTRONICS EXPRESS 2019年第7期16卷 20181150-20181150页

作者： Liu, Huasen Wu, Danyu Zhou, Lei Luan, Jian Guo, Xuan Wang, Dong Wu, Jin Liu, Xinyu Chinese Acad Sci Inst Microelect Beijing 10029 Peoples R China Univ Chinese Acad Sci Beijing 10029 Peoples R China

In this paper, a 1-GS/s 12-bit pipelined folding analog-to-digital converter (ADC) fabricated in 40 nm CMOS technology is presented. A new encoding algorithm based on distributed quantization is proposed to simplify the quantization process of the structure with odd folding factor and reduce the hardware consumption of the circuit. The ADC achieves spurious free dynamic range (SFDR) > 72 dB and signal-to-noise and distortion ratio (SNDR) > 57 dB in low input frequencies.

关键词： analog-to-digital converter folding and interpolating odd folding factor encoding algorithm

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