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error control coding for the N-user mod-2 multiple-access channel

IEEE TRANSACTIONS ON INFORMATION THEORY 1998年第4期44卷 1632-1642页

作者： Telang, VP Herro, MA Cirrus Log Commun Prod Div Austin TX 78744 USA Univ Notre Dame Dept Elect & Comp Engn Notre Dame IN 46556 USA

Efficient use of transmission facilities often requires the sharing of resources by a number of users. Commonly used methods of shared media access are time-division multiple access (TDMA), frequency-division multiple access (FDMA), code-division multiple access (CDMA), carrier-sense multiple access (CSMA), etc. In this correspondence we propose a different approach to designing an N-user multiple access system for the binary input binary adder channel, When all users are sending data, the total rate of information transfer is equal to the timeshare rate. However, when fewer than N users are active, the unused channel capacity is used to achieve error control. The extent of error control is inversely proportional to T, the number of active users. We present in detail two coding schemes;the first based on cyclic block codes, particularly BCH codes and Reed-Solomon codes, and the second based on convolutional codes.

关键词： BCA codes convolutional codes error-control coding mod-2 adder channel multiple-access channels variable error-correction capability

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Design of a transport coding scheme for high-quality video over ATM networks

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1997年第2期7卷 358-376页

作者： Parthasarathy, V Modestino, JW Vastola, KS RENSSELAER POLYTECH INST DEPT ELECT COMP & SYST ENGNTROYNY 12180 RENSSELAER POLYTECH INST CTR IMAGE PROC RESTROYNY 12180

In this paper, we explore the design of forward error control (FEC)-based error concealment schemes for digital video transmission on ATM networks. III particular, me study the impact of code selection on the overall performance and provide a judicious code selection strategy, The use of FEC provides an active and powerful means of recovery from packet loss which is particularly useful when the encoded video material has high motion and scene changes, The best technique for applying FEC is tee throttle the source coding rate so that the overall transmission rate after EEC application equals the original unprotected rate, However, the resulting performance then depends on the particular code selected, A well-chosen code provides good protection while allowing little sacrifice in quality and at the same time satisfies specified delay constraints, Our results show that a single code is generally insufficient to provide good performance under all operating conditions, However, a small group of codes can be preselected, using the efficient code-selection strategy described here, which will provide efficient and robust performance over a wide range of channel conditions, We show that this simple code selection strategy is sufficient to select codes judiciously for a nide range of operating conditions and constraints, Employing this selection strategy, we demonstrate that moderate length codes are sufficient to provide good performance while meeting the imposed delay constraint.

关键词： asynchronous transfer mode broadband communications error-control coding image coding integrated services digital networks multimedia services networks Reed-Solomon codes source coding

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On unequal error protection using convolutional codes

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SIGNAL PROCESSING 1999年第1期77卷 63-70页

作者： Brissett, R Sodha, J Department of Computer Science Mathematics and Physics University of the West Indies Cave Hill Campus Barbados

This paper demonstrates the inherent unequal error protection (UEP) nature of punctured convolutional codes to develop two UEP schemes. In both schemes, the UEP level of error protection is better than the original error-control coding and modulation scheme employed. The first scheme is based on utilizing the inherent UEP capability within the columns of the puncturing matrix, without a reduction in information throughput. The second scheme reduces the effective code rate b/nu of a punctured convolutional code created from an original rate 1/nu(o) code. Such a UEP scheme may be of use in a communication system where it is beneficial to briefly reduce the information throughput for a much improved error protection, It is shown that the performance of a simple rate 1/2, constraint length K = 3 code, when transformed to an effective rate 1/3 code, provides a coding gain of approximately 5.2 dB with the use of eight level soft-decision decoding over uncoded BPSK. In general, this UEP technique provides a coding gain of slightly greater than 10 log(10)(b nu(o)/nu) dB over the performance of the original rate 1/nu(o) code using hard-decision Viterbi decoding. A further coding gain of approximately 1.5 dB can be expected with the use of soft-decision decoding. (C) 1999 Elsevier Science B.V. All rights reserved.

关键词： convolutational codes unequal error protection error-control coding

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Improving SSD Read Latency via coding

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IEEE TRANSACTIONS ON COMPUTERS 2020年第12期69卷 1809-1822页

作者： Park, Hyegyeong Moon, Jaekyun Korea Adv Inst Sci & Technol KAIST Sch Elect Engn Daejeon 34141 South Korea

We study the potential enhancement of the read access speed in high-performance solid-state drives (SSDs) by coding, given speed variations across the multiple flash interfaces and assuming occasional local memory failures. Our analysis is based on a queuing model that incorporates both read request failures and NAND element failures. The NAND element failure in the present context reflects various limitations on the memory element level such as bad blocks, dies or chips that cannot be corrected by error control coding (ECC) typically employed to protect pages read off the NAND cells. Our analysis provides a clear picture of the storage-overhead and read-latency trade-offs given read failures and NAND element failures. We investigate two different ways to mitigate the effect of NAND element failures using the notion of multi-class jobs with different priorities. A strong motivation for this work is to understand the reliability requirement of NAND chip components given an additional layer of failure protection, under the latency/storage-overhead constraints.

关键词： Encoding Maintenance engineering Decoding Parity check codes Sensors error correction codes Bandwidth NAND flash memory solid-state drives NAND component failures distributed storage latency analysis queuing theory error-control coding

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SAFETY AND RELIABILITY OF SYNCHRONIZABLE DIGITAL coding IN RAILWAY TRACK-CIRCUITS

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IEEE TRANSACTIONS ON RELIABILITY 1990年第5期39卷 581-591页

作者： HILL, RJ WEEDON, DN BRITISH RAIL NETWORK SE DEPT SIGNALLING & TELECOMMUNCROYDON CR9 1DYENGLAND

The incorporation of digital error-control coding into railway track circuits represents a new approach for track-train data transmission for automatic train control. Methods based on error-probability analysis are presented for assessing the safety and reliability of synchronizable error-control coding in this application. The results for a sample coding scheme have been verified by experimentation using a calibrated source injecting audio-frequency Gaussian noise into a practical track circuit. Safety and reliability must be traded off, although the safety can be increased by incorporating dictionary checking in the code-receiver algorithm and the reliability can be enhanced by allowing single synchronization error correction. The technique demonstrates the possibility of designing a track-circuit data-transmission system to given target safety and reliability levels of the same order of magnitude as the known failure rates of existing equipment.

关键词： SAFETY RAILWAY control SYSTEM RAILWAY TRACK CIRCUIT SYNCHRONIZABLE coding error-control coding

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Galois field arithmetic over GF(p^m) for high-speed/low-power error-control applications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2004年第4期51卷 709-717页

作者： Conway, T Univ Limerick Dept Elect & Comp Engn Limerick Ireland

This paper presents a very large-scale integration implementation of Galois field arithmetic for high-speed error-control coding applications that is based on the field GF(p(m)) with m a small integer such as 2 or 3 and p a prime of sufficient value to generate the required field size. In this case, the Galois field arithmetic operations of addition, multiplication, and inversion are based on architectures using blocks that perform integer arithmetic modulo p. These integer arithmetic operations modulo p have previously been implemented with low delay power products through the use of one hot coding and barrel shifters circuits based on transistor arrays. In. this paper, the same one hot coding and barrel shifters circuits are used to construct circuits that implement addition, multiplication, and inversion over GF(p(m)). The circuits for GF(p(m)) addition and multiplication with p not equal 2, achieve a lower power-delay product than designs based on GF(2(m)). Also, the architecture for GF(p(m)) inversion can be efficiently implemented when m = 2 or m = 3.

关键词： error-control applications error-control coding Galois field arithmetic Galois field inversion Reed Solomon decoding

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A High-Speed Real-Time Binary BCH Decoder

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1993年第2期3卷 138-147页

作者： Wei, Shyue-Win Wei, Che-Ho Natl Chiao Tung Univ Inst Elect Hsinchu 300 Taiwan Natl Chiao Tung Univ Ctr Telecommun Res Hsinchu 300 Taiwan Telecommun Labs Chungli 32099 Taiwan

A high-speed real-time decoder for t-error-correcting binary Bose-Chaudhuri-Hocquenghem (BCH) codes based on a modified step-by-step decoding algorithm is presented. The average operation cycles for decoding each received word is just equal to the block length of the codeword. The decoder is constructed by three modules: the syndrome module, the comparison module, and the error corrector. Since all of the modules can be implemented by systolic circuits, the operation data rate of this decoder can theoretically be up to a rate of the inverse of two logic-gate delays. Based on different VLSI technologies, such as CMOS, BiCMOS and Gab, the decoder can be operated from approximately several hundreds megabits per second to the order of gigabits per second. Thus, the decoder can be applied in the broadband service and video processing. Besides, by avoiding the use of inverse operation in the step-by-step decoding method, the circuit complexity of this decoder can be much less than the standard algebraic method in which the inverse operation is usually required for finding the coefficients of the error-location polynomial. The detailed circuit diagrams of the comparison module and error corrector for the double- and triple-error-correcting binary BCH codes are given for illustration.

关键词： BCH code error-control coding real-time implementation VLSI architecture

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On-line fault monitoring

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 1998年第1-2期12卷 21-27页

作者： Stiffler, JJ Sequoia Syst Inc Marlborough MA 01752 USA

Sequoia's fault-tolerant computers were designed subject to some rather rigid constraints: No single hardware malfunction can generate an undetected error;an integrated circuit is a "black box" that can fail in arbitrary ways, affecting an arbitrary subset of input and output signals;faults can be transient or intermittent with arbitrary durations and repetition intervals. Moreover, the incremental hardware to be used to achieve these goals was to be kept to a minimum. The resulting computers do, to a very large extent, satisfy these constraints. To achieve this, a combination of fault-monitoring techniques was used, including: Bit and nibble error-correcting and error-detecting codes;byte parity codes with orthogonal partitioning;cyclic-residue codes on I/O data transfers;codes designed to protect against address counter overruns on I/O transfers;lossless control-signal compactors. The nature and rationale for these various fault monitors is described as well as the analytical and testing techniques used to estimate the resulting coverage.

关键词： fault tolerance fault detection error-control coding signal compaction fault models

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Robust Packet Video Transport Over Wireless Fading Channels Using a Joint Source-channel coding Approach

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WIRELESS PERSONAL COMMUNICATIONS 2009年第3期48卷 425-439页

作者： Pei, Yong Modestino, James W. Wright State Univ Dept Comp Sci & Engn Dayton OH 45435 USA Univ Miami Dept Elect & Comp Engn Coral Gables FL 33124 USA

In this paper, we address the problem of robust video transmission over wireless networks. Specifically, we consider packet video transmission over wireless IP networks based on the RTP/UDP/IP protocol stack. Digital video delivered over wireless networks is expected to suffer quality degradation from both packet loss and bit errors in the payload. In this paper, both packet loss and bit errors in the payload are considered and the performance of a joint source-channel coding (JSCC) approach employing forward error-correction (FEC) coding schemes for H.263 + video transmission is studied. Results indicate that with an appropriate JSCC approach, FEC-based error-control techniques can significantly improve the packetization efficiency for a given end-to-end quality requirement and lead to more acceptable video delivery quality over time-varying wireless networks. Another important observation is that with a JSCC approach the fading effects of wireless links upon end-to-end video quality are substantially decreased compared to a system without using channel coding, resulting in attractive robust performance characteristics.

关键词： Video transmission RTP UDP/IP error-control coding RCPC codes Joint source-channel coding Rician fading H.263+

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Probabilistic analysis of linear programming decoding

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IEEE TRANSACTIONS ON INFORMATION THEORY 2008年第8期54卷 3565-3578页

作者： Daskalakis, Constantinos Dimakis, Alexandros G. Karp, Richard M. Wainwright, Martin J. Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94704 USA

We initiate the probabilistic analysis of linear programming (LP) decoding of low-density parity-check (LDPC) codes. Specifically, we show that for a random LDPC code ensemble, the linear programming decoder of Feldman et al. succeeds in correcting a constant fraction of errors with high probability. The fraction of correctable errors guaranteed by our analysis surpasses previous nonasymptotic results for LDPC codes, and in particular, exceeds the best previous finite-length result on LP decoding by a factor greater than ten. This improvement stems in part from our analysis of probabilistic bit-flipping channels, as opposed to adversarial channels. At the core of our analysis is a novel combinatorial characterization of LP decoding success, based on the notion of a flow on the Tanner graph of the code. An interesting by-product of our analysis is to establish the existence of "probabilistic expansion" in random bipartite graphs, in which one requires only that almost every (as opposed to every) set of a certain size expands, for sets much larger than in the classical worst case setting.

关键词： binary-symmetric channel (BSC) channel coding error-control coding expanders factor graphs linear programming decoding low-density parity-check (LDPC) codes randomized algorithms sum-product algorithm

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