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A virtual sequencer reveals the dephasing patterns in error-correction code DNA sequencing

National Science Review 2021年第5期8卷 91-100页

作者： Wenxiong Zhou Li Kang Haifeng Duan Shuo Qiao Louis Tao Zitian Chen Yanyi Huang Biomedical Pioneering Innovation Center (BIOPIC) School of Life SciencesBeijing Advanced Innovation Center for Genomics(ICG)and Peking-Tsinghua Center for Life SciencesPeking University Center for Bioinformatics State Key Laboratory of Protein Engineering and Plant Genetic EngineeringPeking University Center for Quantitative Biology Peking University College of Engineering Peking University College of Chemistry and Molecular Engineering Peking University Institute for Cell Analysis Chinese Institute for Brain Research (CIBR)

An error-correction code(ECC) sequencing approach has recently been reported to effectively reduce sequencing errors by interrogating a DNA fragment with three orthogonal degenerate sequencing-by-synthesis(SBS) reactions. However, similar to other non-single-molecule SBS methods, the reaction will gradually lose its synchronization within a molecular colony in ECC sequencing. This phenomenon, called dephasing, causes sequencing error, and in ECC sequencing, induces distinctive dephasing patterns. To understand the characteristic dephasing patterns of the dual-base flowgram in ECC sequencing and to generate a correction algorithm, we built a virtual sequencer in silico. Starting from first principles and based on sequencing chemical reactions, we simulated ECC sequencing results, identified the key factors of dephasing in ECC sequencing chemistry and designed an effective dephasing *** results show that our dephasing algorithm is applicable to sequencing signals with at least 500 cycles, or1000-bp average read length, with acceptably low error rate for further parity checks and ECC *** virtual sequencer with our dephasing algorithm can further be extended to a dichromatic form of ECC sequencing, allowing for a potentially much more accurate sequencing approach.

关键词： DNA sequencing error-correction code dephasing computer simulation sequencing-by-synthesis

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High-Throughput Software-Defined LDPC Encoder and Decoder With x86-Based Data-Level Parallelism

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2025年第1期74卷 50-60页

作者： Yun, Sangbu Choe, Jeongwon Lee, Youngjoo Pohang Univ Sci & Technol POSTECH Dept Elect Engn Pohang 37673 South Korea

In order to realize the high-throughput software-defined low-density parity-check (SD-LDPC) encoder and decoder for 5G communication systems, this paper presents various algorithm-software co-optimization techniques allowing advanced data-level parallelism. We first develop efficient mapping schemes to describe the contemporary 5G LDPC processing with recent x86 single instruction multiple data (SIMD) instructions. Then, the data rate of 5G SD-LDPC processing is remarkably improved by introducing SIMD-aware algorithm-level innovations, e.g., parallel efficient encoding, minimizing branch instructions, approximate check-node processing, and latency-oriented optimization. Compared with the state-of-the-art approaches, experimental results show that the proposed techniques successfully enhance the speed of encoding and decoding operations by 8.1 and 1.5 times, respectively, leading to the high-speed and fully-flexible software-defined radio (SDR) solutions for 5G systems.

关键词： 5G mobile communication Decoding Encoding Single instruction multiple data Iterative decoding Throughput Vectors error-correction code LDPC decoding 5G new radio SIMD SDR wireless communication

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Wireless-Assisted Key Establishment Leveraging Channel Manipulation

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IEEE TRANSACTIONS ON MOBILE COMPUTING 2021年第1期20卷 263-275页

作者： Fang, Song Markwood, Ian Liu, Yao Univ Oklahoma Sch Comp Sci Norman OK 73019 USA BlackHorse Solut Cyber Dev Herndon VA 20171 USA Univ S Florida Dept Comp Sci & Engn Tampa FL 33620 USA

Wireless communication is easily eavesdropped due to the broadcast nature of the wireless medium. This has spurred extensive research into secret key establishment using physical layer characteristics of wireless channels. In all these schemes, the secret keys directly originate from the physical features of the real wireless channel, which is highly dependent on the communication environment nearby. Also, previous schemes require performing information reconciliation, which increases both the costs and the risk of key leakage. In this paper, we exhibit a novel wireless key establishment method allowing the transmitter to specify arbitrary content as the key and cause the receiver to obtain the same key leveraging a channel manipulation technique. We furthermore enable the transmitter to apply error-correction code to the key, so that the receiver can automatically correct any mismatched bits without sending key-related information back to the transmitter over the public channel. Experimental results demonstrate that our key establishment method reaches a success rate as high as 91.0 percent for establishing a 168-bit key between the transmitter and the receiver, and meanwhile the chance that the eavesdropper can infer the key in meter-order range of the receiver is subdued into the range of 0 similar to 0.10 percent.

关键词： Secret key eavesdropping error-correction code key establishment chain

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Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第6期67卷 2103-2113页

作者： Moon, Seungsik Choe, Jeongwon Lee, Youngjoo Pohang Univ Sci & Technol POSTECH Dept Elect Engn Pohang 37673 South Korea

This paper presents an advanced key-equation solver (KES) algorithm that can reduce the computing latency of BCH decoding for the high-speed storage class memory (SCM). Adopting the unfolding algorithm as a factor of two, compared to the conventional iterative KES scheme, the proposed work potentially halves the number of processing cycles for KES module, which is normally dominates the overall BCH decoding latency. In contrast that the straight-forward unfolding method increases the critical delay, we accelerate the major computing path that is activated at the most of SCM lifetime, preserving the critical delay of the proposed KES module as similar to that of the original one. When the minor cases are detected, the recovery processing is added at the end of the corresponding iteration. In order to reduce the additional energy consumption due to the unfolded architecture, we carefully deactivate the internal modules during the accelerated processing, which only necessitate for the recovery cycle. Implementation results show that the proposed KES architecture greatly reduces the decoding latency of arbitrary BCH decoder, leading to the high-speed and reliable emerging storages.

关键词： Decoding Iterative decoding Memory management Indexes Delays Acceleration BCH decoding emerging nonvolatile memory error-correction code low-latency processing VLSI

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Simplified 2-Dimensional Scaled Min-Sum Algorithm for LDPC Decoder

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JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY 2017年第3期12卷 1262-1270页

作者： Cho, Keol Lee, Wang-Heon Chung, Ki-Seok Hanyang Univ Dept Elect Engn Seoul South Korea Hanyang Univ Dept Elect & Comp Engn Seoul South Korea Hansei Univ Dept IT Gunpo Si Gyeonggi Do South Korea

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

关键词： error-correction code Low-density parity-check code LDPC decoder Min-sum algorithm Normalized min-sum algorithm

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Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第3期69卷 999-1003页

作者： Yun, Sangbu Kong, Byeong Yong Lee, Youngjoo Pohang Univ Sci & Technol Dept Elect Engn Pohang 37673 South Korea Kongju Natl Univ Div Elect Elect & Control Engn Cheonan 31080 South Korea

A practical min-sum algorithm is associated with tree-based comparison units for the check-node operation, being a major bottleneck in designing low-cost and energy-efficient low-density parity-check (LDPC) decoders. In this brief, we present a cost-effective LDPC decoder architecture by changing its internal computing resolution for the power-hungry check-node processing. The proposed mixed-resolution comparison offers significant advantages in terms of both area and energy, while achieving error-correcting performance within 0.3 dB of the previous normalized min-sum (NMS) algorithm for a (1644, 1408) quasi-cyclic LDPC code of the 5G New Radio specifications. Compared to the baseline NMS architecture, the proposed decoder in a 65-nm CMOS technology reduces the hardware complexity and the power consumption by 28.4% and 23.1%, respectively, enhancing the area efficiency by more than 88.2%.

关键词： Decoding Computer architecture Complexity theory Multiplexing Hardware Iterative decoding Indexes error-correction code LDPC decoding cost-effective energy-efficient wireless communication

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Entanglement-assisted concatenated quantum codes

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PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES OF THE UNITED STATES OF AMERICA 2022年第24期119卷 e2202235119-e2202235119页

作者： Fan, Jihao Li, Jun Zhou, Yongbin Hsieh, Min-Hsiu Poor, H. Vincent Nanjing Univ Sci & Technol Sch Cyber Sci & Engn Nanjing 210094 Peoples R China Nanjing Univ Sci & Technol Sch Elect & Opt Engn Nanjing 210094 Peoples R China Hon Hai Res Inst Quantum Comp Res Ctr Taipei 114 Taiwan Princeton Univ Dept Elect & Comp Engn Princeton NJ 08544 USA

Entanglement-assisted concatenated quantum codes (EACQCs), constructed by concatenating two quantum codes, are proposed. These EACQCs show significant advantages over standard concatenated quantum codes (CQCs). First, we prove that, unlike standard CQCs, EACQCs can beat the nondegenerate Hamming bound for entanglement-assisted quantum error-correction codes (EAQECCs). Second, we construct families of EACQCs with parameters better than the best-known standard quantum error-correction codes (QECCs) and EAQECCs. Moreover, these EACQCs require very few Einstein-Podolsky-Rosen (EPR) pairs to begin with. Finally, it is shown that EACQCs make entanglement-assisted quantum communication possible, even if the ebits are noisy. Furthermore, EACQCs can outperform CQCs in entanglement fidelity over depolarizing channels if the ebits are less noisy than the qubits. We show that the error-probability threshold of EACQCs is larger than that of CQCs when the error rate of ebits is sufficiently lower than that of qubits. Specifically, we derive a high threshold of 47% when the error probability of the preshared entanglement is 1% to that of qubits.

关键词： entanglement-assisted quantum error-correction code error-correction code concatenated quantum code quantum Hamming bound entanglement fidelity

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A General Class of Maximal codes for Computer Applications

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IEEE Transactions on Computers 1972年第12期C-21卷 1322-1331页

作者： Hong, Se June Patel, Arvind M. Systems Products Division IBM Corporation Pouzlik-eepsie N. Y 12602 United States Systems Development Division TBM Corporation Poughkeepsie N. Y. 12602 United States

The error-correcting codes for symbols from GF (2b) are often used for correction of byte-errors in binary data. In these byte-error-correcting codes each check symbol in GF (2b) is expressed as b binary check digits and each information symbol in GF (2b), likewise, is expressed by b binary information digits. A new class of codes for single-byte-error correction is presented. The code is general in that the code structure does not depend on symbols from GF (2b). In particular, the number of check bits are not restricted to the multiples of b as in the case of the codes derived from GF (2b) codes. The new codes are either perfect or maximal and are easily implementable using shift registers. Copyright © 1972 by The Institute of Electrical and Electronics Engineers, Inc.

关键词： Adjacent-error correction byte-error correction error-correction code maximal codes shift-register implementation

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An H-ARQ transmission scheme based on rateless code

An H-ARQ transmission scheme based on rateless code

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6th International Symposium on Computational Intelligence and Design (ISCID)

作者： Wang, Yin Lei, Weijia Xie, Xianzhong Chongqing Univ Posts & Telecommun Inst Personal Commun Chongqing Peoples R China

ISBN: (纸本)9780769550794

In the traditional cross-layer redundancy optimization allocation, the system can't fully adapt the time-varying channel, so an H-ARQ transmission mechanism based on rateless code is proposed in this paper. The source uses LT-code as error-erasure code to encode the original packets in the packet-level, every bit of one coded packets is encoded by using LT-code as error-correction code in physical layer. The Receiver can set an upper limit value of the received bits to control decoding overhead, it sends a feedback to the source when the receiver decodes all the bits of a coded packet successfully, and otherwise it will discard the coded packet and send a feedback. Simulation results show that our mechanism improves the transmission efficiency greatly comparing to the mechanism with constant rate for coding transmission.

关键词： rateless code H-ARQ error-erasure code error-correction code

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Analytical Estimation of Self-Orthogonal code Multithreshold Decoders Efficiency 9

Analytical Estimation of Self-Orthogonal Code Multithreshold...

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9th Mediterranean Conference on Embedded Computing (MECO)

作者： Ovechkin, G., V Grinchenko, N. N. Svetlov, G., V Fokina, N. S. Ryazan State Radio Engn Univ Fac Comp Engn Ryazan Russia RPTP Granit Ryazan Russia

ISBN: (纸本)9781728169491

Multithreshold decoders (MTD) of self-orthogonal codes (SOC) for channels with errors as well as erasure channels are discussed. The work offers analytical estimations of MTD efficiency considering SOC structure as well as decoder parameters. These estimations are shown to correspond well with computer simulation results allowing us to estimate the area of MTD efficient operation in the conditions of high noise level.

关键词： error-correction code multithreshold decoder self-orthogonal code binary symmetric channel erasure channel lower bound bit error/erasure rate estimation

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