Soft source decoders, in conjunction with error correcting channel codes, can be used to improve the error resilience of digital communication systems based on variable length codes. In this paper, we present a novel ...
详细信息
ISBN:
(纸本)9781479928934
Soft source decoders, in conjunction with error correcting channel codes, can be used to improve the error resilience of digital communication systems based on variable length codes. In this paper, we present a novel approach to reduce the complexity of maximum a posteriori variable length decoders implemented on a bit-symbol trellis. The decoding algorithm is implemented in a narrow corridor along the trellis diagonal to reduce the decoder complexity. Furthermore, by periodically adjusting the corridor boundaries, a significant reduction in complexity is achieved at the price of a small degradation in decoding performance.
In this paper, a hardware/software co-design approach is proposed to parse the video bitstream which conforms to various video compression standards. The layered structure of the syntax elements in video bitstream...
详细信息
In this paper, a hardware/software co-design approach is proposed to parse the video bitstream which conforms to various video compression standards. The layered structure of the syntax elements in video bitstreams is analyzed. Then a hardware/software partition is proposed accordingly. Due to the high data rate, syntax elements in slice data and lower layers are commonly parsed by hardware. As for syntax elements in slice header and upper layers, we proposed a hw/sw co-design approach in order to combine the advantage of hardware acceleration and software flexibility, specific hardware accelerators are designed to parse these codes. But the parsing process of these codes in slice header and upper layer is controlled by software instead of hardware Finite state machine (FSM). This approach can speed up the process of Variable-Length Decoding (VLD) while it still has the flexibility to support multiple video coding standards.
暂无评论