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5th International Conference on Computational Intelligence and Applications (ICCIA)

作者： Kim, min-Ho Park, Kyeong-Bin Chung, Ki-Seok Hanyang Univ Dept Elect & Comp Engn Seoul South Korea

ISBN: (纸本)9781728160429

The extended min-sum algorithm (EMS) for decoding non-binary low density parity check (NB-LDPC) codes reduces the decoding complexity by truncating the message vector by retaining only the most reliable symbols. However, the EMS algorithm does not consider that the noise of the received codeword is gradually reduced as the iteration count goes up. In this paper, we propose a low-complexity adaptive EMS algorithm, called threshold-based EMS (TB-EMS). The TB-EMS algorithm has a simple adaptive rule to calculate the new message vector length compared to the A-EMS. The proposed algorithm selects one of two message vector lengths. Experimental results show that the proposed algorithm reduces the decoding complexity with minimal performance degradation compared with the EMS algorithm. Further, the decoding performance of the TB-EMS is better than A-EMS.

关键词： Non-Binary Low Density Parity Check codes extended min-sum algorithm Low-complexity decoding Message truncation rule

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Selection-based Low-cost Check Node Operation for extended min-sum algorithm

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KSII TRANSACTIONS ON INTERNET AND INFORMATION SYSTEMS 2021年第2期15卷 485-499页

作者： Park, Kyeongbin Chung, Ki-Seok Hanyang Univ 222 Wangsimni Ro Seoul 133791 South Korea

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

关键词： Non-binary Low-density Parity Check extended min-sum algorithm Hardware Optimization

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Low complexity NB-LDPC decoder based on shared comparator architecture for ECN/EVN

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The Journal of China Universities of Posts and Telecommunications 2018年第3期25卷 65-70页

作者： Sun Shulong Liu Lei Lin min Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai 200050 China University of Chinese Academy of Sciences Beijing 100049 China

Non-binary low density parity check （NB-LDPC） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are required. They have better burst error correcting performance, especially with high order Galois fields （GF）. A shared comparator （SCOMP） architecture for elementary of check node （ECN）/elementary of variable node （EVN） to reduce decoder complexity is introduced because high complexity of check node （CN） and variable node （VN） prevent NB-LDPC decoder from widely applications. The decoder over GF（16） is based on the extended rain-sum （EMS） algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency, the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when SCOMP architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF（64） or GF（256）. Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications.

关键词： extended min-sum algorithm non-binary LDPC decoder shared comparator architecture

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Iterative Decoding algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes

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IEEE TRANSACTIONS ON COMMUNICATIONS 2014年第6期62卷 1779-1789页

作者： Chang, Hsiu-Chi Chang, Hsie-Chia Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan Natl Chiao Tung Univ Inst Elect Hsinchu 300 Taiwan

This paper presents two iterative decoding algorithms for a class of non-binary two-step majority-logic (NB-TS-MLG) decodable cyclic codes. A partial parallel decoding scheme is also introduced to provide a balanced trade-off between decoding speed and storage requirements. Unlike non-binary one-step MLG decodable cyclic codes, the Tanner graphs of which are 4-cycle-free, NB-TS-MLG decodable cyclic codes contain a large number of short cycles of length 4, which tend to degrade decoding performance. The proposed algorithms utilize the orthogonal structure of the parity-check matrices of the codes to resolve the degrading effects of the short cycles of length 4. Simulation results demonstrate that the NB-TS-MLG decodable cyclic codes decoded with the proposed algorithms offer coding gains as much as 2.5 dB over Reed-Solomon codes of the same lengths and rates decoded with either hard-decision or algebraic soft decision decoding.

关键词： extended min-sum algorithm majority-logic decoding non-binary LDPC codes cyclic codes

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A Simplified min-sum Decoding algorithm for Non-Binary LDPC Codes

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IEEE TRANSACTIONS ON COMMUNICATIONS 2013年第1期61卷 24-32页

作者： Wang, Chung-Li Chen, Xiaoheng Li, Zongwang Yang, Shaohua LSI Corp Milpitas CA 95035 USA Microsoft Corp Redmond WA 98052 USA

Non-binary low-density parity-check codes are robust to various channel impairments. However, based on the existing decoding algorithms, the decoder implementations are expensive because of their excessive computational complexity and memory usage. Based on the combinatorial optimization, we present an approximation method for the check node processing. The simulation results demonstrate that our scheme has small performance loss over the additive white Gaussian noise channel and independent Rayleigh fading channel. Furthermore, the proposed reduced-complexity realization provides significant savings on hardware, so it yields a good performance-complexity tradeoff and can be efficiently implemented.

关键词： Low-density parity-check (LDPC) codes non-binary codes iterative decoding extended min-sum algorithm

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A Systolic LLR Generation Architecture for Non-Binary LDPC Decoders

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IEEE COMMUNICATIONS LETTERS 2011年第8期15卷 851-853页

作者： Al Ghouwayel, Ali Boutillon, Emmanuel Univ Europeenne Bretagne Lab STICC CNRS UBS F-56100 Lorient France

Non-Binary LDPC codes offer higher performances than their binary counterpart but suffer from higher decoding complexity. A solution to reduce the decoding complexity is to use the extended min-sum algorithm. The first step of this algorithm requires the generation of the first n(m) largest Log-Likelihood Ratio (LLR), sorted in increasing order, of each received symbol. In the case where GF(q) symbols are transmitted using a BPSK modulation, we propose a simple systolic architecture that generates the sorted list of symbols.

关键词： Non-binary LDPC codes extended min-sum algorithm systolic architecture

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A 5G-code based iterative Non-Binary LDPC decoder 28

A 5G-code based iterative Non-Binary LDPC decoder

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28th IEEE International Conference on Electronics, Circuits, and Systems (IEEE ICECS)

作者： Chytas, Dimitris Paliouras, Vassilis Univ Patras Dept Elect & Comp Engn Patras Greece

ISBN: (纸本)9781728182810

This paper proposes an iterative Non-Binary LDPC (NBLDPC) decoder for non-binary codes constructed using the 5G base matrices. Motivated by the binary to non-binary replacement method, we construct NB-LDPC matrices devised directly from the 5G base matrices. Subsequently, we develop an iterative decoding scheme able to facilitate parallelism due to its low complexity and to offer high performance due to its fast convergence. BER plots comparing min-sum binary decoder (over 5G base matrices) to our proposed NB decoder reveal a performance gain of 0.5 dB in certain cases. Furthermore, hardware synthesis results obtained for a 45-nm ASIC technology are provided in order to quantify the throughput rate and area requirements of the proposed architecture. It is shown that the proposed decoding architecture, because of its independence on the lifting size factor, can offer higher throughput rate than the binary ones for small codeword lengths and code rates. In addition, as Galois Field (GF) order increases, the throughput rate increases too. Finally, the throughput-to-area show that the proposed NB architecture is generally suitable for small lifting size factors.

关键词： 5G base matrices Nonbinary low density parity check codes construction Nonbinary low density parity check decoders extended min-sum algorithm iterative decoding throughput ASIC

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High throughput and low complexity implementation of NB-LDPC decoder based on EMS algorithm

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IEICE ELECTRONICS EXPRESS 2016年第17期13卷 20160653-20160653页

作者： Long, Sun Shu min, Lin Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol Shanghai 200050 Peoples R China

Non-Binary Low-Density-Parity-Check codes (NB-LDPC) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implement a kind of high-throughput low-complexity irregular quasicyclic NB-LDPC decoder over GF (16) based on extended min-sum (EMS) algorithm. Double clocks are adopted in this paper. The low frequency clock at 60 MHz serves as the system clock and the high frequency clock at 480 MHz works for check nodes and variable nodes thus they can be reused 8 times during one system clock period as a result the complexity can be largely reduced. Synthesis result shows that the throughput can achieve 68.57 Mbps at 5 iterations. FPGA testing result shows that the decoder has little performance degradation compared with its floating model and it can provide about 0.5 dB coding gain compared with its binary LDPC code of the same block length. The proposed architecture can be conveniently extended to higher Galois Filed such as GF (64) or GF (256) and it can be applied for different code length and rate by modifying a slight part of the decoder. Compared with previous works, the decoder proposed in this paper is more efficient for practical applications.

关键词： extended min-sum algorithm FPGA low complexity high throughput non-binary LDPC decoder

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Frame synchronization method for BDS B2a signal under the constraint of Non-binary LDPC code

Frame synchronization method for BDS B2a signal under the co...

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第十一届中国卫星导航年会

作者： Bowen Jiang Lin Chen Hongchen Pan Yuqi Liu Jiangyu Chen Shaobin Guo The 29th Research Institute of China Electronics Technology Group Corporation

Low-Density Parity-Check(LDPC) Code has become one of the best coding technologies at present because of its low complexity iterative decoding algorithm and its performance with further close to the S

关键词： Non-binary LDPC codes Frame Synchronization navigation message low SNR extended min-sum algorithm

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