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检索条件"主题词=External memory algorithm"
9 条 记 录,以下是1-10 订阅
Out-of-core algorithms for Binary Partition Hierarchies
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JOURNAL OF MATHEMATICAL IMAGING AND VISION 2025年 第2期67卷
作者: Lefevre, Josselin Cousty, Jean Perret, Benjamin Phelippeau, Harold Univ Gustave Eiffel CNRS LIGM F-77454 Marne La Vallee France Thermo Fisher Sci Bordeaux France
Binary partition hierarchies (BPH) and minimum spanning trees are essential data structures for hierarchical analysis, such as quasi-flat zones and watershed segmentation. Traditional BPH construction algorithms are l... 详细信息
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A Lightweight algorithm for Computing BWT from Suffix Array in Disk  8th
A Lightweight Algorithm for Computing BWT from Suffix Array ...
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8th International Symposium on Parallel Architectures, algorithms, and Programming (PAAP)
作者: Xie, Jing Yi Lao, Bin Nong, Ge Sun Yat Sen Univ Dept Comp Sci Guangzhou Guangdong Peoples R China SYSU CMU Shunde Int Joint Res Inst Shunde Peoples R China
The Burrows-Wheeler transform (BWT) and the suffix array (SA) of an input string are important data structures widely used in modern bioinformatics researches such as full-text search, alignment etc. In this paper, we... 详细信息
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Challenges of Programming a System with Heterogeneous Memories and Heterogeneous Processors  16
Challenges of Programming a System with Heterogeneous Memori...
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International Symposium on memory Systems (MEMSYS)
作者: Che, Shuai Basu, Arkaprava Gallmeier, Jonathan Adv Micro Devices Inc Sunnyvale CA 94088 USA
Recently there has been significant development and innovation in both frontiers of Heterogeneous memory and Heterogeneous Compute domains. This paper summarizes the challenges, surveys related work, and proposes poss... 详细信息
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I/O efficient algorithms for the minimum cut problem on unweighted undirected graphs
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THEORETICAL COMPUTER SCIENCE 2015年 第1期575卷 33-41页
作者: Bhushan, Alka Sajith, G. Indian Inst Technol Guwahati Dept Comp Sci & Engn Gauhati 781039 Assam India
The problem of finding the minimum cut of an undirected unweighted graph is studied on the external memory model. First, a lower bound of Omega((E/V)Sort(V)) on the number of I/Os is shown for the problem, where V is ... 详细信息
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An external memory algorithm of Maxima-Finding Problems
An External Memory Algorithm of Maxima-Finding Problems
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1st International Workshop on Education Technology and Computer Science
作者: Gui, Xiang-Quan Zhang, Yuan-Ping Li, Li Yong, Xue-Rong Lanzhou Univ Technol Coll Comp & Commun Lanzhou 730050 Gansu Peoples R China Univ Puerto Rico Dept Math Mayaguez 00681 PR USA
Maxima-finding problems are the fundamental problem in computational geometry with a great deal of application in many areas, and it has resurfaced with the advent of Skyline Queries for relational databases and data ... 详细信息
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external memory k-Bisimulation Reduction of Big Graphs  13
External Memory k-Bisimulation Reduction of Big Graphs
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22nd ACM International Conference on Information and Knowledge Management (CIKM)
作者: Luo, Yongming Fletcher, George H. L. Hidders, Jan Wu, Yuqing De Bra, Paul Eindhoven Univ Technol Eindhoven Netherlands Delft Univ Technol Delft Netherlands Indiana Univ Bloomington IN USA
In this paper, we present, to our knowledge, the first known I/O efficient solutions for computing the k-bisimulation partition of a massive directed graph, and performing maintenance of such a partition upon updates ... 详细信息
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external memory algorithms for string problems
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FUNDAMENTA INFORMATICAE 2008年 第1期84卷 17-32页
作者: Roh, Kangho Crochemore, Maxime Iliopoulos, Costas S. Park, Kunsoo Seoul Natl Univ Sch Comp Sci & Engn Seoul 151744 South Korea Kings Coll London Dept Comp Sci London England Univ Paris Est Paris France
In this paper we present external memory algorithms for some string problems. external memory algorithms have been developed in many research areas, as the speed gap between fast internal memory and slow external memo... 详细信息
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Incremental analysis of large VLSI Layouts
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INTEGRATION-THE VLSI JOURNAL 2009年 第2期42卷 203-216页
作者: Agrawal, Akash Gupta, Prosenjit Mentor Graph Corp Hyderabad 500082 Andhra Pradesh India Int Inst Informat Technol Hyderabad Andhra Pradesh India
The verification of VLSI layouts is an important and expensive step in physical design process and has significant contribution in overall design cycle time. Design rule checking, connectivity extraction and device ex... 详细信息
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Scanning multiple sequences via cache memory
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algorithmICA 2003年 第1期35卷 75-93页
作者: Mehlhorn, K Sanders, P Max Planck Inst Informat D-66123 Saarbrucken Germany
We consider the simple problem of scanning multiple sequences. There are k sequences of total length N which are to be scanned concurrently. One pointer into each sequence is maintained and an adversary specifies whic... 详细信息
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