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Design and HDL Implementation of Pulse-Arrival-Time Estimation Using XGBoost Regression With Tree-Recycling Architecture

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IEEE ACCESS 2025年 13卷 27596-27609页

作者： Choi, Hyo-Jeong Um, Ji-Yong Kumoh Natl Inst Technol Dept Med IT Convergence Engn Gumi Si 39253 South Korea

This paper presents a pulse-arrival-time (PAT) estimation scheme using Extreme Gradient Boosting (XGBoost) regression and its implementation with hardware description language (HDL). PAT is a significant metric for the estimation of pulse wave velocity (PWV) and blood pressure. We leverage morphological features of single photoplethysmogram (PPG) waveforms and subject-specific parameters to estimate PAT values through a decision tree ensemble regression model. XGBoost regression is adopted for PAT estimation through a comparative study conducted in software. To enable the integration of the regression model into a single chip, we propose a tree-recycling architecture for an area-efficient implementation of the decision tree ensemble model. The proposed PAT estimation has been implemented on a field-programmable gate array (FPGA, Artix7, Xilinx) for real-time verification using a dataset. Additionally, the active area of the proposed scheme in an integrated circuit was estimated after the place-and-route (PnR) procedure, resulting in an area of 1.44 mm2. We utilized the Vital Signs DataBase (VitalDB) for training and testing the proposed PAT estimation in a software-hardware co-design framework. Validation on 80 subjects yielded a determination coefficient (R2) of 0.983 in the linear regression analysis after implementing the HDL on an FPGA.

关键词： Estimation Hardware Biomedical monitoring Regression tree analysis field programmable gate arrays Elasticity Hardware design languages Computer architecture Boosting Training Pulse arrival time decision tree ensemble model extreme gradient boosting regression field programmable gate array tree-recycling architecture hardware description language

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A complex-valued time varying zeroing neural network model for synchronization of complex chaotic systems

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NONLINEAR DYNAMICS 2025年第6期113卷 5471-5491页

作者： Jin, Jie Fang, Jing Chen, Chaoyang Li, Zhijing Yu, Fei Hunan Univ Sci & Technol Sanya Inst Sanya 572024 Hainan Peoples R China Hunan Univ Sci & Technol Sch Informat & Elect Engn Xiangtan 411201 Hunan Peoples R China Changsha Med Univ Sch Informat Engn Changsha 410219 Hunan Peoples R China Changsha Univ Sci & Technol Sch Comp & Commun Engn Changsha 410114 Hunan Peoples R China

Zeroing neural network (ZNN) is an effective tool for solving the synchronization problem of chaotic systems and has received widespread attention. However, previous ZNN models only focused on the synchronization problem of real chaotic systems, failing to tackle the synchronization problem of complex chaotic systems. Based on this, this paper proposes a novel complex-valued time varying zeroing neural network (CVTVZNN) model. This paper rigorously derives the fixed-time convergence and external noise suppression ability of the CVTVZNN model in solving the synchronization problem of complex chaotic systems. Through the results of three numerical experiments on the synchronization of complex Chen chaotic system, complex autonomous chaotic system and complex dynamos chaotic system, verified that the CVTVZNN model has faster convergence speed and higher accuracy in suppressing disturbances compared to other existing ZNN models. It is worth noting that the experimental results show that the CVTVZNN model only takes about 0.00115 s to complete the synchronization task, whether in the noise-free or in environments with external noise. However, in the same experimental environment, other models either cannot achieve synchronization at all, or require at least 0.217 s, which is at least 188 times the synchronization time achieved by the CVTVZNN model. Furthermore, its practical application value has been further demonstrated through its implementation on field programmable gate array.

关键词： Zeroing neural network Complex chaotic system synchronization Fixed-time convergence Robustness field programmable gate array

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FPGA Design, Implementation, and Breadboard Development of an Innovative SCCC Telemetry

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ELECTRONICS 2025年第9期14卷 1786-1786页

作者： Corsinovi, Nico Bertolucci, Matteo Vagaggini, Simone Fanucci, Luca Univ Pisa Dept Informat Engn Via G Caruso n 16 I-56122 Pisa Italy IngeniArs Srl Via Ponte Piglieri 8 I-56121 Pisa Italy

In recent years, missions requiring payload telemetry data transmission to ground stations have increasingly demanded a higher bandwidth. Traditional ranging techniques for spacecraft position determination often use a dedicated spectrum, reducing the available bandwidth for telemetry. To overcome this limitation, a transmission system capable of simultaneously sending high data-rate telemetry and ranging signals within the same bandwidth represents a key advancement for modern space missions, particularly Lagrangian science missions and planetary probes. To enhance the technological readiness of such a system, a hardware demonstrator has been developed using the AMD Xilinx (San Jose, CA, USA) ZCU111 field programmable gate array (FPGA), selected for its high-speed digital signal processing capabilities and integrated converters. The system, in this preliminary breadboarding phase, operates at a fixed telemetry rate of 4.25 Msym/s and a ranging rate of 2.987 Mchip/s, constrained within a 10 MHz bandwidth typical for science missions. Despite these limitations, tests demonstrated that integrating telemetry with Pseudo Noise (PN) Ranging introduces negligible implementation losses compared to telemetry-only transmission. The system also supports high-order modulations up to 64-APSK, improving spectral efficiency within the available bandwidth. Although some limitations have been found in the use of very high-order modulations, this prototype demonstrates the feasibility of integrating advanced coding techniques with PN Ranging.

关键词： telemetry pseudo-noise ranging serially concatenated convolutional codes SCCC regenerative ranging T2B T4B field programmable gate array FPGA breadboard high data rate spacecraft orbit tracking satellite communication

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Low-Cost and High-Throughput Hardware Accelerator for Deblocking Filter in HEVC

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IETE JOURNAL OF RESEARCH 2025年第3期71卷 909-918页

作者： Saravanan, P. Megalingam, R. Sanjana, S. Priyadharshini, T. Sharon Prashanth, S. Kanna, P. Vignesh PSG Coll Technol Dept ECE Coimbatore India Juniper Network India Pvt Ltd Bangalore India Oracle Financial Serv Software Ltd Bangalore India

This paper proposes a low-cost and high-throughput hardware accelerator for the deblocking filter in the encoder and decoder of high-efficiency video coding (HEVC). The total image is split into CTUs (coding tree units) of size 64 x 64 pixels each, which are further divided into 32 x 32 blocks and individually processed. Parallelism is simultaneously applied in this design to filter two luma edges and one chroma edge. In order to minimize the area utilization, the same filter is used for filtering both horizontal and vertical edges. The proposed architecture takes 36 clock cycles to process a 32 x 32 block of the image. The design is implemented in Virtex-6 and Zybo FPGA boards and also in the Cadence tool. The pipelining techniques are used effectively at various levels to provide a high-throughput design, which supports the deblocking of a 16 K UHD (ultra-high definition) video at 134 frames per second (fps).

关键词： Application-specific integrated circuits deblocking filter field programmable gate array filtering order hardware accelerator high-efficiency video coding

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Towards Secure Runtime Customizable Trusted Execution Environment on FPGA-SoC

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IEEE TRANSACTIONS ON COMPUTERS 2024年第4期73卷 1138-1151页

作者： Wang, Yanling Chang, Xiaolin Zhu, Haoran Wang, Jianhua Gong, Yanwei Li, Lin Beijing Jiaotong Univ Beijing Key Lab Secur & Privacy Intelligent Transp Beijing 100044 Peoples R China

Processing sensitive data and deploying well-designed Intellectual Property (IP) cores on remote field programmable gate array (FPGA) are prone to private data leakage and IP theft. One effective solution is constructing Trusted Execution Environment (TEE) and its secure boot process on FPGA-SoC (FPGA System on Chip). This paper aims to establish Secure Runtime Customizable TEE (SrcTEE) on FPGA-SoC through the design of a novel secure boot scheme and the design of the following three components: 1) CrloadIP, which enforces access control on TEE applications deploying IP at runtime such that SrcTEE can alleviate threats from unauthorized TEE applications and then SrcTEE can be adjusted dynamically and securely;2) CexecIP, which not only enables the execution of newly-installed IP cores without modifying the operating system of FPGA-SoC TEE, but also prevents insider attacks from executing IPs in SrcTEE;3) CremoAT, which can provide the newly-measured SrcTEE state and establish a secure communication path between remote verifiers and SrcTEE. Our secure boot scheme supports refreshable root trust key, and assures the authenticity and integrity of boot codes during the SrcTEE booting process. We conduct a security analysis of SrcTEE and its performance evaluation on Xilinx Zynq UltraScale+ XCZU15EG 2FFVB1156 MPSoC.

关键词： field programmable gate arrays Runtime IP networks Codes System-on-chip Access control Random access memory field programmable gate array intellectual property secure boot system on chip trusted execution environment

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Large-Scale Bio-Inspired FPGA Models for Path Planning

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2024年第1期18卷 51-62页

作者： Wang, Kuanchuan Wang, Jiang Hao, Xinyu Deng, Bin Zhang, Zhen Yi, Guosheng Tianjin Univ Sch Elect & Informat Engn Tianjin 300072 Peoples R China

The hippocampus provides significant inspiration for spatial navigation and memory in both humans and animals. Constructing large-scale spiking neural network (SNN) models based on the biological neural systems is an important approach to comprehend the computational principles and cognitive function of the hippocampus. Such models are usually implemented on neuromorphic computing platforms, which often have limited computing resources that constrain the achievable scale of the network. This work introduces a series of digital design methods to realize a field-programmable gate array (FPGA) friendly SNN model. The methods include FPGA-friendly nonlinear calculation modules and a fixed-point design algorithm. A brain-inspired large-scale SNN of similar to 21 k place cells for path planning is mapped on FPGA. The results show that the path planning tasks in different environments are finished in real-time and the firing activities of place cells are successfully reproduced. With these methods, the achievable network size on one FPGA chip is increased by 1595 times with higher resource usage efficiency and faster computation speed compared to the state-of-the-art.

关键词： field programmable gate array FPGA-friendly design fixed-point design path planning spiking neural network

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True random calibration method and application of tapped delay line-TDC with spontaneous parametric down-conversion system

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MEASUREMENT 2025年 251卷

作者： Jin, Zhihan Yu, Bing Chu, Junwei Kang, Qing Li, Jianjun Chinese Acad Sci Hefei Inst Phys Sci Anhui Prov Key Lab Opt Quantitat Remote Sensing Hefei 230031 Anhui Peoples R China Univ Sci & Technol China Hefei 230026 Anhui Peoples R China Xian Inst Appl Opt Xian 710065 Shanxi Peoples R China

The paper proposes a true random calibration method for field programmable gate array (FPGA) based tapped delay line (TDL)-time-to-digital converters (TDCs), which is suitable for spontaneous parametric downconversion (SPDC) systems. The Poisson distribution of single-photon detector (SPD) signals based on a Geiger-mode avalanche photodiode (GM-APD) in the SPDC system makes the SPD function as both a detection device and a quantum random pulse generator (QRPG), which can be used for the true random code density calibration of TDL-TDCs to obtain the nonlinear calibration factors. This method neither adds any system modules nor disrupts the measurement process. Instead, it improves the timeliness of TDL-TDC bin-width calibration in measurement environments featuring significant ambient variations, making it applicable to long-term continuous measurements and reducing measurement uncertainty.

关键词： Single-photon detector Quantum random pulse generator Time-to-digital converter field programmable gate array Calibration Code density test

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A framework for detecting high-performance cardiac arrhythmias using deep inference engine on FPGA and higher-order spectral distribution

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MECHANICAL SYSTEMS AND SIGNAL PROCESSING 2025年 228卷

作者： Karthikeyani, S. Sasipriya, S. Ramkumar, M. Sri Krishna Coll Engn & Technol Dept Elect & Commun Engn Coimbatore 641008 India

Cardiac arrhythmias (CA) are critical health conditions. In such a case, highly accurate detection leads to better management and, therefore, better treatment. Here, this paper presents a novel high-performance detection framework for cardiac arrhythmias based on advanced signal processing algorithms with deep learning on a field programmable gate array (FPGA) towards achieving real-time performances and even higher accuracy. ECG signals are initially analyzed by using compressive sensing theory to obtain sparsity, and from that, the adaptive compressive sensing framework is created. This compressive sensing framework adapts the sensing matrix step by step through compression via the Hybrid Reptile Search Algorithm integrated with the Garra Rufa Algorithm (Hyb-RSA-GRA). The adapted sensing matrix renders signal reconstruction efficient through Bayesian Regularization-Backpropagation Neural Network (BRBNN). The new arrhythmia detection framework employs the possibility of higher-order spectral distribution (HoSD) in extracting finer patterns from ECGs that describe arrhythmia. The task of classification uses a pre-trained Graph Convolutional Neural Network (GCNN) acting as a Deep Inference Engine on the FPGA to support real-time, robust identification of the type of arrhythmias such as N (normal beat), S (supraventricular ectopic beat), V (ventricular ectopic beat), F (fusion beat), and U (unidentified beat). The proposed FPGA implementation reveals better performance with high accuracy, sensitivity, specificity, precision, recall, and F1-score with optimized power dissipation, resource utilization, and delay metrics. Furthermore, the compressive sensing framework guarantees low MSE, reduced RMSE, high SNR, and an improved reconstruction probability. All the above results demonstrate the capability of the framework in accurate prediction and hardware efficiency, hence making it a robust solution for cardiac arrhythmia detection.

关键词： Cardiac arrhythmia field programmable gate array Electrocardiograms ECG sparsity Deep learning Deep inference engine

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A dual-neuron memristive hopfield neural network and its application in image encryption

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NONLINEAR DYNAMICS 2025年第14期113卷 18705-18726页

作者： Liu, Lin Huang, Yi Chen, Zuguo Chen, Chaoyang Chen, Lei Yao, Wei Jin, Jie Hunan Univ Sci & Technol Sanya Inst Sanya 572024 Hainan Peoples R China Hunan Univ Sci & Technol Sch Phys & Elect Sci Xiangtan 411201 Hunan Peoples R China Changsha Med Univ Sch Informat Engn Changsha 410219 Hunan Peoples R China Changsha Univ Sci & Technol Sch Comp & Commun Engn Changsha 410114 Hunan Peoples R China

As one of the four basic electronic components, memristors have been widely applied in artificial neural networks in recent years. However, most of the existing researches focus on the application of memristors in artificial neural networks with three or more neurons, and the artificial neural networks with two neurons are rarely reported. Therefore, a one equilibrium point dual-neuron memristive Hopfield neural network (DNMHNN) model with a memristor serving as the coupling synapse between neurons is proposed in this work. In this research, the chaotic dynamic characteristics of the proposed DNMHNN model are analyzed by various fundamental dynamic analysis methods. Then, its chaotic dynamic characteristics are further validated by field programmable gate array implementation, which further verifies the consistency of the theoretical analysis and experimental results. Finally, a color image encryption algorithm based on the chaotic sequences generated by the proposed DNMHNN model is designed and implemented, which further validates the practical application feasibility and security of the proposed DNMHNN model and the image encryption algorithm.

关键词： Hopfield neural network Image encryption Chaotic dynamics field programmable gate array

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A Video Streaming Encryption Method and Experimental System Based on Reconfigurable Quaternary Logic Operators

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IEEE ACCESS 2024年 12卷 25034-25051页

作者： Zhou, Xinyu Wang, Hongjian Li, Kuiyan Tang, Lifeng Mo, Ningchun Jin, Yi Donghua Univ Sch Comp Sci & Technol Shanghai 201620 Peoples R China Shanghai Astronaut Elect Co Ltd Shanghai 201821 Peoples R China Shanghai Meiduo Commun Equipment Co Ltd Shanghai 200333 Peoples R China Shanghai Univ Sch Comp Engn & Sci Shanghai 200444 Peoples R China

Multiple-valued logics (MVL) have abundant operation functions which can be used for encryption. A reconfigurable MVL operator can perform all MVL functions with a universal circuit structure at fast operation speed, based on which a one-time-pad cryptosystem is expected to be built. However, we find that when the existing MVL encryption method is applied to video data encryption, the color edges in the plaintext image will remain in the ciphertext image, resulting in partial leakage of information. To solve this problem, we propose byte reorganization and random mask strategies, forming an improved MVL encryption method for video streaming. For verifying the effectiveness of the method, we implement an FPGA-based experimental system to encrypt and decrypt real-time video streaming data. In this system, 16-quit reconfigurable quaternary logic operators are implemented to encrypt, decrypt and derive keys. The process of either encryption or decryption only takes 34 clock cycles. The encryption and decryption modules are capable of processing streaming data at a speed of 6.21 Gbit/s, showing that the system has real-time processing capability. For proving that our method is secure, we compare our improved MVL encryption method with existing image encryption methods in terms of common security evaluation metrics. Experimental results show that our method solves the problem of remained color edge and the ciphertext exhibits good statistical properties.

关键词： Encryption Cryptography Streaming media Real-time systems Symbols Image edge detection field programmable gate arrays Videos Image processing Reconfigurable architectures Video and image encryption multiple-valued logic reconfigurable quaternary logic operator field programmable gate array

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