This letter describes a CAD system for automatic implementation of FIR filters on Xilinx field programmable gate arrays (FPGA). Given the frequency specifications, this software package designs an FIR filter, optimize...
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This letter describes a CAD system for automatic implementation of FIR filters on Xilinx field programmable gate arrays (FPGA). Given the frequency specifications, this software package designs an FIR filter, optimizes the filter coefficients in the power of two coefficient space, and implements it on FPGA chips. The FPGA specific mapping techniques used to increase speed are discussed. The performance of the typical filters that were implemented is presented.
This paper discusses the future of field programmable gate arrays (FPGA) from the viewpoint of Ivo Bolsens, chief technology officer at Xilinx. Bolsens believes that the best design features for dealing with the effec...
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This paper discusses the future of field programmable gate arrays (FPGA) from the viewpoint of Ivo Bolsens, chief technology officer at Xilinx. Bolsens believes that the best design features for dealing with the effects of Moore's Law and submicron devices are all in FPGAs. These devices also have a number of built-in advantages when it comes to programmability. Inherent parallelism keeps clock rate down in the MHz range, and transistor counts can be contained by dynamically reconfiguring parts of a circuit. To address the issue of Moore's Law in FPGA design, Bolsens thinks the answer lies in moving up the abstraction level and exploiting FPGA's inherent reprogrammability to simplify the whole design experience.
An R phi trigger was developed using the eight doublet layers of axial fibers in the new Central Fiber Tracker for the DO Upgrade Detector at Fermilab [1]. This trigger must be formed in less than 500 nsec and distrib...
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An R phi trigger was developed using the eight doublet layers of axial fibers in the new Central Fiber Tracker for the DO Upgrade Detector at Fermilab [1]. This trigger must be formed in less than 500 nsec and distributed to other parts of the detector for a level 1 trigger decision. The high speed is achieved by using massively parallel AND/OR logic realized in state-of-the-art field programmable gate arrays, FPGAs. The programmability of the FPGAs allows corrections to the track roads for the as-built detector and for dynamically changing the transverse momentum threshold. To reduce the number of fake tracks at high luminosity, the narrowest possible roads must be used which pushes the total number of roads into the thousands. Monte Carlo simulations of the track trigger were run to develop the trigger algorithms and a vendor specific commercially available simulator was used to develop and test the FPGA programming.
Reliability and precision are very important in space, medical, and industrial robot control applications. Recently, researchers have tried to increase the reliability and precision of the robot control implementation...
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Reliability and precision are very important in space, medical, and industrial robot control applications. Recently, researchers have tried to increase the reliability and precision of the robot control implementations. High precision calculation of inverse kinematic color based object recognition, and parallel robot control based on field programmable gate arrays (FPGA) are combined in the proposed system. The precision of the inverse kinematic solution is improved using the coordinate rotation digital computer (CORDIC) algorithm based on double precision floating point number format. Red, green, and blue (RGB) color space is converted to hue saturation value (HSV) color space, which is more convenient for recognizing the object in different illuminations. Moreover, to realize a smooth operation of the robot arm, a parallel pulse width modulation (PWM) generator is designed. All applications are simulated, synthesized, and loaded in a single FPGA chip, so that the reliability requirement is met. The proposed method was tested with different objects, and the results prove that the proposed inverse kinematic calculations have high precision and the color based object recognition is quite successful in finding coordinates of the objects.
In order to investigate frequency and -architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable sp...
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In order to investigate frequency and -architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz.
Three-dimensional mixed-mode device simulation is used to investigate the dock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned,vith improved SEU hard...
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Three-dimensional mixed-mode device simulation is used to investigate the dock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned,vith improved SEU hardness, The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LETth. The difference between LETth at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality.
Non-linear steady-state power flow solvers have typically relied on the Newton-Raphson method to efficiently compute solutions on today's computer systems. fieldprogrammablegate array (FPGA) devices, which have ...
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ISBN:
(纸本)9781424404926
Non-linear steady-state power flow solvers have typically relied on the Newton-Raphson method to efficiently compute solutions on today's computer systems. fieldprogrammablegate array (FPGA) devices, which have recently been integrated into high-performance computers by major computer system vendors, offer an opportunity to significantly increase the performance of power flow solvers. However, only some algorithms are suitable for an FPGA implementation. The Gauss-Seidel (GS) method of solving the AC power flow problem is an excellent example of such an opportunity. In this paper we discuss algorithmic design considerations, optimization, implementation, and performance results of the implementation of the Gauss-Seidel method running on a Silicon Graphics Inc. Altix-350 computer equipped with a Xilinx Virtex II 6000 FPGA.
New fast and highly complex 'field programmable gate arrays' allow the design of sophisticated decision logic within the trigger latency time of Particle Detectors. As an example we show the Jet Determination ...
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ISBN:
(纸本)076950843X
New fast and highly complex 'field programmable gate arrays' allow the design of sophisticated decision logic within the trigger latency time of Particle Detectors. As an example we show the Jet Determination of the Hera-H1 detector at DESY (Deutsches Elektronen Synchrotron) Hamburg. It has to calculate all existing localized energy depositions (jets) in the calorimeter and deliver the result, sorted according to energy. The system is implemented by a network of three times 440 high density FPGA's which have to deliver the results in less than 1 mus. The computing power of the system is equivalent to 70 Billion operations per second.
General Purpose Processors (GPPs) and ASICs have traditionally been the common means for building and implementing Artificial Neural Network's (ANNs). However Such computing paradigms suffer from the constant need...
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ISBN:
(纸本)0769524567
General Purpose Processors (GPPs) and ASICs have traditionally been the common means for building and implementing Artificial Neural Network's (ANNs). However Such computing paradigms suffer from the constant need of establishing a trade-off between flexibility and performance Due to the technological advance in the development of progammable logic devices, field programmable gate arrays (FPGAs) have become attractive for realizing ANNs. FPGAs have shown to exhibit excellent flexibility in terms of reprogramming the same hardware and at the same time achieving good performance by enabling parallel computation. In this paper various implementations of ANNs on FPGAs are investigated and compared. The research described in this paper proposes three partially parallel architectures and a fully parallel architecture to realize the Back- Propagation algorithm on an FPGA. The proposed designs are coded in Handel-C and functionally, verified by synthesizing them on a Virtex2000e FPGA chip. The partially parallel architectures and the fully parallel architecture are found to be 2.25 and 4 times faster than the software implementation rcspectively for different benchmarks.
The semiconductor industry has adopted a horizontal business model wherein one company designs the Integrated Circuits (ICs), a second company fabricates them and a third one tests and packages them. Separating design...
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ISBN:
(纸本)9781538622544
The semiconductor industry has adopted a horizontal business model wherein one company designs the Integrated Circuits (ICs), a second company fabricates them and a third one tests and packages them. Separating design from fabrication introduces vulnerabilities in the IC supply chain. An offshore semiconductor foundry can overproduce FPGAs, and a malicious distributor can reinsert old, recycled and counterfeit FPGAs into the supply chain. We present an approach to fingerprint FPGAs by leveraging process variations and spatial correlations. We confirmed FPGA fingerprinting on 56 Xilinx Artix-7 FPGAs.
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