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A New Hyperjerk System With a Half Line Equilibrium: Multistability, Period Doubling Reversals, Antimonotonocity, Electronic Circuit, fpga design, and an Application to Image Encryption

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IEEE ACCESS 2024年 12卷 9177-9194页

作者： Sambas, Aceng Miroslav, Mahdal Vaidyanathan, Sundarapandian Ovilla-Martinez, Brisbane Tlelo-Cuautle, Esteban Abd El-Latif, Ahmed A. Abd-El-Atty, Bassem Benkouide, Khaled Bonny, Talal Univ Sultan Zainal Abidin Fac Informat & Comp Campus Besut Besut Terengganu Malaysia Univ Muhammadiyah Tasikmalaya Dept Mech Engn Tasikmalaya 46196 Indonesia VSB Tech Univ Ostrava Fac Mech Engn Dept Control Syst & Instrumentat Ostrava 70800 Czech Republic Vel Tech Univ Ctr Control Syst Vel NagarAvadi Chennai Tamil Nadu India IPN CINVESTAV Mexico City 07360 Mexico Inst Nacl Astrofis Opt & Elect INAOE Dept Elect Mexico City 72840 Puebla Mexico Prince Sultan Univ Coll Comp & Informat Sci EIAS Data Sci Lab Riyadh 11586 Saudi Arabia Menoufia Univ Fac Sci Dept Math & Comp Sci Shibin Al Kawm 32511 Egypt Luxor Univ Fac Comp & Informat Dept Comp Sci Luxor 85951 Egypt Badji Mokhtar Univ Fac Technol Dept Elect Engn Annaba 23000 Algeria Univ Sharjah Dept Comp Engn Sharjah U Arab Emirates

A hyperjerk system pertains to a dynamical system regulated by an ordinary differential equation of nth order, where n >= 4. The main contribution of this work is the finding of a new autonomous hyperjerk system with a half line equilibrium. The mathematical framework of the proposed hyperjerk system contains eight terms with an absolute function nonlinearity. The essential dynamic characteristics of the model are explored, encompassing analysis of equilibrium points and their stability, depiction of the phase trajectories, illustration of bifurcation patterns, and visualization of Lyapunov exponent graphs. Our finding shows that the new 4D hyperjerk system exhibits special behavior like multistability, period doubling reversals and antimonotonocity. The proposed hyperjerk system has been implemented with an electronic circuit using MultiSim 14.0. Moreover, the fpga implementation of the proposed hyperjerk system is performed by applying two numerical methods: Forward Euler and Trapezoidal. Experimental attractors are given from an oscilloscope by using the Zybo Z7-20 fpga development board, which are in good agreement with the MATLAB and MultiSim 14.0 simulations. Finally, based on the chaotic dynamical behavior of the proposed chaotic hyperjerk system, a new image encryption approach is proposed. The experimental outcomes of the presented encryption algorithm prove its efficiency and security.

关键词： Encryption Behavioral sciences Field programmable gate arrays Chaotic communication Heuristic algorithms Bifurcation Complexity theory Chaos chaotic systems HyperJerk systems multistability electronic circuit fpga design encryption

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fpga design and circuit implementation of a new four-dimensional multistable hyperchaotic system with coexisting attractors

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INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY 2020年第3期64卷 223-234页

作者： Vaidyanathan, Sundarapandian Tlelo-Cuautle, Esteban Sambas, Aceng Dolvis, Leutcho Gervais Guillen-Fernandez, Omar Vel Tech Univ Ctr Res & Dev Chennai 600062 Tamil Nadu India Natl Inst Astrophys Opt & Elect INAOE Dept Elect Puebla 72840 Mexico Univ Muhammadiyah Taskimalaya Dept Mech Engn Tasikmalaya 46196 Jawa Barat Indonesia Univ Dschang Dept Phys Lab Condensed Matter Elect & Signal Proc Dschang West Cameroon

This research work focuses upon the fpga design and electronic circuit implementation of a new multistable four-dimensional hyperchaotic system. This work starts with the dynamics and phase plots of a new four-dimensional hyperchaos system. A detailed bifurcation analysis is carried out for the new hyperchaos system, and special properties such as multistability with coexisting attractors are reported for the new system. An electronic circuit model using MultiSim of the new hyperchaos system is designed. Finally, an fpga-based design of the new hyperchaos system is performed by applying two numerical methods. Circuit simulation and fpga design of the new hyperchaos system are very useful for practical applications of the new hyperchaos system.

关键词： hyperchaos hyperchaotic system multistability circuit simulation fpga design

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Automated Integration of Dynamic Power Management into fpga-Based design 22

Automated Integration of Dynamic Power Management into FPGA-...

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22nd IEEE International Symposium on design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Skuta, Michal Macko, Dominik Slovak Univ Technol Bratislava Fac Informat & Informat Technol Bratislava Slovakia

ISBN: (纸本)9781728100739

A low power or energy efficient hardware operation is nowadays gaining attention. It is especially true for battery-operated or energy-harvesting devices, such as most of the Internet of Things end nodes. For specific applications with rather limited market, the fpgas are very good alternative. However, evolution of these devices is focused on high-level programming, giving application designers space to focus on application function rather than to be concerned about its low-level implementation on fpga device - it is handled by automation tools. Thus, new fpga-application designers are nowadays not very familiar with hardware aspects and it is difficult for them to apply power-reduction techniques in order to create an energy-efficient system. This paper is focused on automation of power-management integration into the fpga-application design based on abstract specification, which is easy-to-use even for unfamiliar designers. It simplifies and speedsup the low-power and energy-efficient fpga-application design process. Moreover, the automation prevents many human-errors and thus it also alleviates the verification process. Experimental results indicate that the proposed power-management scheme is working correctly and it can be automatically generated.

关键词： CAD design automation fpga design low power power management

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EraΣer: A Compact fpga-TDC design 5

EraΣer: A Compact FPGA-TDC Design

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5th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)

作者： Knittel, Guenter Traxler, Michael GSI Helmholtzzentrum Schwer Ionenforsch Expt Elect Darmstadt Germany

ISBN: (纸本)9781728123226

We present a compact TDC-design for a low-cost fpga platform. It incorporates a novel encoder design that permits the combined use of the Wave-Union principle and population count encoding for increased precision and efficiency. Furthermore, a highly optimized implementation allows a high sampling clock frequency to be used, which shortens the length of the tapped delay line, which in turn reduces the hardware costs of all downstream units. As a result, 64+1 channels can be integrated on a low-cost Lattice ECP3 fpga. The design offers Time-over-Threshold (ToT) measurements in a single channel using a stretcher. Each TDC-channel is complemented by a high-performance pulse (hit) counter. For trigger-less acquisition systems, 40-bit timestamps are provided. A complete TDC system has been implemented and integrated in our standard data acquisition environment. Key specifications are a channel-to-chanel precision in the 10ps range, a ToT precision in the 30ps range for 10ns pulses, and a minimum ToT measurement time of about 17ns. The hit counters can count pulses as narrow as 833ps at a maximum rate of 600M pulses per second. In this paper we will mostly discuss the principles, methods and tricks for this highly optimized fpga design.

关键词： TDC Wave Union Population Count Encoder fpga design

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Low Power fpga-SoC design Techniques for CNN-based Object Detection Accelerator 10

Low Power FPGA-SoC Design Techniques for CNN-based Object De...

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IEEE 10th Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON)

作者： Kim, Heekyung Choi, Ken IIT Dept Elect & Comp Engn Chicago IL 60616 USA

ISBN: (纸本)9781728138855

This paper shows the possibility of the existing low power register transfer level (RTL) techniques can be effective as a low power design scheme for CNN-based object recognition system acceleration in contrast to conventional techniques. Most power efficient design techniques regarding CNN acceleration are focused on the High-level Synthesis (HLS) aspect, such as memory bandwidth optimization, network architecture reconfiguration, data reuse, and batch normalization. However, these attempts have reached the limits of the effectiveness of itself. Using the postsynthesis RTL code generated by field-programmable gate arrays (fpga) manufacturers, the proposed RTL low power design technique was applied to the original FIFO part for reducing the power consumption during data transformation. We compared the HLS optimized result with the RTL optimized result in the aspect of power consumption. We configured the testbench for the modified FIFO module and analyzed the estimated power dissipation result. These power effectiveness factors, such as a look-up table (LUT), a lookup table RAM (LUTRAM), can reduce the power dissipation by 54%, 49% respectively, even though increased block RAM (BRAM) leads to the elevated power dissipation by 154%. Thus, the total power consumption was able to be decreased by 10%. This paper discusses two factors of fpga with system-on- chip (fpga-SoC) design for CNN-based hardware implementation in power consumption aspect, such as RTL architecture, memory design architecture, and the model architecture-based hardware implementation methods. The virtual additional memory can support the high throughput at full speed. Our simulated low power schemes applied to Processing System (PS) and Programmable Logic (PL) architecture effectively reduced the power consumption by 25.9% in the FIFO data transformation. We established that the increased LUT blocks affect the power-efficient rate and reduce the power consumption of the PL design up to 49%.

关键词： Low Power CNN Power Efficient Power Efficient FIFO Low Power Techniques CNN-based Accelerator fpga design fpga SoC design Xilinx fpga-SoC

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Investigation of Reconfigurable fpga design for Processing Big Data Streams 2

Investigation of Reconfigurable FPGA Design for Processing B...

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2nd IEEE International Conference on High Performance and Smart Computing (IEEE HPSC)

作者： Algemili, Usamah George Washington Univ Dept Comp Sci Washington DC 20052 USA

ISBN: (纸本)9781509024032

Big Data situation has placed a tremendous pressure on the existing computational models. The challenges of Big Data call for a new approach to solve both software and hardware problems. Streaming applications is a form of on-demand software distribution. In streaming scenarios, only essential portions of an application's code need to be installed on the system, while the receiver performs the main operations. The necessary code and files are delivered over the network as, and when, they are required. The hardware architecture plays an important role in improving the efficiency of a streaming system. The variance of hardware performance on different HW architectures is quite interesting. Previous work confirms that the CPUs, GPUs, and fpgas are performing differently on specific applications. The previous efforts of hardware benchmarking show that GPUs outperformed the other platforms in terms of execution time. CPUs outperformed in overall execution combined with transfer time. fpgas outperformed for fixed algorithms using streaming [1]. Hence, this paper evaluates the performance of streaming applications on a pipelined fpga design. In the context of real-time processing, it elects one of the Big Data streaming problems that gets a candidate for majority element on-the-fly;that is Moore's Voting Algorithm. The performance analysis of Moore's algorithm on fpga highlights a noticeable improvement by using a pipelining architecture.

关键词： Big Data Processing Streaming Processing Reconfigurable Computing fpga design Pipeline design On-the-fly processing

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Integrating reliability analysis into MBSE for fpga-based safety critical I&C system design in nuclear power plants

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KERNTECHNIK 2024年第4期89卷 529-546页

作者： Wang, Fanyu Zhao, Yang He, Jinyu Chen, Qi Lei, Minjie Wang, Heng Nucl Power Inst China Sci & Technol Reactor Syst Design Technol Lab Chengdu 610213 Peoples R China

With the widespread application of Field Programmable Gate Array (fpga) technology in the instrumentation and control (I&C) systems of nuclear power plants (NPPs), its design reliability has become the key to ensuring the subsequent safe operation of NPPs. However, the traditional document-based design method is no longer sufficient to meet the current design needs of complex systems, and there is a lack of research related to the reliability and security analysis of fpga-based systems. Therefore, the overall goal of this study is to integrate reliability analysis into the model-based systems engineering (MBSE)-based design of fpga-based I&C systems. Based on the typical application characteristics of the fpga, a digital design framework for fpga-based systems is proposed to realize a traceable design process from requirements to implementation. Subsequently, a model-based forward comprehensive reliability analysis method is proposed, which uses a SysML-based mapping mechanism to integrate Failure Mode and Effects Analysis (FMEA) and Fault Tree Analysis (FTA) methods into the design process, so as to comprehensively identify and analyze failure modes from systems to components and optimize and improve system design. Finally, the proposed method is applied to the analog output design of fpga-based systems. The proposed method can provide guidance for improving the reliability of fpga-based DI&C systems and provide theoretical basis for the further engineering application.

关键词： I&C system fpga design model-based systems engineering reliability analysis

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Mathematical modelling, bifurcation analysis, circuit design and fpga implementation of a 5D hyperchaotic weather fluctuation model with a line of equilibrium points

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INTERNATIONAL JOURNAL OF MODELLING IDENTIFICATION AND CONTROL 2023年第4期43卷 267-283页

作者： Vaidyanathan, Sundarapandian Moroz, Irene M. Tlelo-Cuautle, Esteban Sambas, Aceng Bermudez-Marquez, Ciro Fabian Safaan, Samy Abdelwahab Vel Tech Univ Ctr Control Syst 400 Feet Outer Ring Rd Chennai 600062 Tamil Nadu India Univ Oxford Math Inst Oxford OX2 6GG England Natl Inst Astrophys Opt & Elect INAOE Dept Elect Tonantzintla 72840 Puebla Mexico Univ Muhammadiyah Tasikmalaya Dept Mech Engn Tasikmalaya 46196 W Java Indonesia Qassim Univ Community Coll Buraydah Dept Nat & Appl Sci Buraydah 52571 Saudi Arabia Nile Higher Inst Commercial Sci & Comp Technol Mansoura 35511 Egypt

High-dimensional hyperchaotic systems are known to have several applications in engineering owing to their high complexity. This work reports the finding of a new 5D hyperchaotic weather fluctuation model, which is constructed by means of introducing two state feedback controllers in the 3D Vallis weather fluctuation model (1986). The new hyperchaotic system has a line of equilibrium points. Hence, it has hidden attractors. We carry out a detailed bifurcation analysis with standard tools such as bifurcation diagrams and Lyapunov exponents to study the intrinsic properties of the 5D weather fluctuation model with respect to changes in the system constants. Next, we design an electronic circuit of the 5D weather fluctuation model using MultiSim. The new 5D hyperchaotic weather fluctuation model is implemented herein by applying two one-step numerical methods, viz., forward Euler and trapezoidal rule. Experimental attractors for the 5D hyperchaotic model are shown from an oscilloscope.

关键词： modelling bifurcation chaos hyperchaos hyperchaotic systems equilibrium points line equilibrium stability circuit design fpga design

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Electronic circuit design and fpga-based hardware implementation of a new multistable 4-D hyperchaotic four-leaf system

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INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY 2023年第1期72卷 13-28页

作者： Vaidyanathan, Sundarapandian Sambas, Aceng Clemente-Lopez, Daniel Munoz-Pacheco, Jesus M. Kammogne, Alain Soup Tewa Mawamba, Vannick Fopa Martin, Siewe Siewe Safaan, Samy A. Vel Tech Univ Ctr Control Syst Chennai Tamil Nadu India Univ Sultan Zainal Abidin Fac Informat & Comp Gong Badak 21300 Terengganu Malaysia Univ Muhammadiyah Taskimalaya Dept Mech Engn Tasikmalaya Jawa Barat Indonesia Inst Nacl Astrofis Opt & Elect INAOE Dept Elect Digital Syst Grp Puebla Mexico Benemerita Univ Autonoma Puebla Fac Elect Sci Chaot & Fract Order Syst & Nonlinear Circuits Grp Puebla Mexico Univ Dschang Fac Sci Dept Phys Lab Condensed Matter Elect & Signal Proc Dschang Cameroon Univ Yaounde I Fac Sci Dept Phys Lab Mech Mat & Stuct Yaounde Cameroon Qassim Univ Commun Coll Buraydah Dept Nat & Appl Sci Buraydah Qassim Saudi Arabia Nile Higher Inst Commercial Sci & Comp Technol Mansoura Dakahlia Egypt

We generate a new hyperchaotic four-leaf system by inserting a state feedback control to the 3-D Vaidyanathan-Rhif chaotic four-leaf system (Vaidyanathan and Rhif, 2017). The new hyperchaotic system developed in this work has three quadratic non-linearities and two positive Lyapunov exponents. Bifurcation analysis points coexisting bifurcations and multiple attractors for the new 4-D hyperchaotic four-leaf system. Next, we construct an electronic circuit model using MultiSim (Version 13.0) for implementing the new 4-D hyperchaotic four-leaf system. Embedded and non-embedded implementations of chaotic and hyperchaotic systems are vital to increase their usability in many engineering applications since those fpga designs can be linked to the digital world surrounding us in a direct manner. An ARM-fpga-based hardware implementation of the 4-D hyperchaotic four-leaf system is given in detail, showing a good agreement between numerical and experimental results.

关键词： hyperchaos chaos electronics circuit design stability fpga design hyperchaotic systems phase portraits bifurcation system analysis

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fpga design and Implementation of Gaussian filter 9

FPGA Design and Implementation of Gaussian filter

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9th International Symposium on Multispectral Image Processing and Pattern Recognition (MIPPR) - Multispectral Image Acquisition, Processing, and Analysis

作者： Yang, Zhihui Zhou, Gang Huazhong Univ Sci & Technol Natl Key Lab Multispectral Informat Proc Technol Wuhan 430070 Peoples R China

ISBN: (纸本)9781510600522

In this paper, we choose four different variances of 1,3,6 and 12 to conduct fpga design with three kinds of Gaussian filtering algorithm, they are implementing Gaussian filter with a Gaussian filter template, Gaussian filter approximation with mean filtering and Gaussian filter approximation with IIR filtering. By waveform simulation and synthesis, we get the processing results on the experimental image and the consumption of fpga resources of the three methods. We set the result of Gaussian filter used in matlab as standard to get the result error. By comparing the fpga resources and the error of fpga implementation methods, we get the best fpga design to achieve a Gaussian filter. Conclusions can be drawn based on the results we have already got. When the variance is small, the fpga resources is enough for the algorithm to implement Gaussian filter with a Gaussian filter template which is the best choice. But when the variance is so large that there is no more fpga resources, we can chose the mean to approximate Gaussian filter with IIR filtering

关键词： fpga design fpga implementation Gaussian filter different variances IIR filtering mean filtering error of fpga implementation methods fpga resources

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