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A hybrid GPU-fpga based design methodology for enhancing machine learning applications performance

JOURNAL OF AMBIENT INTELLIGENCE AND HUMANIZED computing 2020年第6期11卷 2309-2323页

作者： Liu, Xu Ounifi, Hibat-Allah Gherbi, Abdelouahed Li, Wubin Cheriet, Mohamed Univ Quebec ETS Synchromedia Lab Montreal PQ Canada Univ Quebec ETS Montreal PQ Canada Ericsson Ericsson Res Montreal PQ Canada

The high-density computing requirements of machine learning (ML) is a challenging performance bottleneck. Limited by the sequential instruction execution system, traditional general purpose processors are not suitable for efficient ML. In this work, we present an ML system design methodology based on GPU and fpga to tackle this problem. The core idea of our proposal is when designing an ML platform, we leverage the graphics processing unit (GPU)'s high-density computing to perform model training and exploit field programmable gate array (fpga)'s low-latency to perform model inferencing. In between, we define a model converter, which enable transforming the model used by the training module to one that is used by inferencing module. We evaluated our approach through two use cases. The first is a handwritten digit recognition with convolutional neural network while the second use case is for predicting data center's power usage effectiveness with deep neural network regression algorithm. The experimental results indicate that our solution can take advantages of GPU and fpga's parallel computing capacity to improve the efficiency of training and inferencing significantly. Meanwhile, the solution preserves the accuracy and the mean square error while converting the models between the different frameworks.

关键词： Machine learning High performance computing Heterogeneous computing Hybrid platform GPU computing fpga computing CNN DNN Model converting PUE

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Prototype and Evaluation of the CoRAM Memory Architecture for fpga-Based computing 12

Prototype and Evaluation of the CoRAM Memory Architecture fo...

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20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (fpga)

作者： Chung, Eric S. Papamichael, Michael K. Weisz, Gabriel Hoe, James C. Mai, Ken Carnegie Mellon Univ Comp Architecture Lab CALCM Pittsburgh PA 15213 USA

ISBN: (纸本)9781450311557

The CoRAM memory architecture for fpga-based computing augments traditional reconfigurable fabric with a natural and effective way for applications to interact with off-chip memory and I/O. The two central tenets of the CoRAM memory architecture are (1) the deliberate separation of concerns between computation versus data marshalling and (2) the use of a multithreaded software abstraction to replace FSM-based memory control logic. To evaluate the viability of the CoRAM memory architecture, we developed a full RTL implementation of a CoRAM microarchitecture instance that can be synthesized for standard cells or emulated on fpgas. The results of our evaluation show that a soft emulation of the CoRAM memory architecture on current fpgas can be impractical for memory-intensive, large-scale applications due to the high performance and area penalties incurred by the soft mechanisms. The results further show that in an envisioned fpga built with CoRAM in mind, the introduction of hard macro blocks for data distribution can mitigate these inefficiencies-allowing applications to take advantage of the CoRAM memory architecture for ease of programmability and portability while still enjoying performance and efficiency comparable to RTL-level application development on conventional fpgas.

关键词： fpga computing memory architecture

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Janus II: A new generation application-driven computer for spin-system simulations

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COMPUTER PHYSICS COMMUNICATIONS 2014年第2期185卷 550-559页

作者： Baity-Jesi, M. Banos, R. A. Cruz, A. Fernandez, L. A. Gil-Narvion, J. M. Gordillo-Guerrero, A. Iniguez, D. Maiorano, A. Mantovani, F. Marinari, E. Martin-Mayor, V. Monforte-Garcia, J. Munoz Sudupe, A. Navarro, D. Parisi, G. Perez-Gaviro, S. Pivanti, M. Ricci-Tersenghi, F. Ruiz-Lorenzo, J. J. Schifano, S. F. Seoane, B. Tarancon, A. Tripiccione, R. Yllanes, D. Univ Complutense Dept Fis Teor Madrid 28040 Spain Inst Biocomputac & Fis Sist Complejos BIFI Zaragoza 50009 Spain Univ Roma Sapienza Dipartimento Fis I-00185 Rome Italy Univ Zaragoza Dept Fis Teor Zaragoza 50009 Spain Univ Ferrara Dipartimento Fis & Sci Terra I-44100 Ferrara Italy INFN I-44100 Ferrara Italy Univ Roma Sapienza Dipartimento Fis IPCF CNR UOS Roma Kerberos I-00185 Rome Italy INFN I-00185 Rome Italy Univ Extremadura Dept Fis Badajoz 06071 Spain Univ Ferrara Dipartimento Matemat & Informat I-44100 Ferrara Italy Fdn ARAID Diputac Gen Aragon Zaragoza Spain

This paper describes the architecture, the development and the implementation of Janus II, a new generation application-driven number cruncher optimized for Monte Carlo simulations of spin systems (mainly spin glasses). This domain of computational physics is a recognized grand challenge of high-performance computing: the resources necessary to study in detail theoretical models that can make contact with experimental data are by far beyond those available using commodity computer systems. On the other hand, several specific features of the associated algorithms suggest that unconventional computer architectures - that can be implemented with available electronics technologies - may lead to order of magnitude increases in performance, reducing to acceptable values on human scales the time needed to carry out simulation campaigns that would take centuries on commercially available machines. Janus II is one such machine, recently developed and commissioned, that builds upon and improves on the successful JANUS machine, which has been used for physics since 2008 and is still in operation today. This paper describes in detail the motivations behind the project, the computational requirements, the architecture and the implementation of this new machine and compares its expected performances with those of currently available commercial systems. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Spin glass Monte Carlo Application-driven computers fpga computing

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Big Data Processing with fpga Supercomputers: Opportunities and Challenges

Big Data Processing with FPGA Supercomputers: Opportunities ...

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IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Dollas, Apostolos Tech Univ Crete Sch ECE Khania Greece

ISBN: (纸本)9781479937653

The use of Field Programmable Gate Arrays (fpgas) as high-end compute engines has proven to be successful in several classes of problems and their application as "big data" supercomputers has already started to be investigated. This paper presents the main approaches in the sate-of-the-art with research highlights as well as skeptics' considerations. It will then proceed to analyze the main memory and network characteristics of present-day systems in the context of "big data" processing. The analysis will reveal that there exist obstacles to overcome in virtually all present-day fpga supercomputers. This work will then propose possible solutions from on-going research in the AFORMI project. These are the decoupling of the memory data accesses from execution - leading to transaction-oriented compute paradigms, the use of fpgas as "snooping" processors, and the need for low-overhead fpga interconnection protocols.

关键词： component fpgas big data fpga computing reconfigurable computing

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Cross-platform fpga accelerator development using CoRAM and CONNECT 13

Cross-platform FPGA accelerator development using CoRAM and ...

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Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

作者： Eric S. Chung Michael K. Papamichael Gabriel Weisz James C. Hoe Microsoft Research Mountain View CA USA Carnegie Mellon Pittsburgh PA USA

ISBN: (纸本)9781450318877

The CoRAM memory architecture is an easy-to-use and portable abstraction for fpga accelerator development [1, 2]. Using the CoRAM framework, fpga developers can write their applications once and re-target them automatically to different fpga platforms and devices (e.g., Xilinx ML605, Altera DE4, ZYNQ-702, etc). In this tutorial, participants will learn the key concepts of the CoRAM Virtual Architecture and the underlying CONNECT Network-on-Chip generation framework [3]. The tutorial is organized into three parts. The first part will provide an overview of the CoRAM Virtual Architecture and include a hands-on section where participants will work on a small example to get first-hand experience with the CoRAM development flow. The second part of the tutorial will provide a beneath-the-hood look at CoRAM and cover more advanced topics. These topics include memory loading, user I/O, debugging, as well as a segment on the CONNECT NoC generation framework which serves as the on-chip interconnect for CoRAM. The final part of the tutorial will be devoted to more advanced exercises and demos, as well as a Q&A session for CoRAM and CONNECT. The tutorial assumes a basic understanding of RTL design and C programming. To join in on the hands-on exercise, the attendees need laptops with 15GB of free space and VirtualBox installed. Please visit http://***/~coram for information about CoRAM and updates on this tutorial.

关键词： network-on-chip fpga computing memory architecture

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SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator

SMPP: Generic SAT Solver over Reconfigurable Hardware Accele...

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26th IEEE International Parallel and Distributed Processing Symposium (IPDPS) / Workshop on High Performance Data Intensive computing

作者： Yuan, Zhongda Ma, Yuchun Bian, Jinian Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9780769546766

To further exploit the potential of reconfigurable computing, fine-grain, super massive parallel processing SAT solver over reconfigurable hardware accelerator is proposed in this paper as SMPP. By analyzing the traditional SAT solver, we proposed a novel way to partition the original problem into software part and hardware part. Software part uses semi-confliction guided backtrack to extract equivalent fixed scale sub-problem sequence. Partition scheme of SMPP exploited the stage effect of inference engine in modern software SAT solver. Hardware part uses tiny processing cells to handle small scale SAT problem in linear time proportional to the number of clause. Theoretical analyze and experiment results show that the speed up factor is significant.

关键词： reconfigurable computing SAT Solver fpga computing hardware accelerator

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fpga curved track fitters and a multiplierless fitter scheme

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2008年第3期55卷 1791-1797页

作者： Wu, Jinyuan Wang, M. Gottschalk, E. Shi, Z. Fermilab Natl Accelerator Lab Batavia IL 60510 USA

The standard least-squares curved track fitting process is tailored for fpga implementation so that only integer multiplications and additions are needed. To further eliminate multiplication, coefficients in the fitting matrices are carefully chosen so that only shift and accumulation operations are used in the process. Comparison in an example application shows that the fitting errors of the multiplierless implementation are less than 4% bigger than the fitting errors of the exact least-squares algorithm. The implementation is suitable for low-cost, low-power applications in high energy physics detector trigger systems.

关键词： fpga computing fpga firmware track fitting trigger

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fpga curved track fitters and a multiplierless fitter scheme

FPGA curved track fitters and a multiplierless fitter scheme

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15th International Workshop on Room-Temperature Semiconductor X- and Gamma-Ray Detectors/ 2006 IEEE Nuclear Science Symposium

作者： Wu, Jinyuan Wang, M. Gottschalk, E. Shi, Z. Fermilab Natl Accelerator Lab Batavia IL 60510 USA

关键词： fpga computing fpga firmware track fitting trigger

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Large-scale logic-array computation

Large-scale logic-array computation

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Conference on High-Speed computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic

作者： Margolus, N BOSTON UNIV CTR COMPUTAT SCIBOSTONMA 02215

ISBN: (纸本)0819423165

For a number of years, we have studied the large-scale fine-grained limit of cellular-logic-array calculations and computers-with particular emphasis on applications to physical simulation. Perhaps the most relevant lessons of this work for the fpga community have to do with the applicability of virtual-processor techniques to these logic-array computations-and by extension to the design of fpga's themselves. These techniques allow us to tradeoff speed against size, to balance resources devoted to data storage with those devoted to processing, and to time-share communication resources as we share processors. An application area of particular interest to the fpga community is in logic emulation, where a virtual processing approach lets us maximize useful processor cycles by having processing hardware follow computational wavefronts through arrays of virtual logic ("temporal pipelining"). This technique is of direct relevance to fpga design. Our virtual processor approach is embodied in our indefinitely scalable cAM-8 cellular automata (CA) machine. Personal-computer-scale prototypes, designed and built at MIT using 1988 technology, are still about as fast as any conventional computer for most large-scale physical CA applications. Using today's high-bandwidth DRAM'S, machine's with the same number of memory chips could be built that run 100 times faster. Rather than build a new dedicated CA machine processor, it is attractive to instead add appropriate DRAM I/O and data-buffering circuitry to an fpga design, to create a general-purpose class of fpga's optimized for large-scale virtualprocessor applications.

关键词： fpga computing fpga architectures virtual processors cellular automata simulation

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