We review and simplify several classical and quantum maps introduced in recent years that have been used in cryptography. For each of these maps, a bitstream is generated and subjected to the NIST test. Leveraging the...
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We review and simplify several classical and quantum maps introduced in recent years that have been used in cryptography. For each of these maps, a bitstream is generated and subjected to the NIST test. Leveraging the advantages of fpga in the loop, these maps are designed in MATLAB Simulink, converted to HDL using HDL Coder, and implemented on fpga. Vivado software is used for more precise synthesis of the implementation of these maps. The results of a detailed analysis of classical and new quantum maps are compared with each other, as well as with other implementations of chaotic maps in the literature. Implementations related to five classical maps and two quantum maps, with maximum frequencies 125 MHz, and maximum throughputs of 4 Gbps, are confirmed. The suitability of these maps for implementation, leveraging their greater dynamic complexity and larger key space, is evident.
Video and Image Processing solution requiring high throughput rate are often implemented in a dedicated hardware such as fpga. The design process traditionally uses Verilog and VHDL for synthesizing and validating the...
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ISBN:
(纸本)9781479986125
Video and Image Processing solution requiring high throughput rate are often implemented in a dedicated hardware such as fpga. The design process traditionally uses Verilog and VHDL for synthesizing and validating the hardware. These design process are technically complex and time consuming. In this paper, we present an alternative approach using a model based design framework based on HDL Coder, Vision HDL Toolbox and Simulink to accelerate the design of video and image solution. Several important issues in this framework are discussed namely, Pixel Streaming Design, Co-simulation and fpga in the loop (FIL). Based on this framework, a video of human walking are processed to extract out two features which are the human height and edge. The design is implemented in an Altera DE2-115 fpga board. The goal of this paper is to tackle the technical complexity and reduce development time of traditional fpga design.
The purpose of this paper is to determine the suitability of low-cost and low-power fpga boards for acceleration, focused especially on cells classification in microscopy images. Our approach is based on simulation by...
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ISBN:
(纸本)9781510838284
The purpose of this paper is to determine the suitability of low-cost and low-power fpga boards for acceleration, focused especially on cells classification in microscopy images. Our approach is based on simulation by means of using Matlab and Simulink. An implementation of the DCT is presented for the extraction of characteristics along with a classification Neural Network. Results show the execution time of the algorithms, their efficiency in terms of accuracy and the limitations of the hardware. The presented system is able to process 640×480 images in 0.53 seconds on average, with a total execution time of 5.04 seconds due to the transfer overhead.
In order to meet a number of industries hardware that require high reliability and large amount of code,this paper gives a model-based design(MBD)workflow compliance with DO-254 standard for hardware development *** t...
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In order to meet a number of industries hardware that require high reliability and large amount of code,this paper gives a model-based design(MBD)workflow compliance with DO-254 standard for hardware development *** the Digital down conversion(DDC)for example;this paper has described how to use the tool chain of Simulink,HDL Coder and Modelsim to complete the entire development *** this way,we can build a DDC model starting from requirements analysis to functional verification and system testing of the model,fixed-point optimization,code generation,and then validation the DDC system on XUPV5 board in visual development *** entire process which starts from design concept to hardware implementation always focuses on the DDC model for continuous testing and *** this way,we can verify and validate the correctness of the design of DDC in three different levels,so that design flaws could be exhumed in the early stages of the *** proposed solution is not only overcoming the flaws of low efficiency and difficulty of meeting the requirements in traditional methods of development,but also to avoid the potential risk in technology and market.
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