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Model predictive control for sodium fast reactors based on Laguerre functions and fpga-in-the-loop environment

NUCLEAR ENGINEERING AND DESIGN 2022年 400卷

作者： Pereira, Luis Felipe da S. C. Batista, Edson Antonio Pinto, Joao Onofre Pereira Upadhyaya, Belle R. Hines, J. Wesley Coble, Jamie B. Univ Fed Mato Grosso do Sul Fac Engn Architecture & Urban Planning & Geog BR-79070900 Campo Grande Brazil Oak Ridge Natl Lab Oak Ridge TN USA Univ Tennessee Knoxville TN USA

This paper proposes a multiple-input multiple-output (MIMO) model predictive control (MPC) design with constraints and Laguerre functions using the simplified model of the primary system (reactor core and intermediate heat exchanger (IHX)) of a prototypical sodium fast reactor (SFR). The control aims at tracking the reactor power, sodium tank temperature and the primary inlet plenum temperature when the reactor operates at 100% capacity by controlling the reactivity and the secondary sodium flow rate. For comparison criteria, this paper simulates the insertion of disturbances related to the reactivity and the sodium inlet temperature. The analysis includes the simulation of the insertion of disturbances in the reactivity and the sodium inlet temperature. The controller design was developed in MATLAB and Simulink, and was tested under a variety of reactivity disturbances (-1 and -5 cents) and a sodium inlet temperature disturbance of +10 degrees F. In each case studied, the MPC tracked the outputs effectively. The proposed MPC-SFR obtained a faster and more robust disturbance rejection regarding insertion of reactivity and sodium inlet temperature when compared with SFR controlled by digital PI controllers (PI-SFR). Finally, the controller was embedded in a Field Programmable Gate Array (fpga) device in order to demonstrate the fpga-in-the-loop (FIL) feature and to compare it with the results using MATLAB-Simulink.

关键词： Model predictive control Laguerre orthonormal functions Quadratic programming Sodium fast reactor fpga-in-the-loop

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Improving Efficiency of fpga-in-the-loop Verification Environment 13

Improving Efficiency of FPGA-in-the-Loop Verification Enviro...

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13th IFAC and IEEE Conference on Programmable Devices and Embedded Systems

作者： Zadek, Pawel Koczor, Arkadiusz Golek, Michal Matoga, Lukasz Penkala, Piotr Evatronix SA Bielsko Biala Poland

The paper presents techniques being developed in order to improve verification efficiency in the fpga-in-the-loop environment. The verification speed-up in relation to typical software simulation within MATLAB (R) suite offered to the presented verification environment is in the range of 100s. The proposed verification environment enables engineers to verify their designs by co-simulation of high-level models with RTL logic. It allows for checking if the prepared VHDL or Verilog code matches the more abstract reference model. The introduced verification environment uses MATLAB (R) and Simulink (R) models, being the de facto modelling standard in the industry. The paper presents a solution which improves signal visibility of a design-under-test and accelerates simulation performance by moving DUT into an fpga. The implemented original fpga based emulation platform offers an efficient interface channel to a host workstation and a GUI software with an embedded viewer for dynamic signal selection and observation. It may be applied to a broad range of simulation subjects. (C) 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： design verification emulation platform debugging fpga-in-the-loop co-simulation

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Improving Efficiency of fpga-in-the-loop Verification Environment

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IFAC-PapersOnLine 2015年第4期48卷 180-185页

作者： Pawel Ządek Arkadiusz Koczor Michal Gołek Łukasz Matoga Piotr Penkala Evatronix S.A. Bielsko-Biala Poland

The paper presents techniques being developed in order to improve verification efficiency in the fpga-in-the-loop environment. The verification speed-up in relation to typical software simulation within MATLAB® suite offered to the presented verification environment is in the range of 100s. The proposed verification environment enables engineers to verify their designs by co-simulation of high- level models with RTL logic. It allows for checking if the prepared VHDL or Verilog code matches the more abstract reference model. The introduced verification environment uses MATLAB® and Simulink® models, being the de facto modelling standard in the industry. The paper presents a solution which improves signal visibility of a design-under-test and accelerates simulation performance by moving DUT into an fpga. The implemented original fpga-based emulation platform offers an efficient interface channel to a host workstation and a GUI software with an embedded viewer for dynamic signal selection and observation. It may be applied to a broad range of simulation subjects.

关键词： design verification emulation platform debugging fpga-in-the-loop co-simulation

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fpga-in-the-loop Co-simulation of Reentrant Arrhythmia Mechanism in One Dimensional (1D) Ring-Shaped based on FitzHugh-Nagumo Model 4

FPGA-in-the-Loop Co-simulation of Reentrant Arrhythmia Mecha...

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4th IEEE International Conference on Control System Computing and Engineering (ICCSCE 2014)

作者： Adon, Nur Atiqah Mahmud, Farhanahani Jabbar, Mohamad Hairol Othman, Norliza Univ Tun Hussein Onn Malaysia UTHM Cardiol & Physiome Anal Res Lab Fac Elect & Elect Engn Microelect & Nanotechnol Shamsudin Res Ctr MiNT S Batu Pahat Johor Malaysia Univ Tun Hussein Onn Malaysia UTHM Manycore Syst Chip MCSoC Res Lab Fac Elect & Elect Engn Microelect & Nanotechnol Shamsudin Res Ctr MiNT S Batu Pahat Johor Malaysia

ISBN: (纸本)9781479956869

This paper presents the simulation of reentrant excitation-conduction of cardiac cells realized by coupling 80 active circuits in one dimensional (1D) ring-shaped based on FitzHugh-Nagumo (FHN) model. 1D ring-shaped cable model is designed using Simulink in order to simulate an action potential signal and its conduction for a hardware design by using HDL Coder to automate the model for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) code generation. Then, the VHDL design is functionally verified on a Field Programmable Gate Array (fpga) Xilinx Virtex-6 board using HDL Verifier proving the model through fpga-in-the-loop (FIL) co-simulation approach. It can then be downloaded into a target fpga device for real-time simulations. This novel approach of prototyping cardiac reentrant excitation-conduction provides a fast and effective fpga-based hardware implementation flow towards a stand-alone implementation to perform complex real-time simulations compared with manual HDL designs.

关键词： Reentrant FitzHugh-Nagumo Model HDL Coder fpga-in-the-loop real-time simulations

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A redundant secondary control scheme to resist FDI attacks in AC microgrids

SCIENCE AND TECHNOLOGY FOR ENERGY TRANSITION

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SCIENCE AND TECHNOLOGY FOR ENERGY TRANSITION 2024年 79卷

作者： Wu, Xueyang Shan, Yinghao Lin, Xiaowu Donghua Univ Coll Informat Sci & Technol Dept Elect Engn Shanghai 201620 Peoples R China Donghua Univ Engn Res Ctr Digitized Text & Apparel Technol Minist Educ Shanghai 201620 Peoples R China

Hierarchical control of AC microgrids, despite providing stable voltage, frequency, and optimal power distribution, is susceptible to false data injection (FDI) attacks on its secondary control. Electric power systems in countries such as the United States and Venezuela have suffered cyberattacks. This paper proposes a redundant secondary control method to resist FDI attacks. This method uses distributed generators (DGs) online as redundant units on standby, generating dynamic corrections to the attacked DGs, thus eliminating the attack impact. It effectively addresses the numerical tampering and addition brought by FDI to the frequency and voltage setting values of the secondary control, ensuring the microgrid can still output stable frequency and voltage. The principle of this control method is direct and practical;it does not require complex controllers and can respond quickly to FDI attacks. Then, focusing on a microgrid system containing six DGs, the setting values of the microgrid system are tampered with by multiple values in different time periods, the simulation results confirm that the proposed method can effectively resist FDI attacks under various scenarios. Finally, field programmable gate array (fpga)-in-the-loop experiments further verify the effectiveness of the proposed method.

关键词： FDI attacks Redundant secondary control method AC microgrids fpga-in-the-loop

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Hardware-in-the-loop simulation and implementation of a fuzzy logic controller with fpga: case study of a magnetic levitation system

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TRANSACTIONS OF THE INSTITUTE OF MEASUREMENT AND CONTROL 2019年第8期41卷 2150-2159页

作者： Akbati, Onur Uzgun, Hatice Didem Akkaya, Sirin Yildiz Tech Univ Dept Control & Automat Engn TR-34220 Istanbul Turkey Istanbul Tech Univ Dept Mechatron Engn Istanbul Turkey

This paper presents the design and implementation of a fuzzy logic controller using Very High Speed Integrated Circuit Hardware Description Language (VHDL) on a field programmable gate array (fpga). First, a Sugeno-type fuzzy logic controller with five triangular and trapezoidal membership functions for two inputs and with nine singleton membership functions for one output is examined. The proposed structure is tested with second- and third-order system model using fpga-in-the-loop simulation via a MATLAB/Simulink environment. Then, for different kinds of fuzzy logic controllers, a new look-up table (LUT) and interpolation-based controller implementation is proposed to eliminate the computational complexity of the primarily designed structure. As a case study, a magnetic levitation system is controlled with an adaptive neuro-fuzzy inference system (ANFIS) trained fuzzy logic controller, then it is simulated and implemented using a LUT-based controller. Finally, we provide a comparison of results.

关键词： fpga VHDL fpga-in-the-loop look-up table fuzzy logic ANFIS magnetic levitation

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Hardware Design with Real-Time Implementation for Security of Medical Images and EPMR

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2022年第2期41卷 867-891页

作者： Ghosh, Sudip Bhateja, Yuvam Palathinkal, Joshua Roy Rahaman, Hafizur Indian Inst Engn Sci & Technol IIEST Sch VLSI Technol Sibpur India IIEST Elect & Telecommun Engn Dept Sibpur India IIEST Dept Informat Technol Sibpur India

In this article, an fpga-based hardware prototype design has been proposed and implemented in real time for the security of the Electronic Patient Medical Record. This proposed hardware can be integrated into various medical image scanning instruments like X-ray, ultrasonography, magnetic resonance imaging, and computed tomography machines, which can embed the health record of a patient into his/her scanned medical images in real time. The fpga prototype was implemented using Xilinx Spartan-3E fpga. The hardware resource utilization results have been observed to be low and practically viable. High operating speed up to 245 MHz (for joint embedding-cum-encryption process) and up to 252 MHz (for joint decoding-cum-decryption process) is achieved, with a respective low power consumption of 95 mW and 82 mW. Extracting the medical data is possible using a key, generated within the proposed algorithm using the patient's fingerprint. The proposed hardware architecture is the first architecture for the algorithm proposed in this article to the best of our knowledge.

关键词： fpga-in-the-loop Digital watermarking Xilinx system generator (SysGen) Medical image security Cryptography Extended Hamming code (EHC) Electronic Patient Medical Record (EPMR)

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LMI-based Predictive Control Applied to the Single-phase PWM Inverter with LC Filter 8

LMI-based Predictive Control Applied to the Single-phase PWM...

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8th Southern Power Electronics Conference and the 17th Brazilian Power Electronics Conference, SPEC / COBEP 2023

作者： Andrea, Cristiano Quevedo Batista, Edson Antonio Pereira, Luís Felipe Da S. C. Gomes De Brito, Moacyr Aureliano De Souza, Gustavo Vargas Architecture and Urban Planning and Geography Ufms Faculty of Engineering Campo Grande Brazil Control Research Laboratory Unesp Electrical Engineering Department Ilha Solteira Brazil

ISBN: (纸本)9798350321128

This work proposes a design methodology for predictive control applied to the single-phase PWM inverter with an LC filter. The control system purpose is to track a sinusoidal signal at the inverter output. The designed control system consists of predicted state feedback which is implemented by uses of the principle of receding horizon. In the inverter model, we have incorporated integral action by utilizing the future discrete state variable of the inverter through an embedded integrator. The methodology is described using linear matrix inequalities, which can be efficiently solved using convex programming techniques to obtain the optimal solution. Real-time fpga-based hardware-in-the-loop simulations illustrate the viability of the proposed control system and demonstrate that the controller can achieve sinusoidal reference signal tracking performance as well as suitable disturbance rejection. © 2023 IEEE.

关键词： fpga-in-the-loop Linear Matrix Inequalities Predictive Control Single-phase PWM Inverter

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LMI-Based MPC Design Applied to the Single-Phase PWM Inverter with LC Filter under Uncertain Parameters

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SENSORS 2024年第13期24卷 4325页

作者： Andrea, Cristiano Quevedo Batista, Edson Antonio Pereira, Luis Felipe da Silva Carlos de Brito, Moacyr Aureliano Gomes de Souza, Gustavo Vargas Univ Fed Mato Grosso do Sul Fac Engn Architecture & Urban Planning & Geog BR-79070900 Campo Grande MS Brazil Sao Paulo State Univ Sch Engn Dept Elect Engn BR-17033360 Ilha Solteira SP Brazil

This work proposes a design methodology for predictive control applied to the single-phase PWM inverter with an LC filter. In the design, we considered that the PWM inverter has parametric uncertainties in the filter inductance and output load resistance. The control system purpose is to track a sinusoidal signal at the inverter output. The designed control system with an embedded integrator uses the principle of receding horizon control, which underpinned predictive control. The methodology was described by linear matrix inequalities, which can be solved efficiently using convex programming techniques, and the optimal solution is obtained. MATLAB-Simulink and real-time fpga-in-the-loop simulations illustrate the viability of the proposed control system. The LMI-based MPC reveals an effective performance for tracking of a sinusoidal reference signal and disturbance rejection of input voltage and load perturbations for the inverter subject to uncertainties.

关键词： single-phase PWM inverter fpga-in-the-loop predictive control linear matrix inequalities

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Robust control of a wind energy conversion system: fpga real-time implementation

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HELIYON 2024年第15期10卷 e35712页

作者： El Attafi, Abdelhafid El Alami, Houda Bossoufi, Badre AlQahtani, Dokhyl Motahhir, Saad Almalki, Mishari Metab Alghamdi, Thamer A. H. Sidi Mohammed Ben Abdellah Univ Fac Sci Dhar El Mahraz LIMS Lab Fes 30003 Morocco Prince Sattam bin Abdulaziz Univ Coll Engn Dept Elect Engn Al Kharj 11942 Saudi Arabia Sidi Mohammed Ben Abdellah Univ ENSA Fes 30000 Morocco Al Baha Univ Fac Engn Dept Elect Engn Alaqiq Ksa Saudi Arabia Cardiff Univ Wolfson Ctr Magnet Sch Engn Cardiff CF24 3AA England Al Baha Univ Fac Engn Elect Engn Dept Al Baha 65779 Saudi Arabia

This study employs an fpga board to implement a robust control technique for wind energy conversion systems (WECS). This approach facilitates extensive testing and validation of the control system across diverse wind conditions, utilizing the fpga's parallel processing capabilities and advanced control algorithms. This method ensures robustness against nonlinearities and system uncertainties. fpga-in-the-loop (FIL) testing provides precise and effective simulation results, enabling rapid prototyping and iterative modifications of control algorithms. The effectiveness of the robust control strategy is confirmed by FIL findings, demonstrating significant improvements in WECS stability and efficiency. Furthermore, the study highlights the strategy's potential to enhance WECS reliability and efficiency in real-world applications.

关键词： Wind energy conversion system fpga DFIG Proportional integral derivative controller HDL fpga-in-the-loop MATLAB/Simulink

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