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Engineering Research Express 2025年第2期7卷

作者： Ali, Aijaz Bingi, Kishore Ibrahim, Rosdiazli Bansal, Lalit Omar, Madiah Department of Electrical and Electronics Engineering Universiti Teknologi PETRONAS Seri Iskandar Malaysia Central Scientific Instruments Organization (CSIR) Sector 30 Chandigarh 160030 India Department of Chemical Engineering Universiti Teknologi PETRONAS Seri Iskandar Malaysia

Implementing fpga-based fractional-order controllers in real-time applications can be challenging due to their memory dependencies. These dependencies require high-order integers, leading to several design complications. Issues such as large design sizes, space exploration, and difficulty creating configurable hardware can affect resource utilization, power consumption, and accuracy. Therefore, this paper presents the implementation of a family of fractional-order PID controllers on the Zynq-7000 fpga using the Tustin approximation technique, which addresses the memory dependency issue in real-time applications. A hybrid approach combining fixed and floating-point methods enhances computational efficiency, reducing resource utilization alongside greater precision and accuracy. The controllers evaluated include PID, PI-PD1, PI-PD2, PIDD, PI^α-PD1, PI^α-PD2, PI-PD^β1, PI-PD^β2, PI^α-PD^β1, PI^α-PD^β2, PI^αD^β, and PIDD^β. These controllers are implemented on three different plants, allowing for a comparison between fractional-order and traditional controllers. The design utilizes the fpga-in-the-loop (FIL) feature for real-time validation and performance evaluation through MATLAB/Simulink and Xilinx Vivado. In Plant 1, the PI^α-PD2 controller exhibits the least overshoot and the shortest rise time with power consumption from Xilinx of 0.3W. Similarly, in plant 2, all the fractional-order controllers demonstrate less overshoot and quicker settling time than the integer-order controllers with a power consumption of 0.3W. Finally, in plant 3, the fractional-order controller achieves significantly less overshoot and a much shorter rise time than traditional controllers, with power consumption ranging from 3W to 4W. Overall, the performance of Zynq-7000 fpga-based fractional-order controllers shows improvements in step response characteristics, resource u

关键词： fixed-point floating-point fpga-in-the-loop fractional-order controllers resource utilization Xilinx Vivado Zynq-7000 fpga

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fpga-in-the-loop Co-simulation of Reentrant Arrhythmia Mechanism in One Dimensional (1D) Ring-Shaped based on FitzHugh-Nagumo Model 4

FPGA-in-the-Loop Co-simulation of Reentrant Arrhythmia Mecha...

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4th IEEE International Conference on Control System Computing and Engineering (ICCSCE 2014)

作者： Adon, Nur Atiqah Mahmud, Farhanahani Jabbar, Mohamad Hairol Othman, Norliza Univ Tun Hussein Onn Malaysia UTHM Cardiol & Physiome Anal Res Lab Fac Elect & Elect Engn Microelect & Nanotechnol Shamsudin Res Ctr MiNT S Batu Pahat Johor Malaysia Univ Tun Hussein Onn Malaysia UTHM Manycore Syst Chip MCSoC Res Lab Fac Elect & Elect Engn Microelect & Nanotechnol Shamsudin Res Ctr MiNT S Batu Pahat Johor Malaysia

ISBN: (纸本)9781479956869

This paper presents the simulation of reentrant excitation-conduction of cardiac cells realized by coupling 80 active circuits in one dimensional (1D) ring-shaped based on FitzHugh-Nagumo (FHN) model. 1D ring-shaped cable model is designed using Simulink in order to simulate an action potential signal and its conduction for a hardware design by using HDL Coder to automate the model for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) code generation. Then, the VHDL design is functionally verified on a Field Programmable Gate Array (fpga) Xilinx Virtex-6 board using HDL Verifier proving the model through fpga-in-the-loop (FIL) co-simulation approach. It can then be downloaded into a target fpga device for real-time simulations. This novel approach of prototyping cardiac reentrant excitation-conduction provides a fast and effective fpga-based hardware implementation flow towards a stand-alone implementation to perform complex real-time simulations compared with manual HDL designs.

关键词： Reentrant FitzHugh-Nagumo Model HDL Coder fpga-in-the-loop real-time simulations

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Improving Efficiency of fpga-in-the-loop Verification Environment 13

Improving Efficiency of FPGA-in-the-Loop Verification Enviro...

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13th IFAC and IEEE Conference on Programmable Devices and Embedded Systems

作者： Zadek, Pawel Koczor, Arkadiusz Golek, Michal Matoga, Lukasz Penkala, Piotr Evatronix SA Bielsko Biala Poland

The paper presents techniques being developed in order to improve verification efficiency in the fpga-in-the-loop environment. The verification speed-up in relation to typical software simulation within MATLAB (R) suite offered to the presented verification environment is in the range of 100s. The proposed verification environment enables engineers to verify their designs by co-simulation of high-level models with RTL logic. It allows for checking if the prepared VHDL or Verilog code matches the more abstract reference model. The introduced verification environment uses MATLAB (R) and Simulink (R) models, being the de facto modelling standard in the industry. The paper presents a solution which improves signal visibility of a design-under-test and accelerates simulation performance by moving DUT into an fpga. The implemented original fpga based emulation platform offers an efficient interface channel to a host workstation and a GUI software with an embedded viewer for dynamic signal selection and observation. It may be applied to a broad range of simulation subjects. (C) 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： design verification emulation platform debugging fpga-in-the-loop co-simulation

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Model predictive control for sodium fast reactors based on Laguerre functions and fpga-in-the-loop environment

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NUCLEAR ENGINEERING AND DESIGN 2022年 400卷

作者： Pereira, Luis Felipe da S. C. Batista, Edson Antonio Pinto, Joao Onofre Pereira Upadhyaya, Belle R. Hines, J. Wesley Coble, Jamie B. Univ Fed Mato Grosso do Sul Fac Engn Architecture & Urban Planning & Geog BR-79070900 Campo Grande Brazil Oak Ridge Natl Lab Oak Ridge TN USA Univ Tennessee Knoxville TN USA

This paper proposes a multiple-input multiple-output (MIMO) model predictive control (MPC) design with constraints and Laguerre functions using the simplified model of the primary system (reactor core and intermediate heat exchanger (IHX)) of a prototypical sodium fast reactor (SFR). The control aims at tracking the reactor power, sodium tank temperature and the primary inlet plenum temperature when the reactor operates at 100% capacity by controlling the reactivity and the secondary sodium flow rate. For comparison criteria, this paper simulates the insertion of disturbances related to the reactivity and the sodium inlet temperature. The analysis includes the simulation of the insertion of disturbances in the reactivity and the sodium inlet temperature. The controller design was developed in MATLAB and Simulink, and was tested under a variety of reactivity disturbances (-1 and -5 cents) and a sodium inlet temperature disturbance of +10 degrees F. In each case studied, the MPC tracked the outputs effectively. The proposed MPC-SFR obtained a faster and more robust disturbance rejection regarding insertion of reactivity and sodium inlet temperature when compared with SFR controlled by digital PI controllers (PI-SFR). Finally, the controller was embedded in a Field Programmable Gate Array (fpga) device in order to demonstrate the fpga-in-the-loop (FIL) feature and to compare it with the results using MATLAB-Simulink.

关键词： Model predictive control Laguerre orthonormal functions Quadratic programming Sodium fast reactor fpga-in-the-loop

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Improving Efficiency of fpga-in-the-loop Verification Environment

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IFAC-PapersOnLine 2015年第4期48卷 180-185页

作者： Pawel Ządek Arkadiusz Koczor Michal Gołek Łukasz Matoga Piotr Penkala Evatronix S.A. Bielsko-Biala Poland

The paper presents techniques being developed in order to improve verification efficiency in the fpga-in-the-loop environment. The verification speed-up in relation to typical software simulation within MATLAB® suite offered to the presented verification environment is in the range of 100s. The proposed verification environment enables engineers to verify their designs by co-simulation of high- level models with RTL logic. It allows for checking if the prepared VHDL or Verilog code matches the more abstract reference model. The introduced verification environment uses MATLAB® and Simulink® models, being the de facto modelling standard in the industry. The paper presents a solution which improves signal visibility of a design-under-test and accelerates simulation performance by moving DUT into an fpga. The implemented original fpga-based emulation platform offers an efficient interface channel to a host workstation and a GUI software with an embedded viewer for dynamic signal selection and observation. It may be applied to a broad range of simulation subjects.

关键词： design verification emulation platform debugging fpga-in-the-loop co-simulation

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Hardware-in-the-loop simulation and implementation of a fuzzy logic controller with fpga: case study of a magnetic levitation system

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TRANSACTIONS OF THE INSTITUTE OF MEASUREMENT AND CONTROL 2019年第8期41卷 2150-2159页

作者： Akbati, Onur Uzgun, Hatice Didem Akkaya, Sirin Yildiz Tech Univ Dept Control & Automat Engn TR-34220 Istanbul Turkey Istanbul Tech Univ Dept Mechatron Engn Istanbul Turkey

This paper presents the design and implementation of a fuzzy logic controller using Very High Speed Integrated Circuit Hardware Description Language (VHDL) on a field programmable gate array (fpga). First, a Sugeno-type fuzzy logic controller with five triangular and trapezoidal membership functions for two inputs and with nine singleton membership functions for one output is examined. The proposed structure is tested with second- and third-order system model using fpga-in-the-loop simulation via a MATLAB/Simulink environment. Then, for different kinds of fuzzy logic controllers, a new look-up table (LUT) and interpolation-based controller implementation is proposed to eliminate the computational complexity of the primarily designed structure. As a case study, a magnetic levitation system is controlled with an adaptive neuro-fuzzy inference system (ANFIS) trained fuzzy logic controller, then it is simulated and implemented using a LUT-based controller. Finally, we provide a comparison of results.

关键词： fpga VHDL fpga-in-the-loop look-up table fuzzy logic ANFIS magnetic levitation

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Gain-analytical equations generalized for FOPID controllers — An application with DC–DC power converters

e-Prime - Advances in Electrical Engineering, Electronics an...

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e-Prime - Advances in Electrical Engineering, Electronics and Energy 2025年 12卷

作者： Pereira, Luís Felipe da S.C. Volpato, Anderson S. Batista, Edson Antonio de Brito, Moacyr A.G. Godoy, Ruben B. Pinto, João O.P. Tolbert, Leon M. Faculty of Engineering Architecture and Urban Planning and Geography Federal University of Mato Grosso do Sul University City Campo Grande 79070-900 Brazil Oak Ridge National Laboratory Oak Ridge TN United States Min H. Kao Department of Electrical Engineering and Computer Science University of Tennessee Knoxville TN United States

This study presents algebraic formulations for determining the gains of a fractional-order PID (FOPID) regulator, with attention to gain crossover frequency, phase margin, and robustness against gain variations (iso-damping). The differential evolution (DE) algorithm is employed for optimal tuning of fractional-order values, aligned with FOPID gain parameters. fpga-in-the-loop simulations for Buck and DC–DC Boost converters are conducted to validate the DE-tuned FOPID controllers, optimized using the L² norm and compared to MATLAB-Simulink simulations. The approach introduces a key innovation: disaggregating the FOPID equation for memory efficiency. Simulations and experiments demonstrate the controller's precision in setpoint tracking and resilience to load and input voltage variations in Buck and DC–DC Boost converters, with effective damping of load disturbances. A test bench validated the proposed method, which was also compared to conventional PID, Type 3, and PIDD2-IMC controllers. While the proposed FOPID controller performed better in the presented results, a conclusive comparison could not be drawn due to unequal tuning efforts. Future work will focus on a more thorough comparison of controllers. © 2025

关键词： Buck converter DC–DC boost converter Differential evolution fpga-in-the-loop Fractional-order PID Oustaloup filter

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A redundant secondary control scheme to resist FDI attacks in AC microgrids

SCIENCE AND TECHNOLOGY FOR ENERGY TRANSITION

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SCIENCE AND TECHNOLOGY FOR ENERGY TRANSITION 2024年 79卷

作者： Wu, Xueyang Shan, Yinghao Lin, Xiaowu Donghua Univ Coll Informat Sci & Technol Dept Elect Engn Shanghai 201620 Peoples R China Donghua Univ Engn Res Ctr Digitized Text & Apparel Technol Minist Educ Shanghai 201620 Peoples R China

Hierarchical control of AC microgrids, despite providing stable voltage, frequency, and optimal power distribution, is susceptible to false data injection (FDI) attacks on its secondary control. Electric power systems in countries such as the United States and Venezuela have suffered cyberattacks. This paper proposes a redundant secondary control method to resist FDI attacks. This method uses distributed generators (DGs) online as redundant units on standby, generating dynamic corrections to the attacked DGs, thus eliminating the attack impact. It effectively addresses the numerical tampering and addition brought by FDI to the frequency and voltage setting values of the secondary control, ensuring the microgrid can still output stable frequency and voltage. The principle of this control method is direct and practical;it does not require complex controllers and can respond quickly to FDI attacks. Then, focusing on a microgrid system containing six DGs, the setting values of the microgrid system are tampered with by multiple values in different time periods, the simulation results confirm that the proposed method can effectively resist FDI attacks under various scenarios. Finally, field programmable gate array (fpga)-in-the-loop experiments further verify the effectiveness of the proposed method.

关键词： FDI attacks Redundant secondary control method AC microgrids fpga-in-the-loop

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Testing framework for on-board verification of HLS modules using grey-box technique and fpga overlays

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INTEGRATION-THE VLSI JOURNAL 2019年 68卷 129-138页

作者： Caba, Julian Rincon, Fernando Dondo, Julio Barba, Jesus Abaldea, Manuel Carlos Lopez, Juan Univ Castilla La Mancha Sch Comp Sci E-13071 Ciudad Real Spain Univ Nacl San Luis Av Ejercito los Andes 950D5700 BPB San Luis Argentina

High-Level Synthesis (HLS) provides a simple way to implement complex applications using Field Programmable Gate Array (fpga) devices. Unfortunately, this technology introduces non-negligible problems related to verification: speed, accuracy and behavior mismatch between co-simulation and implementation. This paper presents RC-Unity, a heterogeneous unit testing framework that integrates fpga-in-the-loop devices in order to extend the scope and capabilities of current HLS tools. Verification engineers can focus on the design of the tests while the framework automates the generation of the underlying verification infrastructure, making the testbed reusable across different stages of the design flow as the experiments show.

关键词： Design for testability Testing framework fpga-in-the-loop High-level synthesis Verification overlay

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Hardware Design with Real-Time Implementation for Security of Medical Images and EPMR

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2022年第2期41卷 867-891页

作者： Ghosh, Sudip Bhateja, Yuvam Palathinkal, Joshua Roy Rahaman, Hafizur Indian Inst Engn Sci & Technol IIEST Sch VLSI Technol Sibpur India IIEST Elect & Telecommun Engn Dept Sibpur India IIEST Dept Informat Technol Sibpur India

In this article, an fpga-based hardware prototype design has been proposed and implemented in real time for the security of the Electronic Patient Medical Record. This proposed hardware can be integrated into various medical image scanning instruments like X-ray, ultrasonography, magnetic resonance imaging, and computed tomography machines, which can embed the health record of a patient into his/her scanned medical images in real time. The fpga prototype was implemented using Xilinx Spartan-3E fpga. The hardware resource utilization results have been observed to be low and practically viable. High operating speed up to 245 MHz (for joint embedding-cum-encryption process) and up to 252 MHz (for joint decoding-cum-decryption process) is achieved, with a respective low power consumption of 95 mW and 82 mW. Extracting the medical data is possible using a key, generated within the proposed algorithm using the patient's fingerprint. The proposed hardware architecture is the first architecture for the algorithm proposed in this article to the best of our knowledge.

关键词： fpga-in-the-loop Digital watermarking Xilinx system generator (SysGen) Medical image security Cryptography Extended Hamming code (EHC) Electronic Patient Medical Record (EPMR)

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