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Spiketrum: An fpga-based implementation of a Neuromorphic Cochlea

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第4期72卷 1648-1656页

作者： Alsakkal, Anas Wijekoon, Jayawan Univ Manchester Dept Elect & Elect Engn Manchester M13 9PL England

This paper presents a novel fpga-based neuromorphic cochlea, leveraging the general-purpose spike-coding algorithm, Spiketrum. The focus of this study is on the development and characterization of this cochlea model, which excels in transforming audio vibrations into biologically realistic auditory spike trains. These spike trains are designed to withstand neural fluctuations and spike losses while accurately encapsulating the spatial and precise temporal characteristics of audio, along with the intensity of incoming vibrations. Noteworthy features include the ability to generate real-time spike trains with minimal information loss and the capacity to reconstruct original signals. This fine-tuning capability allows users to optimize spike rates, achieving an optimal balance between output quality and power consumption. Furthermore, the integration of a feedback system into Spiketrum enables selective amplification of specific features while attenuating others, facilitating adaptive power consumption based on application requirements. The hardware implementation supports both spike-based and non-spike-based processors, making it versatile for various computing systems. The cochlea's ability to encode diverse sensory information, extending beyond sound waveforms, positions it as a promising sensory input for current and future spike-based intelligent computing systems, offering compact and real-time spike train generation.

关键词： Spike-based coding neuromorphic engineering cochlea cochlea fpga-based implementation fpga-based implementation Gammatone filters Gammatone filters Gammatone filters

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fpga-based implementation of cuckoo search

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第1期13卷 28-37页

作者： Alfailakawi, Mohammad Gh. El-Shafei, Mohammed Ahmad, Imtiaz Salman, Ayed Kuwait Univ Comp Engn Dept Khaldiyah POB 5969 Safat 13060 Kuwait

Cuckoo search (CS) is a recent swarm intelligence-based meta-heuristic optimisation algorithm that has shown excellent results for a broad class of optimisation problems in diverse fields. However, CS is generally compute intensive and slow when implemented in software requiring large number of fitness function evaluations to obtain acceptable solutions. In this study, the authors present a problem specific parallel pipelined field programmable gate array-based accelerator to reduce execution time when solving complex optimisation problems. Experiments conducted on a large number of well-known benchmark functions revealed that the hardware approach offers a promising average speedup of 75x and 53x than software and GPU implementations, respectively.

关键词： swarm intelligence search problems optimisation field programmable gate arrays parallel processing mathematics computing pipeline processing fpga-based implementation cuckoo search CS swarm intelligence-based meta-heuristic optimisation algorithm fitness function evaluations parallel pipelined fpga-based accelerator field programmable gate array execution time reduction complex optimisation problems benchmark functions

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Bifurcation and chaos in a smooth 3D dynamical system extended from Nose-Hoover oscillator

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CHAOS SOLITONS & FRACTALS 2022年 158卷

作者： Cang, Shijian Wang, Luo Zhang, Yapeng Wang, Zenghui Chen, Zengqiang Tianjin Univ Sci & Technol Dept Prod Design Tianjin 300222 Peoples R China Tianjin Univ Sci & Technol Coll Mech Engn Tianjin Key Lab Integrated Design & Online Monitor Tianjin 300222 Peoples R China Tianjin Univ Sci & Technol Sch Elect Informat & Automation Tianjin 300222 Peoples R China Tianjin Univ Technol Tianjin Key Lab Control Theory & Applicat Complica Tianjin 300384 Peoples R China Univ South Africa Dept Elect Engn ZA-1710 Florida South Africa Nankai Univ Coll Artificial Intelligence Tianjin 300350 Peoples R China

The chaotic system with complicated dynamical behaviors has high potential in practical applications. This paper reports a simple smooth 3D dynamical system that is derived from the Nose-Hoover oscillator and has rich dynamical behaviors, such as fold-Hopf bifurcation, saddle-node bifurcation, transient chaos, and conservative chaos (hidden attractors), which respectively correspond to four cases of equilibrium: infinitely many equilibria, two equilibria, four equilibria and no equilibrium. We first concentrate on the theoretical investigation of degenerate fold-Hopf and saddle-node bifurcations. Then, the power-law distribution of average lifetime of transient chaos is calculated and the coexistence of steady state and periodic motion after transient chaos is partially exhibited by time series. For the case of no equilibrium, we further study the conservative and ergodic dynamics, and hidden attractors with extremely rare properties by time-domain waveforms, phase portraits, histograms and Poincare sections. Finally, the fpga-based experimental results are presented and they are consistent with the numerical simulation results.

关键词： Degenerate fold-Hopf bifurcation Saddle-node bifurcation Transient chaos Conservative chaos Hidden chaotic attractors fpga-based implementation

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Bifurcations to bursting and spiking in the Chay neuron and their validation in a digital circuit

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CHAOS SOLITONS & FRACTALS 2020年 141卷 110353-110353页

作者： Xu, Quan Tan, Xiao Zhu, Dong Bao, Han Hu, Yihua Bao, Bocheng Changzhou Univ Sch Informat Sci & Engn Changzhou 213164 Jiangsu Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Automat Engn Nanjing 211106 Peoples R China Univ York Dept Elect Engn York YO10 5DD N Yorkshire England

Due to the great importance of the outward current carried by K+ ions and the inward one by Na+ and Ca(2+)ions in 3-D Chay neuron model, the dynamical behaviors associated with the maximal conductances of K(+)ions channel and mixed Na+-Ca(2+)ions channel are explored for better demonstrating dynamical effects on the electrical activities in this paper. By utilizing some common dynamical exploring methods, the representative electrical activities of bursting and spiking behaviors endowed with the fast-slow structure of the 3-D Chay neuron model are revealed and classified on the dependence of the two maximal conductances. Moreover, the bifurcation mechanisms for periodic fold/fold bursting, periodic and chaotic fold/homoclinic bursting, and chaotic spiking behaviors are expounded qualitatively by fast-slow dynamical analysis with some specified model parameters. Finally, based on a field programmable gate array (fpga), a digitally circuit-implemented electronic neuron is made, from which the chaotic and periodic bursting/spiking behaviors are experimentally captured to confirm the numerical simulations. (C) 2020 Elsevier Ltd. All rights reserved.

关键词： Bifurcation Bursting behavior Chay neuron model fpga-based implementation Spiking behavior

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An fpga-based architecture for a latitude and longitude correction in autonomous navigation tasks

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MEASUREMENT 2021年 182卷 109757-109757页

作者： Correa-Caicedo, Pedro J. Barranco-Gutierrez, Alejandro I. Guerra-Hernandez, Erick I. Batres-Mendoza, Patricia Padilla-Medina, Jose A. Rostro-Gonzales, Horacio Tecnol Nacl Mexico Celaya Celaya 38010 Mexico Catedras CONACYT Mexico City DF Mexico Univ Autonoma Benito Juarez Oaxaca Escuela Sistemas Biol & Innovac Tecnol Oaxaca 68120 Oaxaca Mexico Univ Guanajuato Dept Elect Salamanca 36885 Mexico

The response speed of the intelligent systems embedded in an autonomous vehicle is crucial for its correct operation and reduction of the risks on the road derived from autonomous driving. For that reason, it is necessary to optimize the algorithms that process the data from the sensors;with that aim the Field-Programmable Gate Arrays (fpgas) offer the possibility of parallelizing the tasks to be carried out by mentioned systems, accelerating their response and improving their performance. In this regard, this paper introduces a fuzzy absolute position correction system, which corrects the latitude and longitude data registered from a GPS Pmod sensor and its implementation on a fpga to speed up the correction results. A necessary comparison of the algorithm execution time on different platforms such as: A Raspberry pi 4 model B, a personal computer (PC) with Ubuntu 18.04.4 64bit and the fpga model, was performed to validate the results and the effectiveness of the implementation. The correction system was validated in software and hardware on 4 different routes, each of them with a large number of samples. The results were highly similar in the three platforms;however, the fpga-based implementation offers a speed up of 40000x compared to software-based implementations.

关键词： fpga-based implementation Fuzzy Systems GPS Data Correction

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Novel Algorithm and Architectures for High-Speed Low-Power ConText-based Steganography 19

Novel Algorithm and Architectures for High-Speed Low-Power C...

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19th International Symposium on Computer Architecture and Digital Systems (CADS)

作者： Timarchi, Somayeh Alaei, Masoud Abbasi Koushkbaghi, Hossein Shahid Beheshti Univ Dept Elect Engn Tehran Iran Univ Twente Dept Elect Engn Math & Comp Sci Enschede Netherlands

ISBN: (纸本)9781538643792

Least Significant Bit (LSB) insertion method is a popular type of steganographic algorithms in spatial domain. Nevertheless, in this approach essential measures should be considered to enhance the both visual quality and security properties. ConText is a revised version of LSB method to hide secret information in image carrier with enhanced visual imperceptibility. This paper introduces a novel algorithm based on ConText, called the Modified ConText (MCT). The proposed algorithm is based on using a threshold level to compare pixels in a sub-block which leads to faster and power efficient implementation. We strengthen the ConText algorithm which can embed data in a more noisy-like area to increase security and visual quality. Moreover, a high-speed hardware implementation of the MCT algorithm is also presented by employing faster comparisons. In addition to assigning threshold value that can lead to a more efficient architecture, the pre-computation low power technique is also employed to reduce power consumption. The proposed architecture is synthesized by the ISE tool and implemented on a Spartan-3 fpga device. The results imply that the proposed architecture outperforms the system frequency, the usage of fpga resources, and power consumption by approximately 7%, 30%, and 64%, respectively.

关键词： Steganography LSB insertion fpga-based implementation Pre-computation technique Low-power design

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An fpga-based integrated signal conditioner for measurement of position, velocity and acceleration of a rotating shaft using an incremental encoder 1

An FPGA-based integrated signal conditioner for measurement ...

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1st IEEE International Conference on Control, Measurement and Instrumentation (CMI)

作者： Banerjee, K. Dam, B. Majumdar, K. Jadavpur Univ Dept Instrumentat & Elect Engn Salt Lake Campus Kolkata 700098 W Bengal India

ISBN: (纸本)9781479917693

Digital motion control applications, where electric motors are utilized as actuators, use incremental encoders as feedback devices to sense the rotating shaft position. However, for the controller to implement an accurate tracking of input position or velocity trajectories, and to make the tracking performance robust with respect to unpredictable disturbances like parameter uncertainties and load fluctuations, measurement of velocity and acceleration data is also required. In majority of the existing digital motion control solutions, direct measurement of velocity and acceleration is rarely done. Instead, they are estimated from the discrete position data obtained from the incremental encoder. Well documented velocity and acceleration estimation algorithms exist, and the literature report both simulation and experimental results on the performance of the said algorithms with typical input position trajectories. However, no integral hardware module that uses an incremental encoder to provide position, velocity and acceleration measurement is reported. This paper presents the design and fpga-based implementation of an integrated signal conditioner that uses the signals coming from an incremental encoder to measure the current position, and then estimate the current velocity and acceleration from it, and its performance on a test-rig. With a fast, industry-standard serial link, the proposed signal conditioner qualifies to be an integrated feedback device in digital motion control applications.

关键词： Digital motion control incremental encoders velocity and acceleration estimation fpga-based implementation signal conditioner

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Using Stochastic Computing to Reduce the Hardware Requirements for a Restricted Boltzmann Machine Classifier 16

Using Stochastic Computing to Reduce the Hardware Requiremen...

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ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (fpga)

作者： Li, Bingzhe Najafi, M. Hassan Lilja, David J. Univ Minnesota Dept Elect & Comp Engn St Paul MN 55414 USA

ISBN: (纸本)9781450338561

Artificial neural networks are powerful computational systems with interconnected neurons. Generally, these networks have a very large number of computation nodes which forces the designer to use software-based implementations. However, the software based implementations are offline and not suitable for portable or real-time applications. Experiments show that compared with the software based implementations, fpga-based systems can greatly speed up the computation time, making them suitable for real-time situations and portable applications. However, the fpga implementation of neural networks with a large number of nodes is still a challenging task. In this paper, we exploit stochastic bit streams in the Restricted Boltzmann Machine (RBM) to implement the classification of the RBM handwritten digit recognition application completely on an fpga. We use finite state machine based (FSM) stochastic circuits to implement the required sigmoid function and use the novel stochastic computing approach to perform all large matrix multiplications. Experimental results show that the proposed stochastic architecture has much more potential for tolerating faults while requiring much less hardware compared to the currently un-implementable deterministic binary approach when the RBM consists of a large number of neurons. Exploiting the features of stochastic circuits, our implementation achieves much better performance than a software-based approach.

关键词： Neural network Restricted Boltzman Machine fpga-based implementation stochastic computing

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An fpga-based integrated signal conditioner for measurement of position, velocity and acceleration of a rotating shaft using an incremental encoder

An FPGA-based integrated signal conditioner for measurement ...

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IEEE International Conference on Control, Measurement and Instrumentation

作者： K. Banerjee B. Dam K. Majumdar Dept. of Instrumentation & Electronics Engineering Jadavpur University

ISBN: (纸本)9781479988501

关键词： Digital motion control Incremental encoders Velocity and acceleration estimation fpga-based implementation Signal conditioner

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Investigating Measurement Methods for High-Resolution Electromagnetic Field Side-Channel Analysis 14

Investigating Measurement Methods for High-Resolution Electr...

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14 International Symposium on Integrated Circuits (ISIC)

作者： Specht, Robert Heyszl, Johann Sigl, Georg Fraunhofer Inst AISEC Munich Germany Tech Univ Munich Munich Germany

ISBN: (纸本)9781479948338

Recent publications have emphasized the power of high-resolution, low-distance EM measurements for side channel analysis. In this paper, we investigate several aspects of such measurements, e.g. different coil-diameters, probe-to-die distances, bandwidths and spatial measurement resolutions. We use an fpga-based implementation of an AES s-box as device under test and perform measurements of the magnetic near-field. Using the peak amplitude of the magnetic near-field and the Pearson correlation coefficient as quality measures, we show that the probes with smallest diameters lead to the best results. We propose a suitable trade-off between measurement time and measurement quality by using one fourth of the coil diameter as spatial measurement resolution. We show that the correlation is decreasing significantly if a bandwidth less than 300 MHz is used and we recommend a bandwidth of 1 GHz. Additionally, we confirm that the maximum value of the measured EM amplitude decreases by 1/r(2), and the correlation of the measurement by 1/r with r being the distance between probe and die.

关键词： coils cryptography electromagnetic fields field programmable gate arrays probes AES s-box EM measurements fpga-based implementation Pearson correlation coefhcient coil-diameters embedded cryptographic devices high-resolution electromagnetic field side-channel analysis magnetic near-field measurement methods probe-to-die distances side channel analysis spatial measurement resolutions Bandwidth Correlation Position measurement Probes Spatial resolution Time measurement Voltage measurement

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