This paper describes a new approximate transform for the high efficiency video coding (HEVC). A 8 x 8 discrete cosine transform (DCT) approximation is proposed and then down-sampled or expanded to generate the 4 x 4, ...
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This paper describes a new approximate transform for the high efficiency video coding (HEVC). A 8 x 8 discrete cosine transform (DCT) approximation is proposed and then down-sampled or expanded to generate the 4 x 4, 16 x 16, and 32 x 32 approximate matrices. The proposed 8 x 8 approximation is carried out in part by neighbourhood in order to take the advantage of adjacent pixels correlation of natural images. Hence, rather than approximating the odd basis vectors of DCT kernel by referring to their intrinsic values, we choose to quantize that by taking into account their signs and positions. The proposed approximation matrices respect the properties of transform matrices prescribed by HEVC like orthogonality and bit-length of the basis vector elements. Furthermore, they have nearly the same arithmetic complexity and hardware requirement as those of recently proposed related methods, but involve significantly less error energy. Moreover, a reconfigurable design based on the 8 x 8 approximation transform is proposed in order to allow the simultaneous computation of eight 4-, four 8-, two 16-, or one 32-point approximate DCTs. It is found that the reconfigurable design can involve nearly 26% less area-delay product (ADP) when compared with the separate non-reconfigurable designs. Experimental results obtained from fpga prototype and HM simulations have demonstrated the advantages of the proposed transforms.
A wideband field-programmable gate array (fpga) basedhardwareimplementation for the m parameter estimation of the Nakagami-m fading channel is introduced. It requires fresh estimation of the noise spectrum power den...
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ISBN:
(纸本)9781479953448
A wideband field-programmable gate array (fpga) basedhardwareimplementation for the m parameter estimation of the Nakagami-m fading channel is introduced. It requires fresh estimation of the noise spectrum power density to actually evaluate the signal-to-noise ratio (SNR), and with it, one can efficiently measure the m parameter of Nakagami-m fading channel. The hardware employs a Xilinx Virtex-6 SX475T-2c fpga integrated Minibee platform operated in Centos system, in which a wideband quadrature modulator ADL5375 is integrated, with output frequency ranging from 400MHz to 6GHz. Such a hardware framework enables the measure system to function well in wireless wideband systems. In addition, we utilize it to conduct real-scenario estimations and compare the results with the software simulations. It also indicates our developed m parameter ML estimation has a better performance compared with some known estimation algorithms.
Medical imaging classification is one of the areas where using algorithm-basedhardware architecture improves performance, in terms of time processing. It gives better and clearer results than when using software impl...
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Medical imaging classification is one of the areas where using algorithm-basedhardware architecture improves performance, in terms of time processing. It gives better and clearer results than when using software implementation. Today, advantages of field-rogrammable gate array (fpga), including reusability, filed reprogramability, simpler design cycle, fast marketing and a combination of the main advantages of ASICs and DSPs make them powerful and very attractive devices for rapid prototyping of all images processing applications. In this paper, we use Xilinx system generator (XSG) environment to develop a hardware classification-based correlation algorithm from a system level approach. This architecture may be of great influence on the final choice to prove if the MRI image is with lesions brain or normal. Results are illustrated on a simple example for brain magnetic resonance imaging (MRI) images classification. Two sets are used: a set of normal MR images and another set with MR lesion brain images.
A wideband field-programmable gate array (fpga) basedhardwareimplementation for the m parameter estimation of the Nakagami-m fading channel is introduced. It requires fresh estimation of the noise spectrum power den...
详细信息
ISBN:
(纸本)9781479953455
A wideband field-programmable gate array (fpga) basedhardwareimplementation for the m parameter estimation of the Nakagami-m fading channel is introduced. It requires fresh estimation of the noise spectrum power density to actually evaluate the signal-to-noise ratio (SNR), and with it, one can efficiently measure the m parameter of Nakagami-m fading channel. The hardware employs a Xilinx Virtex-6 SX475T-2c fpga integrated Minibee platform operated in Centos system, in which a wideband quadrature modulator ADL5375 is integrated, with output frequency ranging from 400MHz to 6GHz. Such a hardware framework enables the measure system to function well in wireless wideband systems. In addition, we utilize it to conduct real-scenario estimations and compare the results with the software simulations. It also indicates our developed m parameter ML estimation has a better performance compared with some known estimation algorithms.
String matching is a ubiquitous problem that arises in a wide range of applications in computing, e.g., packet routing, intrusion detection, web querying, and genome analysis. Due to its importance, dozens of algorith...
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ISBN:
(纸本)9780769543017
String matching is a ubiquitous problem that arises in a wide range of applications in computing, e.g., packet routing, intrusion detection, web querying, and genome analysis. Due to its importance, dozens of algorithms and several data structures have been developed over the years. A recent breakthrough in this field is the FM-index, a data structure that synergistically combines the Burrows-Wheeler transform and the suffix array. In software, the FM-index allows searching (exact and approximate) in times comparable to the fastest known indices for large texts (suffix trees and suffix arrays), but has the additional advantage of being more space-efficient than those approaches. In this paper, we describe the first fpga-based hardware implementation of the FM-index for exact pattern matching. We report experimental results on the problem of mapping short DNA sequences to a reference genome. We show that the throughput of the FM-index is significantly higher than the naive (brute force) approach. Like the Bowtie software tool, the FM-index can abandon early the hardware matching. It outperforms Bowtie by two orders of magnitude*.
Computer vision is one of the areas where hardware-implemented algorithms perform clearly better than those implemented via software. Digital designers have so far optimized their designs by means of application speci...
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Computer vision is one of the areas where hardware-implemented algorithms perform clearly better than those implemented via software. Digital designers have so far optimized their designs by means of application specific integrated circuits (ASICs) or digital signal processors (DSPs). However, nowadays they are increasingly using field programmable gate arrays (fpgas), powerful hardware devices combining the main advantages of ASICs and DSPs with the possibility of re-programming, which make them very attractive devices for rapid prototyping. This paper shows how the Xilinx system generator (XSG) environment can be used to develop hardware-based computer vision algorithms from a system level approach, which makes it suitable for developing co-design environments. (C) 2004 Elsevier B.V. All rights reserved.
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