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Spiketrum: An fpga-based implementation of a Neuromorphic Cochlea

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第4期72卷 1648-1656页

作者： Alsakkal, Anas Wijekoon, Jayawan Univ Manchester Dept Elect & Elect Engn Manchester M13 9PL England

This paper presents a novel fpga-based neuromorphic cochlea, leveraging the general-purpose spike-coding algorithm, Spiketrum. The focus of this study is on the development and characterization of this cochlea model, which excels in transforming audio vibrations into biologically realistic auditory spike trains. These spike trains are designed to withstand neural fluctuations and spike losses while accurately encapsulating the spatial and precise temporal characteristics of audio, along with the intensity of incoming vibrations. Noteworthy features include the ability to generate real-time spike trains with minimal information loss and the capacity to reconstruct original signals. This fine-tuning capability allows users to optimize spike rates, achieving an optimal balance between output quality and power consumption. Furthermore, the integration of a feedback system into Spiketrum enables selective amplification of specific features while attenuating others, facilitating adaptive power consumption based on application requirements. The hardware implementation supports both spike-based and non-spike-based processors, making it versatile for various computing systems. The cochlea's ability to encode diverse sensory information, extending beyond sound waveforms, positions it as a promising sensory input for current and future spike-based intelligent computing systems, offering compact and real-time spike train generation.

关键词： Spike-based coding neuromorphic engineering cochlea cochlea fpga-based implementation fpga-based implementation Gammatone filters Gammatone filters Gammatone filters

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fpga-based implementation of cuckoo search

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第1期13卷 28-37页

作者： Alfailakawi, Mohammad Gh. El-Shafei, Mohammed Ahmad, Imtiaz Salman, Ayed Kuwait Univ Comp Engn Dept Khaldiyah POB 5969 Safat 13060 Kuwait

Cuckoo search (CS) is a recent swarm intelligence-based meta-heuristic optimisation algorithm that has shown excellent results for a broad class of optimisation problems in diverse fields. However, CS is generally compute intensive and slow when implemented in software requiring large number of fitness function evaluations to obtain acceptable solutions. In this study, the authors present a problem specific parallel pipelined field programmable gate array-based accelerator to reduce execution time when solving complex optimisation problems. Experiments conducted on a large number of well-known benchmark functions revealed that the hardware approach offers a promising average speedup of 75x and 53x than software and GPU implementations, respectively.

关键词： swarm intelligence search problems optimisation field programmable gate arrays parallel processing mathematics computing pipeline processing fpga-based implementation cuckoo search CS swarm intelligence-based meta-heuristic optimisation algorithm fitness function evaluations parallel pipelined fpga-based accelerator field programmable gate array execution time reduction complex optimisation problems benchmark functions

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fpga-based implementation of DTSFC and DTRFC algorithms

FPGA-based implementation of DTSFC and DTRFC algorithms

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31st Annual Conference of the IEEE-Industrial-Electronics-Society

作者： Charaabi, L Monmasson, E Nassani, MA Slama-Belkhodja, I LSE Ecole Natl Ingn Tunis Tunis Tunisia

ISBN: (纸本)0780392523

In this paper, authors present a fpga-based implementation of Direct Torque and Stator Flux Control (DTSFC) and Direct Torque and rotor Flux Control (DTRFC) with and without use of Space Vector Modulation (SVM) for induction motor drives. Indeed, due to their similar structures but also their differences, this set of algorithms is a good example to show the effectiveness of a fpga-based modular approach to implement sensorless control induction motor drives. Therefore, the chosen solution is based on a custom hardware architecture designed by assembling a set of building blocks. These blocks are tested and organized in a library of Intellectual Property (IP) modules for easy re-use. Each block is geared toward specific algorithm function (Flux estimator, Hysteresis controller...). Besides, a special attention is given to the algorithm refinement which allows finding the optimum fixed-point data word length. Finally experimental results are shown which validate the proposed approach.

关键词： fpga-based implementation direct torque and stator flux control direct torque and rotor flux control

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A fpga-based implementation of data acquisition and processing for digital protective relays

A FPGA-based implementation of data acquisition and processi...

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4th International Conference on ASIC

作者： Feng, T Zhang, GQ Wang, JH Geng, YS Zhang, H Xi An Jiao Tong Univ Dept Elect Apparatus Xian 710049 Peoples R China

ISBN: (纸本)0780366778

In order to improve the performance of digital protective relay, a data acquisition and processing system based on fpga is designed in VHDL and implemented in this paper. They are foul parts in system: ADC control, 32-point FFT module, frequency counter and power meter. It cans control ADC and multiplexer to sample and convert 16-channel voltage and current signal of power system, process the discrete data with FFT algorithms in real time, measure the system frequency and power. So it can supply the processed data for protective relays and measurement All parts can be implemented in an Altera ACEX EP1k100. Using this system, the protective relays will achieve the good characteristic: high reliability and performance, multi-function, small size and cheap cost.

关键词： relay protection power system relaying power system protection field programmable gate arrays fast Fourier transforms data acquisition analogue-digital conversion power meters power engineering computing application specific integrated circuits digital instrumentation fpga-based implementation data acquisition system data processing system digital protective relay VHDL design ADC control FFT module frequency counter power meter multiplexer control FFT algorithms real time processing Altera ACEX EP1k100

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Design Space Exploration for the implementation of a Predictive Current Controller based on fpga

Design Space Exploration for the Implementation of a Predict...

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23rd IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Martin, Pedro Machado, Osmell Rodriguez, Francisco J. Bueno, Emilio J. Univ Alcala Dept Elect Madrid 28871 Spain

ISBN: (纸本)9780769547688

Predictive algorithms are increasingly being proposed for implementing current controllers in power converters. However, the computational burden associated with this technique has hindered its widespread use compared to classic control schemes. This paper presents a new approach to the implementation of a predictive current controller for a multilevel converter. This approach takes advantage of the computing capability of fpga devices with the aim of speeding up the predictive current controller implementation. A processing element is defined and optimized to evaluate a cost function for each future state of the system.

关键词： fpga-based implementation multilevel converters design space exploration predictive control optimization

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A novel hardware-oriented Kohonen SOM image compression algorithm and its fpga implementation

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JOURNAL OF SYSTEMS ARCHITECTURE 2008年第10期54卷 983-994页

作者： Kurdthongmee, W. Walailak Univ Sch Engn & Resources Management Div Comp Engn Tha Sa La 80160 Nakorn Si Thamm Thailand

Kohonen self-organizing map (K-SOM) has proved to be suitable for lossy compression of digital images. The major drawback of the software implementation of this technique is its very computational intensive task. Fortunately, the structure is fairly easy to convert into hardware processing units executing in parallel. The resulting hardware system, however, consumes much of a microchip's internal resources, i.e. slice registers and look-up table units. This results in utilising more than a single microchip to realize the structure in pure hardware implementation. Previously proposed K-SOM realizations were mainly targetted on implementing on an application specific integrated circuit (ASIC) with low restriction on resource utilization. In this paper, we propose an alternative architecture of K-SOM suitable for moderate density fpgas with acceptable image quality and frame rate. In addition, its hardware architecture and synthesis results are presented. The proposed K-SOM algorithm compromises between the image quality, the frame rate throughput, the fpga's resource utilization and, additionally, the topological relationship among neural cells within the network. The architecture has been proved to be successfully synthesized on a single moderate resource fpga with acceptable image quality and frame rate. (C) 2008 Elsevier B.V. All rights reserved.

关键词： Image quantization Image compression fpga-based implementation Kohonen self-organizing map

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The hardware-based implementation of the colour palette generation stage of a colour image quantization algorithm

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MICROPROCESSORS AND MICROSYSTEMS 2006年第5期30卷 234-249页

作者： Kurdthongmee, W. Walailak Univ Sch Engn & REsources Div Comp Engn Tha Sa La 80160 Nakorn Si Thamm Thailand

Many techniques have been proposed to quantize a digital colour image in order to reduce the representative number of colours to be suitable for presenting on different type of display screens. Most of the techniques are targeted for implementation on a general purpose multitasking computer with low restriction on resource utilization. The drawback of these techniques relies on the fact that they cannot fulfil the requirement of some applications with real-time constraint and limited resources. In this paper, the most suitable algorithm for hardware implementation is reviewed and the details of its implementation and experimentation which is focused on the colour palette generation stage are presented. The implementation given in this paper is for use in construction of colour palette image compression for real-time transferring of video data to an LED display board. It can also be adapted to use as a dedicated computer hardware for other real-time image compression applications. (C) 2006 Elsevier B.V. All rights reserved.

关键词： palette generation image quantization image compression fpga-based implementation

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Bifurcations to bursting and spiking in the Chay neuron and their validation in a digital circuit

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CHAOS SOLITONS & FRACTALS 2020年 141卷 110353-110353页

作者： Xu, Quan Tan, Xiao Zhu, Dong Bao, Han Hu, Yihua Bao, Bocheng Changzhou Univ Sch Informat Sci & Engn Changzhou 213164 Jiangsu Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Automat Engn Nanjing 211106 Peoples R China Univ York Dept Elect Engn York YO10 5DD N Yorkshire England

Due to the great importance of the outward current carried by K+ ions and the inward one by Na+ and Ca(2+)ions in 3-D Chay neuron model, the dynamical behaviors associated with the maximal conductances of K(+)ions channel and mixed Na+-Ca(2+)ions channel are explored for better demonstrating dynamical effects on the electrical activities in this paper. By utilizing some common dynamical exploring methods, the representative electrical activities of bursting and spiking behaviors endowed with the fast-slow structure of the 3-D Chay neuron model are revealed and classified on the dependence of the two maximal conductances. Moreover, the bifurcation mechanisms for periodic fold/fold bursting, periodic and chaotic fold/homoclinic bursting, and chaotic spiking behaviors are expounded qualitatively by fast-slow dynamical analysis with some specified model parameters. Finally, based on a field programmable gate array (fpga), a digitally circuit-implemented electronic neuron is made, from which the chaotic and periodic bursting/spiking behaviors are experimentally captured to confirm the numerical simulations. (C) 2020 Elsevier Ltd. All rights reserved.

关键词： Bifurcation Bursting behavior Chay neuron model fpga-based implementation Spiking behavior

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A novel Kohonen SOM-based image compression architecture suitable for moderate density fpgas

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IMAGE AND VISION COMPUTING 2008年第8期26卷 1094-1105页

作者： Kurdthongmee, W. Walailak Univ Sch Engn & Resources Management Div Comp Engn Tha Sa La 80160 Nakron Si Thamm Thailand

Kohonen self-organizing map (K-SOM) has proved to be suitable for lossy compression of digital images. The main drawback of this technique is that it is a very computationally intensive task if software implementation is performed alone. Fortunately, the structure is fairly easy to convert into parallel processing units. However, it consumes much of a microchip's internal resources and results in utilizing more than a single microchip to realize the structure in pure hardware. Previously proposed K-SOM realizations were mainly targeted on implementing on an ASIC (Application Specific Integrated Circuit) with low restriction on resource utilization. In this paper, we, in contrast, propose a novel architecture of K-SOM which compromises between image quality, frame rate throughput and fpga's resource utilization. The architecture is based on unsigned integer arithmetic in all operations and has been successfully synthesized on a single moderate resource fpga with acceptable image quality and frame rate. (C) 2007 Elsevier B.V. All rights reserved.

关键词： image quantization image compression fpga-based implementation Kohonen self-organizing map

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Multiplier-less VLSI architecture for real-time computation of multi-dimensional convolution

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MICROPROCESSORS AND MICROSYSTEMS 2007年第1期31卷 25-37页

作者： Zhang, Ming Z. Ngo, Hau T. Asari, Vijayan K. Old Dominion Univ Dept Elect & Comp Engn Computat Intelligence & Machine Vis Lab Norfolk VA 23529 USA

A VLSI efficient multiplier-less architecture for real-time computation of multi-dimensional convolution is presented in this paper. The new architecture performs computations in the logarithmic domain by utilizing novel multiplier-less 1092 and inverse-log(2) modules which are capable of converting the fraction numbers currently not available in the literature. An effective data handling strategy is developed in conjunction with the logarithmic modules to eliminate the necessity of multipliers in the architecture. The proposed approach reduces hardware resources significantly compared to other approaches maintaining a high degree of accuracy. The architecture is developed as a combined systolic-pipelined design that produces an output in every clock cycle after an initial latency of 93.19 uSec. The architecture is capable of operating with a clock frequency of 99 MHz based on Xilinx's Virtex II 2v2000ff896-4 fpga and the throughput of the system is observed as 99 MOPS (million outputs per second). Error analysis performed with the fpga-based system in the image processing examples of edge detection and noise filtering shows that the proposed architecture produces outputs similar to that obtained by software simulation using Matlab. (c) 2006 Elsevier B.V. All rights reserved.

关键词： multi-dimensional convolution multiplier-less architecture logarithmic domain computation systolic-pipelines architecture fpga-based implementation

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