检索结果-内蒙古大学图书馆

16th International Conference on Advanced Communication Technology (ICACT)

作者： Yao, Rugui Li, Geng Wang, Ling Bi, Yanbo Chen, Yun Northwestern Polytech Univ Sch Elect & Informat Xian 710072 Shaan Xi Peoples R China

ISBN: (纸本)9788996865032

Frequency-domain anti-jamming (FDAJ) algorithms achieve prominent performance on interference suppression with simple calculations;and hence they are widely used in many applications. The interference suppression threshold plays a key role in the algorithm and affects system performance greatly. In this paper, the initial interference threshold is derived theoretically and then a novel FDAJ algorithm is proposed based on the iterative calculation of the threshold. With the iterative process, the optimal threshold for the interference suppression can be approached with little loss of valid signals;and the anti-jamming performance can be further improved. The simulation results validate well that our proposed iterative algorithm has superior performance for interference suppression. Finally, two fpga-based implementations are presented: pipeline scheme and iterative scheme. After analysing the different characteristics of each implementation, we discuss the suitable applications for these schemes.

关键词： Frequency-domain anti-jamming iterative threshold simulation fpga-based implementation

来源：评论

学校读者我要写书评

暂无评论

Unified time-domain formulation of switching frequency for hysteresis current controlled AC/DC and DC/AC grid connected converters

引用

IET POWER ELECTRONICS 2013年第4期6卷 683-692页

作者： Gautam, Shweta Gupta, Rajesh Motilal Nehru Natl Inst Technol Dept Elect Engn Allahabad 211004 Uttar Pradesh India

This study presents a unified time-domain formulation of switching frequency for hysteresis current controlled AC/DC and DC/AC grid connected converters. It is shown that the generalised expression of switching frequency obtained can be used for any mode of operation of the converter based on phase relation between the reference AC current and grid voltage. The presented analysis provides information of maximum, minimum and average switching frequencies for all modes of the converter operation. The analytical results derived under different configurations are verified through the experimental results obtained using fpga-based implementation of the controller for the converter. The applications of the results are shown on the three different single-phase systems operating in current control mode: (i) static synchronous compensator, (ii) boost rectifier and (iii) grid interface of wind-turbine system. The results of switching operations in these applications are verified using simulation studies performed in power systems CAD/electromagnetic transients including DC (PSCAD/EMTDC) software.

关键词： AC-DC power convertors DC-AC power convertors electric current control field programmable gate arrays hysteresis time-domain analysis switching frequency unified time-domain formulation hysteresis current controlled AC-DC grid connected converters hysteresis current controlled DC-AC grid connected converters phase relation AC current grid voltage maximum switching frequencies minimum switching frequencies average switching frequencies fpga-based implementation single-phase systems static synchronous compensator boost rectifier grid interface wind-turbine system PSCAD-EMTDC software AC-DC power convertors DC-AC power convertors electric current control field programmable gate arrays hysteresis time-domain analysis switching frequency unified time-domain formulation hysteresis current controlled AC-DC grid connected converters hysteresis current controlled DC-AC grid connected converters phase relation AC current grid voltage maximum switching frequencies minimum switching frequencies average switching frequencies fpga-based implementation single-phase systems static synchronous compensator boost rectifier grid interface wind-turbine system PSCAD-EMTDC software

来源：评论

学校读者我要写书评

暂无评论

Design Space Exploration for the implementation of a Predictive Current Controller based on fpga

Design Space Exploration for the Implementation of a Predict...

引用

23rd IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Martin, Pedro Machado, Osmell Rodriguez, Francisco J. Bueno, Emilio J. Univ Alcala Dept Elect Madrid 28871 Spain

ISBN: (纸本)9780769547688

Predictive algorithms are increasingly being proposed for implementing current controllers in power converters. However, the computational burden associated with this technique has hindered its widespread use compared to classic control schemes. This paper presents a new approach to the implementation of a predictive current controller for a multilevel converter. This approach takes advantage of the computing capability of fpga devices with the aim of speeding up the predictive current controller implementation. A processing element is defined and optimized to evaluate a cost function for each future state of the system.

关键词： fpga-based implementation multilevel converters design space exploration predictive control optimization

来源：评论

学校读者我要写书评

暂无评论

fpga-based implementation of DTSFC and DTRFC algorithms

FPGA-based implementation of DTSFC and DTRFC algorithms

引用

31st Annual Conference of the IEEE-Industrial-Electronics-Society

作者： Charaabi, L Monmasson, E Nassani, MA Slama-Belkhodja, I LSE Ecole Natl Ingn Tunis Tunis Tunisia

ISBN: (纸本)0780392523

In this paper, authors present a fpga-based implementation of Direct Torque and Stator Flux Control (DTSFC) and Direct Torque and rotor Flux Control (DTRFC) with and without use of Space Vector Modulation (SVM) for induction motor drives. Indeed, due to their similar structures but also their differences, this set of algorithms is a good example to show the effectiveness of a fpga-based modular approach to implement sensorless control induction motor drives. Therefore, the chosen solution is based on a custom hardware architecture designed by assembling a set of building blocks. These blocks are tested and organized in a library of Intellectual Property (IP) modules for easy re-use. Each block is geared toward specific algorithm function (Flux estimator, Hysteresis controller...). Besides, a special attention is given to the algorithm refinement which allows finding the optimum fixed-point data word length. Finally experimental results are shown which validate the proposed approach.

关键词： fpga-based implementation direct torque and stator flux control direct torque and rotor flux control

来源：评论

学校读者我要写书评

暂无评论

A novel hardware-oriented Kohonen SOM image compression algorithm and its fpga implementation

引用

JOURNAL OF SYSTEMS ARCHITECTURE 2008年第10期54卷 983-994页

作者： Kurdthongmee, W. Walailak Univ Sch Engn & Resources Management Div Comp Engn Tha Sa La 80160 Nakorn Si Thamm Thailand

Kohonen self-organizing map (K-SOM) has proved to be suitable for lossy compression of digital images. The major drawback of the software implementation of this technique is its very computational intensive task. Fortunately, the structure is fairly easy to convert into hardware processing units executing in parallel. The resulting hardware system, however, consumes much of a microchip's internal resources, i.e. slice registers and look-up table units. This results in utilising more than a single microchip to realize the structure in pure hardware implementation. Previously proposed K-SOM realizations were mainly targetted on implementing on an application specific integrated circuit (ASIC) with low restriction on resource utilization. In this paper, we propose an alternative architecture of K-SOM suitable for moderate density fpgas with acceptable image quality and frame rate. In addition, its hardware architecture and synthesis results are presented. The proposed K-SOM algorithm compromises between the image quality, the frame rate throughput, the fpga's resource utilization and, additionally, the topological relationship among neural cells within the network. The architecture has been proved to be successfully synthesized on a single moderate resource fpga with acceptable image quality and frame rate. (C) 2008 Elsevier B.V. All rights reserved.

关键词： Image quantization Image compression fpga-based implementation Kohonen self-organizing map

来源：评论

学校读者我要写书评

暂无评论

A novel Kohonen SOM-based image compression architecture suitable for moderate density fpgas

引用

IMAGE AND VISION COMPUTING 2008年第8期26卷 1094-1105页

作者： Kurdthongmee, W. Walailak Univ Sch Engn & Resources Management Div Comp Engn Tha Sa La 80160 Nakron Si Thamm Thailand

Kohonen self-organizing map (K-SOM) has proved to be suitable for lossy compression of digital images. The main drawback of this technique is that it is a very computationally intensive task if software implementation is performed alone. Fortunately, the structure is fairly easy to convert into parallel processing units. However, it consumes much of a microchip's internal resources and results in utilizing more than a single microchip to realize the structure in pure hardware. Previously proposed K-SOM realizations were mainly targeted on implementing on an ASIC (Application Specific Integrated Circuit) with low restriction on resource utilization. In this paper, we, in contrast, propose a novel architecture of K-SOM which compromises between image quality, frame rate throughput and fpga's resource utilization. The architecture is based on unsigned integer arithmetic in all operations and has been successfully synthesized on a single moderate resource fpga with acceptable image quality and frame rate. (C) 2007 Elsevier B.V. All rights reserved.

关键词： image quantization image compression fpga-based implementation Kohonen self-organizing map

来源：评论

学校读者我要写书评

暂无评论

Multiplier-less VLSI architecture for real-time computation of multi-dimensional convolution

引用

MICROPROCESSORS AND MICROSYSTEMS 2007年第1期31卷 25-37页

作者： Zhang, Ming Z. Ngo, Hau T. Asari, Vijayan K. Old Dominion Univ Dept Elect & Comp Engn Computat Intelligence & Machine Vis Lab Norfolk VA 23529 USA

A VLSI efficient multiplier-less architecture for real-time computation of multi-dimensional convolution is presented in this paper. The new architecture performs computations in the logarithmic domain by utilizing novel multiplier-less 1092 and inverse-log(2) modules which are capable of converting the fraction numbers currently not available in the literature. An effective data handling strategy is developed in conjunction with the logarithmic modules to eliminate the necessity of multipliers in the architecture. The proposed approach reduces hardware resources significantly compared to other approaches maintaining a high degree of accuracy. The architecture is developed as a combined systolic-pipelined design that produces an output in every clock cycle after an initial latency of 93.19 uSec. The architecture is capable of operating with a clock frequency of 99 MHz based on Xilinx's Virtex II 2v2000ff896-4 fpga and the throughput of the system is observed as 99 MOPS (million outputs per second). Error analysis performed with the fpga-based system in the image processing examples of edge detection and noise filtering shows that the proposed architecture produces outputs similar to that obtained by software simulation using Matlab. (c) 2006 Elsevier B.V. All rights reserved.

关键词： multi-dimensional convolution multiplier-less architecture logarithmic domain computation systolic-pipelines architecture fpga-based implementation

来源：评论

学校读者我要写书评

暂无评论

The hardware-based implementation of the colour palette generation stage of a colour image quantization algorithm

引用

MICROPROCESSORS AND MICROSYSTEMS 2006年第5期30卷 234-249页

作者： Kurdthongmee, W. Walailak Univ Sch Engn & REsources Div Comp Engn Tha Sa La 80160 Nakorn Si Thamm Thailand

Many techniques have been proposed to quantize a digital colour image in order to reduce the representative number of colours to be suitable for presenting on different type of display screens. Most of the techniques are targeted for implementation on a general purpose multitasking computer with low restriction on resource utilization. The drawback of these techniques relies on the fact that they cannot fulfil the requirement of some applications with real-time constraint and limited resources. In this paper, the most suitable algorithm for hardware implementation is reviewed and the details of its implementation and experimentation which is focused on the colour palette generation stage are presented. The implementation given in this paper is for use in construction of colour palette image compression for real-time transferring of video data to an LED display board. It can also be adapted to use as a dedicated computer hardware for other real-time image compression applications. (C) 2006 Elsevier B.V. All rights reserved.

关键词： palette generation image quantization image compression fpga-based implementation

来源：评论

学校读者我要写书评

暂无评论

A fpga-based implementation of data acquisition and processing for digital protective relays

A FPGA-based implementation of data acquisition and processi...

引用

4th International Conference on ASIC

作者： Feng, T Zhang, GQ Wang, JH Geng, YS Zhang, H Xi An Jiao Tong Univ Dept Elect Apparatus Xian 710049 Peoples R China

ISBN: (纸本)0780366778

In order to improve the performance of digital protective relay, a data acquisition and processing system based on fpga is designed in VHDL and implemented in this paper. They are foul parts in system: ADC control, 32-point FFT module, frequency counter and power meter. It cans control ADC and multiplexer to sample and convert 16-channel voltage and current signal of power system, process the discrete data with FFT algorithms in real time, measure the system frequency and power. So it can supply the processed data for protective relays and measurement All parts can be implemented in an Altera ACEX EP1k100. Using this system, the protective relays will achieve the good characteristic: high reliability and performance, multi-function, small size and cheap cost.

关键词： relay protection power system relaying power system protection field programmable gate arrays fast Fourier transforms data acquisition analogue-digital conversion power meters power engineering computing application specific integrated circuits digital instrumentation fpga-based implementation data acquisition system data processing system digital protective relay VHDL design ADC control FFT module frequency counter power meter multiplexer control FFT algorithms real time processing Altera ACEX EP1k100

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：