This paper presents a design methodology for the fpga-based simulation of the Universal Line Model (ULM). The proposed approach yields a higher computational performance compared to alternative implementations reporte...
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This paper presents a design methodology for the fpga-based simulation of the Universal Line Model (ULM). The proposed approach yields a higher computational performance compared to alternative implementations reported in the literature. Such performance allows the use of the fpga model in real-time simulation applications or for the acceleration of offline EMT programs. A state-space approach is used to perform the time domain simulation of the pole-residue form of the rational fitting of the characteristic admittance and propagation functions. The paper also discusses the appropriate scheduling of the ULM computations and proper management of the history terms that lead to an optimized hardware utilization, low latency response times, and higher computational performances using floating-point arithmetic.
The simulation models of power electronic converters and power systems may be reused for rapid prototyping, prototype testing and type approval. Such models already run on real-time simulators (RTS) of various supplie...
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ISBN:
(纸本)9798350346893
The simulation models of power electronic converters and power systems may be reused for rapid prototyping, prototype testing and type approval. Such models already run on real-time simulators (RTS) of various suppliers, on fpga- basedsimulation platforms. The target is to solve many more applications with the same hardware (HW) in a faster way by decoupling the application from the power electronics. Therefore, it is a goal to adapt existing DC sources by adding a high-speed fiber interface to decouple the application from the power electronics. One common interface specification enables the use of a wide range of products as power amplifiers (battery/cell emulators & testers, machine emulators, dyno drives, universal inverters, grid emulators). An interchangeable fiber optic interface between different RTS platforms will be used to provide low latency and synchronization concepts.
Electrification significantly increases the complexity of aerospace electric power systems (EPS), as there is a transition from conventional aircraft to more electric aircraft (MEA) and all electric aircraft (AEA) [1]...
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ISBN:
(纸本)9798350346893
Electrification significantly increases the complexity of aerospace electric power systems (EPS), as there is a transition from conventional aircraft to more electric aircraft (MEA) and all electric aircraft (AEA) [1]. This publication shows a novel method to use Power Hardware-in-the-Loop (PHIL) based inverter emulator (PHIL-IE) as an efficient test tool along the product life cycle. In early R&D phase the PHIL-IE can already fully emulate the future target inverter with full power under real life conditions. The same PHIL-IE with a modified HIL model can be used to test the target inverter. Finally, the PHIL-IE with a more complex HIL model can function as test unit to emulate batteries, H-2-Systems, machines and more within an iron bird. In addition, this method is perfectly suitable for co-simulations of real electric components and digital twins.
Error-resilient designs have become more important with the continued device scaling. One critical challenge of designing error-resilient systems is the lack of tools to quickly and accurately evaluate the effectivene...
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ISBN:
(纸本)9781450318877
Error-resilient designs have become more important with the continued device scaling. One critical challenge of designing error-resilient systems is the lack of tools to quickly and accurately evaluate the effectiveness and performance of such systems. We propose an fpga-based transient error simulator to accelerate transient error simulations incorporating accurate datapath delay models and realistic error models. Compared to conventional digital error simulators, the fpga-based transient error simulator operates at a finer time step and captures intricate interactions between errors and datapath under different circuit-level error detection and correction techniques. The error simulator is constructed using configurable datapath delay model and error model, making it general-purpose and widely applicable. We demonstrate the capability of this simulator in the evaluation of two popular error-resilient design techniques, pre-edge and post-edge detection and correction, using a synthesized CORDIC processor and an Alpha processor that operate under soft error, coupling noise and voltage droop models. The proposed error simulator uncovers insights to guide practical designs, including the choice of checking window in pre-edge designs and the optimal operating frequency in post-edge designs. The fpga-based transient simulation will complement circuit simulation and system emulation for resilient system designs.
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