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A novel s-box generation method based on metastable inducing over FPGA for block ciphers

KNOWLEDGE-BASED SYSTEMS 2025年 310卷

作者： Garipcan, Ali Murat Aydin, Yilmaz Ozkaynak, Fatih Munzur Univ Dept Comp Engn Tunceli Turkiye Firat Univ Dept Software Engn Elazig Turkiye

Substitution boxes (s-boxes) providing the nonlinearity property are fundamental components of modern encryption systems. The security of these systems directly depends on the quality of the s-boxes ensuring a high level of resistance to advanced attacks. Although there is no perfect method in the literature, improving the cryptographic properties of s-boxes, such as nonlinearity and differential independence remains an important area of interest for many researchers. In this paper, we propose a new s-box generation method based on the reinforcement of the randomness obtained from the metastable states of the R-S latch. In the proposed method, a field programmable gate array (FPGA) chip is used to obtain design inputs based on physical reality obtained from the hardware level. Design inputs with poor statistical adequacy are transformed into s-boxes by passing them through four different hash functions (Blake2b, Blake2 s, SHA3 and Shake). A total of 333,328 s-boxes are generated with the proposed method for four different scenarios and widely used evaluation metrics such as bijectivity, nonlinearity (NL), strict avalanche criteria (SAC), bit independence criteria (BIC), differential probability (DP) and linear probability (LP) are considered for the analysis. Taking into account these metric values, the study also presents a detailed performance comparison of the proposed s-boxes with recent studies from the last 5 years in the literature. The fact that the nonlinearity degree of 75 % of the produced s-boxes is higher than 103, which is the average limit value in the literature, also confirms the method's efficiency, proven reliable by the analysis results. When all these results are evaluated together, they confirm that the proposed method is highly effective in generating robust s-boxes and that these s-boxes can be reliably used in modern cryptographic systems.

关键词： Substitution box Block ciphers Cryptography Hash functions field programmable gate array

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True random calibration method and application of tapped delay line-TDC with spontaneous parametric down-conversion system

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MEASUREMENT 2025年 251卷

作者： Jin, Zhihan Yu, Bing Chu, Junwei Kang, Qing Li, Jianjun Chinese Acad Sci Hefei Inst Phys Sci Anhui Prov Key Lab Opt Quantitat Remote Sensing Hefei 230031 Anhui Peoples R China Univ Sci & Technol China Hefei 230026 Anhui Peoples R China Xian Inst Appl Opt Xian 710065 Shanxi Peoples R China

The paper proposes a true random calibration method for field programmable gate array (FPGA) based tapped delay line (TDL)-time-to-digital converters (TDCs), which is suitable for spontaneous parametric downconversion (SPDC) systems. The Poisson distribution of single-photon detector (SPD) signals based on a Geiger-mode avalanche photodiode (GM-APD) in the SPDC system makes the SPD function as both a detection device and a quantum random pulse generator (QRPG), which can be used for the true random code density calibration of TDL-TDCs to obtain the nonlinear calibration factors. This method neither adds any system modules nor disrupts the measurement process. Instead, it improves the timeliness of TDL-TDC bin-width calibration in measurement environments featuring significant ambient variations, making it applicable to long-term continuous measurements and reducing measurement uncertainty.

关键词： Single-photon detector Quantum random pulse generator Time-to-digital converter field programmable gate array Calibration Code density test

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A framework for detecting high-performance cardiac arrhythmias using deep inference engine on FPGA and higher-order spectral distribution

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MECHANICAL SYSTEMS AND SIGNAL PROCESSING 2025年 228卷

作者： Karthikeyani, S. Sasipriya, S. Ramkumar, M. Sri Krishna Coll Engn & Technol Dept Elect & Commun Engn Coimbatore 641008 India

Cardiac arrhythmias (CA) are critical health conditions. In such a case, highly accurate detection leads to better management and, therefore, better treatment. Here, this paper presents a novel high-performance detection framework for cardiac arrhythmias based on advanced signal processing algorithms with deep learning on a field programmable gate array (FPGA) towards achieving real-time performances and even higher accuracy. ECG signals are initially analyzed by using compressive sensing theory to obtain sparsity, and from that, the adaptive compressive sensing framework is created. This compressive sensing framework adapts the sensing matrix step by step through compression via the Hybrid Reptile Search Algorithm integrated with the Garra Rufa Algorithm (Hyb-RSA-GRA). The adapted sensing matrix renders signal reconstruction efficient through Bayesian Regularization-Backpropagation Neural Network (BRBNN). The new arrhythmia detection framework employs the possibility of higher-order spectral distribution (HoSD) in extracting finer patterns from ECGs that describe arrhythmia. The task of classification uses a pre-trained Graph Convolutional Neural Network (GCNN) acting as a Deep Inference Engine on the FPGA to support real-time, robust identification of the type of arrhythmias such as N (normal beat), S (supraventricular ectopic beat), V (ventricular ectopic beat), F (fusion beat), and U (unidentified beat). The proposed FPGA implementation reveals better performance with high accuracy, sensitivity, specificity, precision, recall, and F1-score with optimized power dissipation, resource utilization, and delay metrics. Furthermore, the compressive sensing framework guarantees low MSE, reduced RMSE, high SNR, and an improved reconstruction probability. All the above results demonstrate the capability of the framework in accurate prediction and hardware efficiency, hence making it a robust solution for cardiac arrhythmia detection.

关键词： Cardiac arrhythmia field programmable gate array Electrocardiograms ECG sparsity Deep learning Deep inference engine

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Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2025年第5期34卷

作者： Behera, Niharika Pradhan, Manoranjan Bhoi, Bandan Kumar Veer Surendra Sai Univ Technol Dept Elect & Telecommun Engn Burla India

Computing the square of any large signed number using conventional methods is challenging. Therefore, parallel and partial product generation while squaring signed numbers is complex and time-consuming. This paper suggests a very large scale integration design for an efficient signed square architecture using a nonconventional method. The square of a large magnitude signed number is reduced to a lower magnitude signed multiplication and an addition operation by the Yavadunam algorithm. The suggested method finds the deficit of the signed number from the adjacent base to perform the signed square operation. The proposed design is coded using Verilog hardware description language. The synthesis and simulation of this architecture are performed using Xilinx integrated synthesis environment 14.7 software. Furthermore, this architecture is implemented on the Virtex-4, spartan-3 and spartan-6 field programmable gate array devices. The design is also coded in cadence virtuoso centos version 5. Then, it is synthesized using 180nm and 90nm technology. The validation of the proposed architecture is examined using the performance parameters, such as path delay and area. The synthesis results show improvements in delay-area complexity compared to state-of-the-art architectures. The superiority of the proposed architecture is claimed based on performance comparisons with the previous square, multipliers and signed multiplier architectures.

关键词： Signed multiplier square architecture computer arithmetic field programmable gate array Yavadunam algorithm

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Windowed Sliding DFT Structure for Integrated Resistance and Capacitance Sensing With Wider Sensing Range

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Tiwari, Ranjan Parasuraman, Sumathi Indian Inst Technol Roorkee Dept Elect Engn Roorkee 247667 Uttarakhand India

This article presents an integrated frequency domain measurement system for resistance (R) and capacitance (C) sensing. The proposed software and hardware combination achieves one of the largest R and C measurement ranges in the literature. A simple analog front-end circuit with a relaxation oscillator is designed to toggle between resistive and capacitive sensing. This oscillator accommodates the sensing variable (R or C) and converts this parameter change into the corresponding change in frequency of square wave output. A novel 2-in-1 Hanning and Blackman window-based FLL is designed to track the input square wave signal frequency. The proposed integrated measurement system contains two measuring units in a single system-on-chip, designed and implemented on an FPGA. Therefore, two types of measurements such as humidity measurement (C) and temperature measurement (R) are possible with a single instrument. Further, the windowed SDFT incorporation in a frequency-locked loop offers a wide capacitive and resistive measurement range. The range of R measurement is found to be ( 150 Omega -21.5 M Omega ) +/- 0.2% with an error of 0.023% +/- 0.53% while the same for C measurement is (3.4 pF-507.8 nF) +/- 0.5% and 0.038% +/- 0.53% . The proposed measurement system is also validated through the measurement of temperature from (30 degrees C to 90 degrees C) +/- 0.1% and humidity in the range of (40%RH-90%RH) +/- 4% separately.

关键词： Capacitance measurement field programmable gate array humidity sensor integrated measurement resistance measurement sensor interfacing circuit temperature sensor windowed sliding discrete Fourier transform (DFT) Capacitance measurement field programmable gate array humidity sensor integrated measurement resistance measurement sensor interfacing circuit temperature sensor windowed sliding discrete Fourier transform (DFT)

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Line-by-Line Computation of Atmospheric Infrared Spectra With field programmable gate arrays

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IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2011年第3期4卷 701-709页

作者： Kohlert, Dieter Schreier, Franz Regensburg Univ Appl Sci Dept Elect Engn D-93053 Regensburg Germany DLR German Aerosp Ctr Remote Sensing Technol Inst D-82234 Wessling Germany

Radiative transfer modelling of high resolution infrared (or microwave) spectra still represents a major challenge for the processing of atmospheric remote sensing data despite significant advances in the numerical techniques utilized in line-by-line modelling by, e. g., optimized Voigt function algorithms or multigrid approaches. Special purpose computing hardware such as field programmable gate arrays (FPGAs) can be used to cope with the dramatic increase of data quality and quantity. Utilizing a highly optimized implementation of an uniform rational function approximation of the Voigt function, the molecular absorption cross section computation-representing the most compute intensive part of radiative transfer codes-has been realized on FPGA. Design and implementation of the FPGA coprocessor is presented along with first performance tests and an outlook for the ongoing further development.

关键词： Atmospheric radiative transfer field programmable gate array FPGA infrared microwave molecular absorption

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A VARIABLE-PRECISION SQUARE-ROOT IMPLEMENTATION FOR field-programmable gate arrayS

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JOURNAL OF SUPERCOMPUTING 1995年第3期9卷 315-336页

作者： LOUIE, ME ERCEGOVAC, MD Computer Science Department University of California Los Angeles

Applications requiring variable-precision arithmetic often rely on software implementations because custom hardware is either unavailable or too costly to build. By using the flexibility of the Xilinx XC4010 field programmable gate arrays, we present a hardware implementation of square root that is easily tailored to any desired precision. Our design consists of three types of modules: a control logic module, a data path module to extend the precision in 4-bit increments, and an interface module to span multiple chips. Our data path design avoids the common problem of large fan-out delay in the critical path. Cycle time is independent of precision, and operation latency can be independent of interchip communication delays.

关键词： SQUARE ROOT field programmable gate array FPGA VARIABLE PRECISION HIGH PRECISION

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Invited: Innovation in Times of Technology Disruption 25

Invited: Innovation in Times of Technology Disruption

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Proceedings of the 2025 International Symposium on Physical Design

作者： Bryan Preas Technology Consulting Battle Ground WA USA

ISBN: (纸本)9798400712937

I hosted Jason Cong when he was an intern at the Xerox Palo Alto Research Center in 1987. Since then, we have been friends and collaborators. I have watched his extraordinary accomplishments with pride and pleasure over the *** technologies are a well-studied business school topic. New, or significantly improved, technologies present new problems and allow new approaches for older challenges. These disruptions are often accompanied by substantial technical innovation and creation of new business values. In their time, electric power, automobiles and television disrupted society. More recent examples include the internet and e-commerce.

关键词： field programmable gate array

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Technology mapping for field programmable gate arrays using Content-Addressable Memory (CAM)

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MICROPROCESSORS AND MICROSYSTEMS 2006年第7期30卷 445-456页

作者： Lucas, Joshua M. Hoare, Raymond Kourtev, Ivan S. Jones, Alex K. Univ Pittsburgh Dept Elect & Comp Engn Pittsburgh PA 15261 USA Univ Pittsburgh Dept Comp Sci Pittsburgh PA 15261 USA

The growing complexity of field programmable gate arrays (FPGA's) is leading to architectures with high input cardinality look-up tables (LUT's). This paper describes a methodology for area-optimal combinational technology mapping, specifically designed for such FPGA architectures. This methodology, called LURU, leverages the parallel search capabilities of Content-Addressable Memories (CAM's) to outperform traditional mapping algorithms in both execution time and quality of results. The LURU algorithm is fundamentally different from other techniques for technology mapping in that LURU uses textual representations of circuit topology in order to efficiently store and search for circuit patterns in a CAM. A circuit is mapped to the target LUT technology using exact, inexact, or hybrid matching techniques. Common subcircuit expressions (CSE's) are also identified and used for architectural optimization-a small set of CSE's is shown to effectively cover an average of 96% of the test circuits. LURU was tested with the ISCAS '85 suite of combinational benchmark circuits and compared with the mapping algorithms FlowMap and CutMap. The area requirement of LURU's mapping is, on average, 20% less than FlowMap or CutMap. The asymptotic runtime complexity of LURU is shown to be better than that of both FlowMap and CutMap. (C) 2006 Elsevier B.V. All rights reserved.

关键词： technology mapping CAM Content-Addressable Memory FPGA field programmable gate array

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Multiplicative finite impulse response filters: implementations and applications using field programmable gate arrays

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IET SIGNAL PROCESSING 2015年第5期9卷 449-456页

作者： Vandenbussche, Jean-Jacques Lee, Peter Peuteman, Joan Katholieke Univ Leuven KU Leuven Kulab Dept ESAT Fac Engn Technol Louvain Belgium Univ Kent Sch Engn & Digital Arts Canterbury CT2 7NT Kent England

This paper describes how modern field programmable gate array (FPGA) technology can be used to build practical and efficient multiplicative finite impulse response (MFIR) filters with low-pass, high-pass, band-pass and band-stop characteristics. This paper explains how MFIR structures can be built with or without linear phase characteristics and implemented efficiently on modern FPGA architectures using fixed-point arithmetic without incurring stability problems or limit cycles which commonly occur when using equivalent infinite impulse response structures. These properties have a particular importance for applications such as tunable resonators, narrow band rejectors and linear phase filters which have demanding, narrow transition band requirements. The results presented in this paper indicate that MFIR filters are, for some applications, a viable alternative to existing filter structures when implemented on an FPGA.

关键词： field programmable gate arrays FIR filters low-pass filters high-pass filters band-pass filters band-stop filters linear phase filters IIR filters multiplicative finite impulse response filter MFIR filter field programmable gate array low-pass characteristics band-stop characteristics high-pass characteristics band-pass characteristics linear phase characteristics modern FPGA architecture fixed-point arithmetic equivalent infinite impulse response structures

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