I hosted Jason Cong when he was an intern at the Xerox Palo Alto Research Center in 1987. Since then, we have been friends and collaborators. I have watched his extraordinary accomplishments with pride and pleasure ov...
详细信息
ISBN:
(纸本)9798400712937
I hosted Jason Cong when he was an intern at the Xerox Palo Alto Research Center in 1987. Since then, we have been friends and collaborators. I have watched his extraordinary accomplishments with pride and pleasure over the *** technologies are a well-studied business school topic. New, or significantly improved, technologies present new problems and allow new approaches for older challenges. These disruptions are often accompanied by substantial technical innovation and creation of new business values. In their time, electric power, automobiles and television disrupted society. More recent examples include the internet and e-commerce.
The growing complexity of field programmable gate arrays (FPGA's) is leading to architectures with high input cardinality look-up tables (LUT's). This paper describes a methodology for area-optimal combination...
详细信息
The growing complexity of field programmable gate arrays (FPGA's) is leading to architectures with high input cardinality look-up tables (LUT's). This paper describes a methodology for area-optimal combinational technology mapping, specifically designed for such FPGA architectures. This methodology, called LURU, leverages the parallel search capabilities of Content-Addressable Memories (CAM's) to outperform traditional mapping algorithms in both execution time and quality of results. The LURU algorithm is fundamentally different from other techniques for technology mapping in that LURU uses textual representations of circuit topology in order to efficiently store and search for circuit patterns in a CAM. A circuit is mapped to the target LUT technology using exact, inexact, or hybrid matching techniques. Common subcircuit expressions (CSE's) are also identified and used for architectural optimization-a small set of CSE's is shown to effectively cover an average of 96% of the test circuits. LURU was tested with the ISCAS '85 suite of combinational benchmark circuits and compared with the mapping algorithms FlowMap and CutMap. The area requirement of LURU's mapping is, on average, 20% less than FlowMap or CutMap. The asymptotic runtime complexity of LURU is shown to be better than that of both FlowMap and CutMap. (C) 2006 Elsevier B.V. All rights reserved.
This paper describes how modern field programmable gate array (FPGA) technology can be used to build practical and efficient multiplicative finite impulse response (MFIR) filters with low-pass, high-pass, band-pass an...
详细信息
This paper describes how modern field programmable gate array (FPGA) technology can be used to build practical and efficient multiplicative finite impulse response (MFIR) filters with low-pass, high-pass, band-pass and band-stop characteristics. This paper explains how MFIR structures can be built with or without linear phase characteristics and implemented efficiently on modern FPGA architectures using fixed-point arithmetic without incurring stability problems or limit cycles which commonly occur when using equivalent infinite impulse response structures. These properties have a particular importance for applications such as tunable resonators, narrow band rejectors and linear phase filters which have demanding, narrow transition band requirements. The results presented in this paper indicate that MFIR filters are, for some applications, a viable alternative to existing filter structures when implemented on an FPGA.
field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gatearrays, Hierarchical interconnection structures for field programmable gate arrays are proposed, They ...
详细信息
field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gatearrays, Hierarchical interconnection structures for field programmable gate arrays are proposed, They help overcome these problems, Logic blocks in a held programmablegatearray are grouped into clusters, Clusters are then recursively grouped together, To obtain the optimal hierarchical structure with high performance and high density, various hierarchical structures with the same routability are discussed, The held programmablegatearrays with new architecture can be efficiently configured with existing computer aided design algorithms, The k-way min-cut algorithm is applicable to the placement step in the implementation. Global routing paths in a field programmable gate array can be obtained easily. The placement and global routing steps can be performed simultaneously, Experiments on benchmark circuits show that density and performance are significantly improved.
We present a test methodology for estimating system error rates of field programmable gate arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which ...
详细信息
We present a test methodology for estimating system error rates of field programmable gate arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilinx Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.
This study provides an application-specific integrated circuit (ASIC) diagram of Artificial Neural Networks (ANN) with module design for 32-bit floating point operations on field programmable gate array (FPGA). It is ...
详细信息
ISBN:
(纸本)9781728128689
This study provides an application-specific integrated circuit (ASIC) diagram of Artificial Neural Networks (ANN) with module design for 32-bit floating point operations on field programmable gate array (FPGA). It is aimed that ANNs train operations are moved from software to hardware and calculations are made by using IEEE 754 single precision floating point number format. The proposed architecture is designed with combination of Verilog and Very High Speed Integrated Circuits Hardware Description Language (VHDL). Sigmoidal non-linear function was used as the activation function of the train and look-up table (LUT) was created for process efficiency of the designed circuit. Natural parallelisms were used in the calculation of the operations, which are implemented on FPGA, thus the system operations was accelerated by performing independent operations during the same clock cycle. The results obtained from FPGA were compared with the results obtained from MATLAB R2016b.
We present a test methodology for estimating system error rates of field programmable gate arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which ...
详细信息
We present a test methodology for estimating system error rates of field programmable gate arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilinx Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.
The charpy impact is a technique used to evaluate the toughness of an engineering material that determines the amount of energy absorbed by it during fracture. Initially, measurements were estimated manually and later...
详细信息
ISBN:
(纸本)9780819473301
The charpy impact is a technique used to evaluate the toughness of an engineering material that determines the amount of energy absorbed by it during fracture. Initially, measurements were estimated manually and later replaced by a PC version. This study reports the development of the field programmable gate array (FPGA) portable version. The FPGA based version allows easy analysis of samples without the need of sending them to a, lab for analysis. The process, presented here,as the original, is based on measuring the percent of crystal in the test sample after impact, to determine if the material is ductile or brittle. The FPGA version, adapted under the MATLAB Simulink environment, shows a graphical block representation of the charpy impact PC version. An important asset of the FPGA version is its portability, it has to be easily modified and downloaded onto a device to estimate the percent of brittle fracture of the broken Charpy surface. The beauty of the DSP Builder programme is that it allows the model to be compiled to various types of optimise code for any Altera FPCA device. To provide a firm basis for scientific comparison to the new FPGA system, images already analysed via the PC based Java system were also used for testing and comparison purposes. The FPGA system converts the image into an 8 bit grayscale image and analyses it in a 5x5 sampling window. This produces texture features that can be used in a comparison system, similar to the Support Vector Machine (SVM) used in the original. The output is a signal that, states the material being tested is brittle or not via, an output of '1' for brittle and a '0' for ductile. A detailed pixel by pixel analysis of the various output images is then investigated to state the percentage difference between the PC and FPGA based systems.
The Total Ionizing Dose (TID) tolerance of some FPGAs and memory devices has been evaluated. Two FPGAs and five memories of various types and technologies have been irradiated. Results show that the total dose toleran...
详细信息
ISBN:
(纸本)9781509002320
The Total Ionizing Dose (TID) tolerance of some FPGAs and memory devices has been evaluated. Two FPGAs and five memories of various types and technologies have been irradiated. Results show that the total dose tolerance of the tested FPGAs is around 200 Gy. The SRAM is the most tolerant device with a failure dose level over 2.4 kGy. Two Flash memories were still well-functioning after 1 kGy.
field programmable gate arrays (FPGAs) are a popular platform for evolving digital circuits. FPGAs allow to be reconfigured partially which provides a natural way of establishing candidate solutions. Recent research f...
详细信息
ISBN:
(纸本)9781479944798
field programmable gate arrays (FPGAs) are a popular platform for evolving digital circuits. FPGAs allow to be reconfigured partially which provides a natural way of establishing candidate solutions. Recent research focuses on the hardware implementation of evolutionary design platforms. Several approaches have been developed for effective establishment and evaluation of candidate solutions in FPGAs. In this paper a new mutation operator is proposed for evolutionary algorithms. The chromosome representing the candidate solution is mutated in such a way that only one configuration frame is required for establishing the mutated candidate solution in hardware. The experimental results confirm that the reduced number of configuration frames and mutations at lower level of granularity ensure faster evolution, generation of more candidate solutions in a given time as well as solutions with better quality.
暂无评论