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作者： Billian, Bruce Virginia Tech | University

The Frequency Disturbance Recorder (FDR) is a specialized data acquisition device designed to monitor fluctuations in the overall power system. The device is designed such that it can be attached by way of a standard wall power outlet to the power system. These devices then transmit their calculated frequency data through the public internet to a centralized data management and storage server.

By distributing a number of these identical systems throughout the three major North American power systems, Virginia Tech has created a Frequency Monitoring Network (FNET). The FNET is composed of these distributed FDRs as well as an Information Management Server (IMS). Since frequency information can be used in many areas of power system analysis, operation and control, there are a great number of end uses for the information provided by the FNET system. The data provides researchers and other users with the information to make frequency analyses and comparisons for the overall power system. Prior to the end of 2004, the FNET system was made a reality, and a number of FDRs were placed strategically throughout the United States.

The purpose of this thesis is to present the elements of a new generation of FDR hardware design. These elements will enable the design to be more flexible and to lower reliance on some vendor specific components. Additionally, these enhancements will offload most of the computational processing required of the system to a commodity PC rather than an embedded system solution that is costly in both development time and financial cost. These goals will be accomplished by using a field programmable gate array (FPGA), a commodity off-the-shelf personal computer, and a new overall system design.

关键词： Frequency Disturbance Recorder FDR FNET field programmable gate array FPGA Frequency Monitoring Network Time Synchronization Power System Monitoring Thesis

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Optical Multi-Context Blind Scrubbing for field programmable gate arrays

IEEE PHOTONICS JOURNAL

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IEEE PHOTONICS JOURNAL 2020年第6期12卷 1页

作者： Takaki, Yusuke Watanabe, Minoru Shizuoka Univ Grad Sch Integrated Sci & Technol 3-5-1 Johoku Hamamatsu Shizuoka 4328561 Japan

This paper presents aproposal of a new optical multi-context blind scrubbing that can not only increase the soft-error tolerance of the configuration memory of field programmable gate arrays (FPGAs) but also support high-speed dynamic reconfiguration suitable for accelerating FPGA operations. The optical multi-context blind scrubbing operation uses a holographic memory as a soft-error free radiation-hardened external memory. It exploits its two-dimensional large-bandwidth optical bus. Optical multi-context blind scrubbing operation was demonstrated with four configuration contexts. The soft-error tolerance of the scrubbing operation was evaluated using a radiation tolerance experiment using two 4-MBq Americium-241 alpha particle sources. Results show the worst case mean time to repair (MTTR) of the scrubbing operation as 560 ns, which can realize sufficient soft-error tolerance in radiation-rich space environments.

关键词： field programmable gate arrays Logic gates Holography Holographic optical components Optical imaging Adaptive optics High-speed optical techniques field programmable gate array holography optical scrubbing optoelectronic device

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Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in field programmable gate arrays: An Experimental Case Study

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ENERGIES 2018年第4期11卷 739页

作者： Conti, Vincenzo Rundo, Leonardo Billeci, Giuseppe Dario Militello, Carmelo Vitabile, Salvatore Univ Enna KORE Fac Engn & Architecture I-94100 Enna Italy Univ Milano Bicocca Dept Informat Syst & Commun DISCo I-20126 Milan Italy CNR Italian Natl Res Council Inst Mol Bioimaging & Physiol IBFM I-90015 Cefalu Italy Univ Palermo Dept Biopathol & Med Biotechnol DIBIMED I-90133 Palermo Italy

Both computational performances and energy efficiency are required for the development of any mobile or embedded information processing system. The Internet of Things (IoT) is the latest evolution of these systems, paving the way for advancements in ubiquitous computing. In a context in which a large amount of data is often analyzed and processed, it is mandatory to adapt node logic and processing capabilities with respect to the available energy resources. This paper investigates under which conditions a partially reconfigurable hardware accelerator can provide energy saving in complex processing tasks. The paper also presents a useful analysis of how the dynamic partial reconfiguration technique can be used to enable energy efficiency in a generic IoT node that exploits a field programmable gate array (FPGA) device. Furthermore, this work introduces a hardware infrastructure and new energy metrics tailored for the energy efficiency evaluation of the dynamic partial reconfiguration process in embedded FPGA based devices. Exploiting the ability of reconfiguring circuit portions at runtime, the latest generation of FPGAs can be used to foster a better balance between energy consumption and performance. More specifically, the design methodology for the implemented digital signal processing application was adapted for the ZedBoard. To this aim, a case study of a video filtering system is proposed and analyzed by dynamically loading three different hardware filters from the management software running on a Linux-based device. With more details, the presented analytical framework allows for a direct comparison between the energy efficiency of a dynamic partially reconfigurable device and a static non-reconfigurable one. The estimated timing conditions that allow the dynamic partially reconfigurable process to achieve relevant energy efficiency with respect to the corresponding static architecture are also outlined.

关键词： energy efficiency dynamic partial reconfiguration field programmable gate array digital signal processing video filtering

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FPGA based digital phase-coding quantum key distribution system

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Science China(Physics,Mechanics & Astronomy) 2015年第12期58卷 153-159页

作者： LU XiaoMing Zhang LiJun WANG YongGang CHEN Wei HUANG DaJun LI Deng WANG Shuang HE DeYong YIN ZhenQiang ZHOU Yu HUI Cong HAN ZhengFu Department of Modern Physics University of Science and Technology of China Key Laboratory of Quantum Information University of Science and Technology of China Synergetic Innovation Center of Quantum Information & Quantum Physics University of Science and Technology of China Chinese Academy of Sciences

Quantum key distribution （QKD） is a technology with the potential capability to achieve information-theoretic security. Phase- coding is an important approach to develop practical QKD systems in fiber channel. In order to improve the phase-coding modulation rate, we proposed a new digital-modulation method in this paper and constructed a compact and robust prototype of QKD system using currently available components in our lab to demonstrate the effectiveness of the method. The system was deployed in laboratory environment over a 50 km fiber and continuously operated during 87 h without manual interaction. The quantum bit error rate （QBER） of the system was stable with an average value of 3.22% and the secure key generation rate is 8.91 kbps. Although the modulation rate of the photon in the derno system was only 200 MHz, which was limited by the Faraday- Michelson interferometer （FMI） structure, the proposed method and the field programmable gate array （FPGA） based electronics scheme have a great potential for high speed QKD systems with Giga-bits/second modulation rate.

关键词： quantum key distribution phase-coding digital phase modulation field programmable gate array Faraday-Michelsoninterferometer

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Total Ionizing Dose Effect and Failure Mechanism of Digital Signal Processor

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Chinese Journal of Electronics 2021年第5期30卷 986-990页

作者： YU Xin LU Wu LI Xiaolong LIU Mohan WANG Xin SUN Jing GUO Qi Xinjiang Technical Institute of Physics and Chemistry Laboratory of Solid State Radiation Physics

Ionizing radiation effect and failure mechanism of Digital signal processor(DSP) is studied through test-board and automatic test equipment to find the relationship between system function failure and parameter degradation. Static bias is more sensitive than dynamic bias when DSP is tested on-line during radiation. Core current, high-Z leakage current and timing parameter are sensitive to ionizing radiation. No enhanced low-dose-rate sensitivity is found by comparing experiment results under high and low dose rate *** memory interface and Timer are deduced to be the sensitive module by step radiation and analysis basing full parameter test in Verigy 93000. The timing parameter degradation have a strong correlation to these module functions. And the degeneration mechanism is analysed on inverter through Hspice simulation which indicate the leakage circuit caused by radiation can lead a delay to the digital signal propagating. The parasitical capacitance among long connections make it worse to the data transmission around DSP, field programmable gate array and memory. Then an early function failure occurs in test board than Verigy 93000. This work provide support to systematic radiation hardness design and hardness assurance/lot acceptance testing in space applications.

关键词： Verigy 93000 analysis basing full parameter test digital signal propagating radiation effect radiation effects DSP external memory interface leakage currents early function failure leakage circuit test board sensitive module system function failure high dose rate radiation static bias automatic test equipment timing parameter degradation low dose rate radiation field programmable gate array enhanced low-dose-rate sensitivity Digital signal processor degeneration mechanism systematic radiation hardness design radiation hardening (electronics) field programmable gate arrays integrated circuit testing ionizing radiation dynamic bias module functions step radiation digital signal processing chips failure mechanism test-board

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Real-time implementation of non-integer oversampling timing recovery algorithm incorporating IQ compensation for coherent optical communication systems

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Optical Fiber Technology 2025年 93卷

作者： Benyao Zou Wei Wang Kaiyang Dong Hong Wang Fan Li School of Electronics and Information Technology Sun Yat-Sen University Guangzhou 510275 China Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems Sun Yat-Sen University Guangzhou 510275 China

In coherent optical communication systems, digital signal processing (DSP) plays a critical role in achieving efficient signal recovery and demodulation. The traditional analog-to-digital converter (ADC) must operate at integer oversampling (≥2 samples per symbol, SPS) to support accurate timing recovery algorithms. However, the computational complexity involved in processing individual symbols presents significant challenges in meeting the low-power consumption demands of high-speed optical modules. In this paper, we propose a timing recovery algorithm based on the Modified-Godard algorithm for coherent optical communication systems that can work under non-integer baudrate oversampling, which greatly reduces the complexity of DSP and effectively alleviates the demand for ADC with high oversampling rates. Our algorithm enables simultaneous timing recovery and IQ skew compensation in the frequency domain (FD). In order to ensure the reliability of our DSP algorithms under non-integer baudrate oversampling, we analyze and simulate the impact of the laser frequency offset and IQ skew on the timing recovery algorithm. Finally, the DSP algorithms are further implemented on a field-programmable gate array (FPGA) chip. The experimental results demonstrate that the real-time coherent receiver achieves a minimum received optical power of −35-dBm at the KP4-FEC BER threshold, while reducing the ADC sampling rate by 42.9 % compared to conventional timing recovery schemes.

关键词： Coherent optical communication Digital signal processing field programmable gate array Timing recovery

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High-resolution independent component analysis-based time-of-arrival estimation for line-of-sight multipath environments

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IET COMMUNICATIONS 2011年第10期5卷 1440-1452页

作者： Pourkhaatoun, M. Zekavat, S. A. (Reza) Michigan Technol Univ Dept Elect & Comp Engn Houghton MI 49931 USA

A novel super resolution time-of-arrival (TOA) estimation technique applicable to multipath wireless channels is proposed. Here, it is assumed that the line-of-sight signal is available. This technique applies the concept of independent component analysis (ICA) to the received signal in the frequency domain. The proposed ICA algorithm solves an optimisation problem for TOA estimation. The selection of a proper cost function for this optimisation is investigated. The objective is to improve the estimation performance in multipath environments. The proposed technique extracts the TOA estimation iteratively. An optimum initialisation constraint is incorporated to detect the desired (shortest) TOA as the first estimated time delay. This reduces the complexity of the proposed approach. Compared with the traditional super-resolution techniques such as MUSIC, this algorithm represents a lower sensitivity to signal-to-noise ratio (SNR) for positive SNRs, and bandwidth. The proposed method is a good candidate for high-resolution TOA estimation in rich scattering wireless environments. It possesses a low complexity implementation over many high-speed fixed-point platforms such as digital signal processor (DSP) and field programmable gate array (FPGA). The proposed technique has applications in radar, sonar, wireless local positioning systems, and, localisation in mobile ad hoc networks.

关键词： field programmable gate array signal-to-noise ratio mobile ad hoc networks FPGA rich scattering wireless environments MUSIC multipath channels Radionavigation and direction finding high-resolution independent component analysis wireless local positioning systems Signal processing and detection high-speed fixed-point platforms frequency domain time-of-arrival estimation time-of-arrival estimation technique sonar Mobile radio systems optimum initialisation constraint DSP multipath wireless channels cost function Sonar and acoustic radar TOA estimation digital signal processor MANET line-of-sight signal independent component analysis radar radar applications Other topics in statistics

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Design of Narrow Transition Band Digital Filter: An Analytical Approach

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INTEGRATION-THE VLSI JOURNAL 2019年第Sep.期68卷 38-49页

作者： Roy, Subhabrata Chandra, Abhijit Jadavpur Univ Dept Instrumentat & Elect Engn Sect 3Block LBPlot 8 Kolkata 700106 India

Frequency response masking (FRM) approach, is widely used to reduce the transition width of FIR filter which includes several advantages like lower coefficient sensitivity, higher computation speed and low power consumption. This paper proposes a novel interpolated bandpass method (IBM) for the synthesis of linear phase, narrow transition band FIR filter with less complexity. Simulation results have shown the magnitude response of several lowpass FIR filters with narrow transition bandwidth, as designed with the aid of proposed approach. Supremacy of the proposed algorithm has also been established in terms of frequency response characteristics and hardware complexity over a number of state-of-the-art techniques of recent interest. Simulation results have identified an improvement of similar to 18.89%, 44.62%, 38.75%, 41.2% and 29.5% in terms of transition bandwidth when compared with several example filters under consideration. In addition to this, hardware cost resulting from the proposed narrow-band FIR filter is analyzed by implementing it on Artix field programmable gate array (FPGA) chip and consequently power consumption of the resulting filter has been estimated using Xilinx Power Estimator (XPE)-2018.1. Finally, the designed narrow transition band FIR filter is used in filtered-orthogonal frequency division multiplexing (F-OFDM) based quadrature amplitude modulated (QAM) system and the resultant bit error rate (BER) performance has been studied.

关键词： Bandpass filter Bit error rate Finite impulse response filter field programmable gate array Filtered OFDM Low complexity Narrow-band filter Orthogonal frequency division multiplexing Xilinx

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A Survey: FPGA-Based Dynamic Scheduling of Hardware Tasks

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Chinese Journal of Electronics 2021年第6期30卷 991-1007页

作者： LI Tianyang ZHANG Fan GUO Wei SUN Mingqian CHEN Li PLA Strategic Support Force Information Engineering University National Digital Switching System Engineering and Technological R&D Center Southeast University

To meet the increasing computing needs of various application fields, field programmable gate array(FPGA) has been widely deployed. In FPGA-based processing, hardware tasks can be better accelerated by allocating appropriate computing resources. Therefore,FPGA-based hardware task scheduling has become one of the mainstream research directions in academia and industry. However, the optimization objectives of existing FPGA-based hardware task scheduling methods are relatively scattered. In this regard, this paper summarizes the research status of hardware task dynamic scheduling from the three essential elements of FPGA processing: time, resources, and power *** paper analyzes, sorts out, categorizes the ideas and implementations of various scheduling methods and analyzes and evaluates optimization effects of various scheduling methods from multiple dimensions. Then, the shortcomings of the existing methods are summarized and some practical applications are introduced. Finally, the research direction of task scheduling based on FPGA is prospected and summarized.

关键词： optimisation field programmable gate array FPGA-based dynamic scheduling mainstream research directions appropriate computing resources dynamic scheduling optimization objectives hardware task dynamic scheduling power consumption field programmable gate arrays

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High-performance digital replica of analogue peak current mode control for DC-DC converter

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IET POWER ELECTRONICS 2016年第4期9卷 809-816页

作者： Taeed, Fazel Nymand, Morten Univ Southern Denmark Maersk Mc Kinney Moller Inst Fac Engn Odense Denmark

A simple and robust digital peak current mode controller is proposed in this study. The controller replicates an analogue peak current mode control in the discrete domain. The inner current loop has negligible delay, which results in a high controller bandwidth. The controller structure allows the compensation slope to be updated in each switching cycle;therefore, the controller can maintain a high bandwidth over a wide range of operating points. The modelling principles of an analogue peak current mode controller are used to model the proposed controller. For experimental verification, the controller is implemented in a field programmable gate array to control a 100 W buck converter. The measured loop gain of the system correlates very well with the modelling results. The achieved controller crossover frequency is similar to 1/10 of the switching frequency which is close to the crossover frequency of analogue peak current mode controllers.

关键词： DC-DC power convertors electric current control field programmable gate arrays high-performance digital replica analogue peak current mode control DC-DC converter digital peak current mode controller inner current loop buck converter field programmable gate array power 100 W

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