检索结果-内蒙古大学图书馆

Proceedings of the 1998 ACM/SIGDA sixth international symposium on field programmable gate arrays

作者： James R. Anderson Siddharth Sheth Kaushik Roy Intel Corporation 2200 Mission College Blvd. Santa Clara CA School of Electrical Engineering Purdue University West Lafayette IN

ISBN: (纸本)9780897919784

This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations.

关键词： architecture finite impluse response filtering digital signal processing field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

A Real-time Synthetic Aperture Beamformer for Medical Ultrasound Imaging 2010

A Real-time Synthetic Aperture Beamformer for Medical Ultras...

引用

2010 IEEE International Ultrasonics Symposium

作者： Jong-Ho Park Changhan Yoon Jin Ho Chang Yangmo Yoo Tai-Kyung Song Interdisciplinary Program of Integrated Biotechnology Sogang University Seoul Korea Department of Electronic Engineering Sogang University Seoul Korea Sogang Institute of Advanced Technology Sogang University Seoul Korea

ISBN: (纸本)9781457703829

Synthetic aperture (SA) imaging techniques have drawn many attentions since they are capable of providing improved spatial resolution over conventional receive dynamic focusing (CRDF) methods. However, the processing of SA imaging is computationally demanding for real-time processing. Furthermore, massive memories for storing the pre-beamformed radio frequency (RF) data are required, leading to substantial increase in hardware complexity. In this paper, we propose the efficient real-time SA beamformer architecture that could be integrated in modern ultrasound imaging systems. The feasibility of the proposed architecture was demonstrated by implementing a 64-channel SA beamformer on two high-performance field programmable gate arrays (FPGAs, Virtex-5 SX95T, Xilinx, USA). The developed SA beamformer can support up to 12 synthesis beams by utilizing 61percent of slice registers, 43percent of lookup tables (LUTs), 89percent of random access memories (RAMs) and 51percent of digital signal processing (DSP) blocks in each FPGA.

关键词： Synthetic aperture beamformer field programmable gate array dynamic receive focusing radiofrequency random access machine Digital signal processing Synthetic aperture field programmable gate arrays slicing Ultrasonography

来源：评论

学校读者我要写书评

暂无评论

Classification of Myoelectric Signals Using Multilayer Perceptron Neural Network with Back Propagation Algorithm in a Wireless Surface Myoelectric Prosthesis

Classification of Myoelectric Signals Using Multilayer Perce...

引用

SCIEI 2015 Paris Conference

作者： Kevin D.Manalo Noel B.Linsangan Jumelyn L.Torres Mapúa Institute of Technology the Computer Engineering (Cp E) program at the Mapúa Institute of Technology the Computer Engineering (CpE)Department at Mapúa Institute of Technology

The paper focuses on a wireless myoelectric prosthesis of the upper-limb that uses a Multilayer Perceptron(MLP) neural network with back propagation algorithm in classifying electromyography(EMG) *** Neural network is composed of processing units that have the capability of sending signals to each other and perform a desired *** algorithm is widely used in pattern *** network is used to train EMG signals and use it in performing the necessary hand positions of the *** programming a field programmable gate array(FPGA) using Verilog and transmission of data with Zigbee,the EMG signals are acquired,classified,and simulated *** signals are classified and trained to produce the necessary hand *** corresponding hand movements of Open,Pick,Hold and Grip are simulated through the Zigbee controller.Z-test is used to analyze the data that were produced and acquired from using the neural network.

关键词： field programmable gate array Multilayer Perceptron Neural network Verilog Zigbee

来源：评论

学校读者我要写书评

暂无评论

Networks-on-Chip for FPGAs: Hard, Soft or Mixed?

引用

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2014年第3期7卷 20-20页

作者： Abdelfattah, Mohamed S. Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

As FPGA capacity increases, a growing challenge is connecting ever-more components with the current low-level FPGA interconnect while keeping designers productive and on-chip communication efficient. We propose augmenting FPGAs with networks-on-chip (NoCs) to simplify design, and we show that this can be done while maintaining or even improving silicon efficiency. We compare the area and speed efficiency of each NoC component when implemented hard versus soft to explore the space and inform our design choices. We then build on this component-level analysis to architect hard NoCs and integrate them into the FPGA fabric;these NoCs are on average 20-23x smaller and 5-6x faster than soft NoCs. A 64-node hard NoC uses only similar to 2% of an FPGA's silicon area and metallization. We introduce a new-communication efficiency metric: silicon area required per realized communication bandwidth. Soft NoCs consume 4960 mm(2)/TBps, but hard NoCs are 84x more efficient at 59 mm(2)/TBps. Informed design can further reduce the area overhead of NoCs to 23 mm(2)/TBps, which is only 2.6x less efficient than the simplest point-to-point soft links (9 mm(2)/TBps). Despite this almost comparable efficiency, NoCs can switch data across the entire FPGA while point-to-point links are very limited in capability;therefore, hard NoCs are expected to improve FPGA efficiency for more complex styles of communication.

关键词： Design Measurement Performance field programmable gate array network-on-chip application-specific integrated circuit interconnect area delay resource management hard soft

来源：评论

学校读者我要写书评

暂无评论

A system-level design for foreground and background identification in 3D scenes

A system-level design for foreground and background identifi...

引用

International Symposium on Circuits and Systems

作者： Amin Safaei Q. M. Jonathan Wu Department of Electrical and Computer Engineering University of Windsor Windsor ON Canada

ISBN: (纸本)9781479953424

This paper proposes a system-on-chip (SoC) FPGA - based real-time video processing platform for background and foreground identification. Background and foreground identification is a co mmon feature in many tasks in video content analytics (VCA), including object detection, tracking, segmentation and recognition. VCA is a relatively new field in video processing;it has generally been implemented using two chips, with the image signal processing (ISP) part in a DSP or an FPGA and the VCA part executed by a processor. However, a new generation of SoC FPGAs that incorporates a processor and an FPGA into a single chip makes it possible for a single chip to perform both ISP and VCA. This study details the hardware implementation of a real-time background and foreground identification algorithm in an SoC, including the capture, processing and display stages. The proposed platform uses photometric invariant color, depth data and local binary patterns (LBPs) to distinguish backgrounds from foregrounds. The system uses minimal cell resources and tries to implement modules using a pipeline technique.

关键词： subtraction techniques Real time video processing field programmable gate array embedded vision

来源：评论

学校读者我要写书评

暂无评论

Analyzing Electro Cardio Graphy Signals using Least-Square Linear Phase FIR Methodology

Analyzing Electro Cardio Graphy Signals using Least-Square L...

引用

2014 1st International Congress on Computer,Electronics,Electrical,and Communication Engineering(ICCEECE2014)

作者： Mohamed G.Egila Magdy A.El-Moursy Adel E.El-Hennawy Hamed A.El-Simary Amal Zaki Microelectronics Department Electronics Research InstituteCairoEgypt Mentor Graphics Corporation CairoEgypt Communication and Electronics Department Ain Shams UniversityCairoEgypt

This paper presents a signal processing methodology to analyze Electrocardiography(ECG) signals. Discrete Wavelet Transform(DWT) is used as a feature extraction methodology to achieve efficient design. Baseline wandering noise is removed in this design using Lest-Square Linear Phase FIR methodology. ECG signals classification is done using Feed forward neural network methodology. An accuracy of 100% in identifying the normal samples, and accuracy of 95.23% for identifying abnormal ECG beats are obtained, achieving a total accuracy of 97.78% for identifying ECG signals using this presented methodology.

关键词： Discrete Wavelet Transform Denoising Neural Networks field programmable gate array Electro Cardio Goraphy

来源：评论

学校读者我要写书评

暂无评论

DESIGN OF A ROBUST ADAPTIVE CMAC SYSTEM FOR BLDC MOTORS WITH PI TYPE PARAMETER ADAPTATION

DESIGN OF A ROBUST ADAPTIVE CMAC SYSTEM FOR BLDC MOTORS WITH...

引用

2008 International Conference on Machine Learning and Cybernetics (ICMLC 2008), vol.7

作者： CHAO-MING CHUNG CHUN-FEI HSU CHIH-MIN LIN CHIA-YU HSU Department of Electrical Engineering Yuan-Ze University Chungli Taiwan Department of Electrical Engineering Chung Hua University Hsinchu Taiwan

The main advantage of cerebellar model articulation controller (CMAC) is its fast learning rate compared to other neural networks since it can provide more potential to enrich the mapping relationship between inputs and outputs. This paper proposes a robust adaptive CMAC system for brushless DC motors with PI type parameter adaptation. CMAC is used to mimic an ideal controller based on the Lyapunov stability theory, and the robust controller is designed to achieve L{sub}2 tracking performance with desired attenuation level. The robust adaptive CMAC system is implemented on a field programmable gate array chip and is applied to brushless DC (BLDC) motor control. Some experimental results verify that the proposed robust adaptive CMAC method can achieve good parameter adaptation and favorable tracking performance.

关键词： Adaptive control Robust control CMAC BLDC motor field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

MPC based Controller Design of Battery Integrated Modular Multilevel Converter

MPC based Controller Design of Battery Integrated Modular Mu...

引用

第40届中国控制会议

作者： Fang Xu Zhongyi Guo Qifang Liu Hong Chen Yali Qu State Key Laboratory of Automotive Simulation and Control Jilin University College of Communication Engineering Jilin University Department of control science and engineering Tongji University Huawei Technologies Co. Ltd.

The control performance of converter directly affects the drive efficiency of electric vehicle（EV）.This paper studies on the model predictive control（MPC） based controller design of battery integrated modular multilevel converter（B-MMC）.Aiming at the goal of three-phase current tracking and battery balancing control of B-MMC,three-layer controllers are *** first controller is the finite control set model predictive control（FCS-MPC）,which realizes the motor drive by tracking the phase *** second controller is the circulation controller for the active balance control of *** is composed of multiple proportional controllers to realize the battery balance between the bridge *** third controller is the battery sorting algorithm to achieve the passive balance control of the battery in the same bridge *** the same time,field programmable gate array（FPGA） is used to accelerate the controller to meet the real-time requirements of ***,the simulation results of the B-MMC control system validates the effectiveness of the control algorithm.

关键词： Electric Vehicle Battery Integrated Modular Multilevel Converter Finite Control Set Model Predictive Control field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Code Generator Implementation on FPGA for an Optical ZCZ Code Using a Sylvester Type Hadamard Matrix

Code Generator Implementation on FPGA for an Optical ZCZ Cod...

引用

第三届信号设计及其在通信中的应用国际会议(Proceedings of 2007 International Workshop on Signal Design and Its Applications in Communications IWSDA'07)

作者： Takahiro MATSUMOTO Shinya MATSUFUJI Graduate School of Science and Engineering Yamaguchi University2-16-1 Tokiwadai Ube 755-8611 Japan

The optical ZCZ code is a set of pairs of binary and bi-phase sequences with zero correlation zone. An optical code division multiple access (CDMA) system using this code can remove co-channel interference and influence of multi-path. We proposed the compact construction of a bank of matched filters for this code in a receiver. But we have not proposed the construction of a code generator for this code in a transmitter yet. In this paper, we propose the construction of two code generators for an optical ZCZ code using a Sylvester-type Hadamard matrix, which are called ROM-type and non ROM- type code generators. This ROM-type code generator can be constructed by a ROM and a up-counter. Similarly,this non ROM-type code generator can be constructed by a up-counter, flip-flops and logic gates. The ROM-type and non ROM-type code generators are implemented on a field programmable gate array (FPGA) corresponding to 400,000 logic gates, and the non ROM-type code generator can reduce logic elements than the ROM-type code generator.

关键词： Optical communication Optical ZCZ code Optical CDMA system Code generator field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

TURTLE: A Low-Cost Fault Injection Platform for SRAM-based FPGAs

TURTLE: A Low-Cost Fault Injection Platform for SRAM-based F...

引用

International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Corbin Thurlow Hayden Rowberry Michael Wirthlin NSF Center for Space High-performance and Resilient Computing (SHREC) Brigham Young University Provo Utah USA

ISBN: (纸本)9781728119588

This paper presents the TURTLE fault injection platform for inserting faults into SRAM FPGAs. The TURTLE system is designed to gather significant fault injection data to test and validate radiation-induced single-event upset (SEU) mitigation techniques for FPGAs. The TURTLE is a low-cost fault injection platform that emulates upsets within the configuration memory (CRAM) of an FPGA through partial reconfiguration. This work successfully implemented the proposed architecture and performed several successful fault injection campaigns on multiple designs and SEU mitigation techniques. Results in this paper show large amounts of data collected from a fault injection campaign used to validate the PCMF SEU mitigation technique. Over 170 million injections were performed using the TURTLE for this campaign.

关键词： field programmable gate array Fault injection SEU Mitigation field programmable gate arrays Single event upsets faults Injections Upset Platform

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：