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2010 Asia-Pacific Conference on Power Electronics and Design (APPED 2010)

作者： Guo Weina College of Computer and Automation Hebei Polytechnic University Tangshan,China Huang Wenjie College of Computer and Automation Hebei Polytechnic University Tangshan,China

Explain the factors which affect the performance of optical current transformer (OCT) and Solutions. Signal processing measure is the key to the application of optical current transformer. Therefore the signal processing system’s improved method of optical current transformer was introduced, and prospects the future development of optical current transformers.

关键词： Matlab power system technology optical current transformer faraday effect digital signal processing adaptive interference cancellation field programmable gate array real-time wavelet analysis

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Behavior of a Hippocampal Spiking Network and FPGA Implementation

Behavior of a Hippocampal Spiking Network and FPGA Implement...

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第三十八届中国控制会议

作者： Jingyi Hao Xinyu Hao Jiang Wang Shuangming Yang Bin Deng Haitao Yu School of Electrical and Information Engineering Tianjin University

The hippocampus in human brain is responsible for memory processing and tasks learning, which has long been one of the main interests of many researchers. In this paper, a spiking neural network of the hippocampus is realized based on a designed task. In the task, the model rat firstly gets familiar with the environment and finds item in one of the pots and finally gets a reward for making the correct response. Through the network, the feature of the hippocampal neurons can be simulated in software successfully. The three-layer network was built based on the spike-timing dependent synaptic plasticity and the synaptic weights will be modified between layers during task which can finally achieve the memory-related behavior of the model rat. Besides software realization, we also utilize field programmable gate array(FPGA) to reproduce the characteristics of the network in real time. The results show that the spiking neural network of the hippocampus can mimic the memory-related behavior of the model rat.

关键词： Hippocampus spiking neural network memory-related behavior field programmable gate array

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Generic Data Acquisition System for Multi-Dimensional Radiation Detectors

Generic Data Acquisition System for Multi-Dimensional Radiat...

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2007 IEEE Nuclear Science Symposium Conference, vol.2

作者： Adam W. Lynch Andrew Berry Goran Panjkovic Rob Lewis Monash Centre for Synchrotron Science Monash University Melbourne Australia

The instrumentation group at the Monash Centre for Synchrotron Science have developed a low cost generic data acquisition system. This system is to be used in a variety of applications and to assist in the design and testing of emerging detectors. The system utilises a desktop PC which interfaces to a detector via one or more custom 64-bit PCI cards, each equipped with an Altera CycloneII FPGA (2c70) and plug-in daughter boards, this provides flexibility to easily customise analogue and digital signal processing. A GUI application controls the system via variables and scripts, renders and analyses real-time data, and supports importing and exporting in a variety of formats. This paper presents an overview of the data acquisition system and the process of interfacing with a two-dimension multi-wire proportional chamber with delay-line readout with an expected timing resolution of 10 ρs.

关键词： Data acquisition field programmable gate array Nuclear electronics Instrumentation computing Readout electronics X-ray detectors

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A FPGA-Based Data Acquisition System for GEM array detector

A FPGA-Based Data Acquisition System for GEM array detector

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IEEE Nuclear Science Symposium

作者： W. W. Yen H. P. Chou Department of Engineering and System Science National Tsing-Hua University Hsinchu Taiwan

In the present study, a data acquisition system for a GEM one-dimensional array detector is presented. The detector system is to measure the trajectory of photoelectrons produced by cosmic rays. The GEM array detector for the present project has 16 signal channels. The front-end unit provides timing signals from trigger units and energy signals from charge sensitive amplifies and pulse shapers. The timing signals and the energy signals are fed to the time-to-digital converter (TDC) units and analog-to-digital converter (ADC) units respectively. The TDC is to measure the time interval between time marks provided by the front-end unit for trajectory information. The measurement of the pulse height for particle energy information is using an amplitude to time convertor (ATC). The designed TDC has a resolution about 2 ns with good linearity.

关键词： Time-to-Digital Converter field programmable gate array Front-end Electronics Gas Electron Multiplier Detector

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Acceleration and Implementation of Convolutional Neural Network Based on FPGA

Acceleration and Implementation of Convolutional Neural Netw...

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作者： Enyi Wang Dehui Qiu Information and Engineering College Capital Normal University

Aiming at the problem of high power consumption and slow operation speed of neural network in embedded system, this paper presents an automatic design method of convolutional neural network(CNN) accelerator based on field programmable gate array(FPGA) to meet the requirements of embedded terminal for operation performance and power consumption. Firstly, in order to reduce the storage resources of the FPGA and the time required for network computing, the weight quantization method is used to convert network parameters from floating-point data to binary data. Secondly, in order to improve the speed and throughput of the whole system, coarse-grained and fine-grained parallel computing optimization methods are used. In this paper, the above acceleration scheme will be applied to the scene of unmanned aerial vehicle(UAV) object detection. The test results shows that the power consumption of the system is 2.38 W and the calculated power consumption ratio is 29.3 GOPS/W. Compared with the work of related literature in recent years, the proposed scheme can provide higher speed and efficiency. The experimental results show that the accuracy of the IOU is 21% and the speed is 7 FPS.

关键词： Convolutional Neural Network field programmable gate array Weight quantization Parallel computing Object detection

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Implementation of Digital Lock-in Amplifier Based on System Generator

Implementation of Digital Lock-in Amplifier Based on System ...

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2016 IEEE International Conference on Signal and Image Processing

作者： Qingfeng Wang Hong Zheng Meng Jiang School of Automation Science and Electrical Engineering Beijing University of Aeronautics and Astronautics 13th Research Institute The Ninth Research Academy of China Aerospace Science and Technology Corporation

Nowadays the weak signal detection technology is necessary in scientific research field, in which the phase-locked amplifying technology is widely used in the field of weak signal detection because it can meet the requirements of high speed and high *** Generator software is adopted as a tool since System Generator can make the design more conveniently and *** design of each module in orthogonal vector type digital phase-locked amplifier is introduced in this *** overall design was *** simulation results confirm that the design is feasible.

关键词： Weak signal Lock-in amplifier System Generator Orthogonal vector field programmable gate array

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Design and Implementation of Router for NOC on FPGA

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INTERNATIONAL JOURNAL OF FUTURE GENERATION COMMUNICATION AND NETWORKING 2016年第12期9卷 263-271页

作者： Verma, Gaurav Agarwal, Harsh Singh, Shreya Khanam, Shaheem Nighat Gupta, Prateek Kumar Jain, Vishal Jaypee Univ Dept Elect & Commun A-10 Sect-62 Noida Uttar Pradesh India BVICAM New Delhi India

In today's technological era, SOC has undergone rapid evolution and is still processing at a swift pace. But due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate and hence, SOC today have become communication-centric. However, the existing bus architectures comprising of wires for global interconnection in SOC design are undergoing design crises as they are not able to keep up with the rate of scaling down of devices. To overcome bottleneck of communication system, NOC is an upcoming archetype. In on-chip network, router is considered as an important component. This paper proposes router, its components and parameters which affects the entire design. Thus, to validate the functioning of NOC on hardware, router has been designed in VHDL and simulated in Xilinx ISE 14.1 targeting Xilinx XC5VLX30-3 FPGA.

关键词： Network-on-chip System-on-chip VHDL field programmable gate array

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FPGA-based Real-Time Hardware-In-the-Loop validation of a 3-phase PWM Rectifier controller

FPGA-based Real-Time Hardware-In-the-Loop validation of a 3-...

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Annual Conference of the IEEE Industrial Electronics Society

作者： M. Dagbagi A. Hemdani L. Idkhajine M. W. Naouar E. Monmasson I. Slama-Belkhodja Universite de Tunis El Manar ENIT SATIE-IUP GEII

ISBN: (纸本)9781479902255

The proposed paper deals with Hardware-In-the-Loop (HIL) validation of a 3-phase PWM boost rectifier controller. This validation has been made using field programmable gate array (FPGA) target. The development of the Real-Time Emulator (RTE) of the power system is firstly discussed. All voltage sources from the grid, filters, power switches and the load real-time models are implemented in hardware using a Xilinx Spartan-6 FPGA device. As for the controller, a PI-based strategy has been chosen to control the DC-link voltage and a Hysteresis-based one for the control of 3-phase line currents. This controller has been implemented in software using the embedded Cortex-M3 processor of SmartFusion FPGA from MicroSemi. Real-time HIL simulation results, as well as offline simulation results are presented and compared.

关键词： Real time Hardware-In-the-Loop PWM boost rectifier field programmable gate array Real-Time Emulator Associate Discrete Circuit Processor-based controller

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Area Efficient Vernier Time to Digital Converter(TDC) with Improved Resolution using Identical Ring Oscillators on FPGA

Area Efficient Vernier Time to Digital Converter(TDC) with I...

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IEEE International Conference on Smart Structures and Systems

作者： Mahantesh P Mattada Hansraj Guhilot Department of Electronics &Telecommunication Sanjay Godawat Group of Institutions Kolhapur INDIA Department of Electronics & Communication K.L.E. Society's College of Engineering & Technology Belgaum INDIA

ISBN: (纸本)9781467362429

We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement. Ring oscillators used in this work are identical and designed using fast carry logic. The reported improved resolution is attributed to the difference in their frequencies. The novel technique of obtaining difference in their period reduces manual efforts of designer. Two main features of this work are prototyping on a low-cost general purpose FPGA and new low cost verification methodology.

关键词： Time to Digital Converter TOF Tapped Delay Line field programmable gate array Fluorescence Vernier Delay Line Ring oscillator Ring oscillators field programmable gate arrays FEZF2 gene tapped delay line Fluorescence system clock Identical

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FPGA Implementation of Real-Time Soldier Activity Detection based on Neural Network Classifier in Smart Military Suit

FPGA Implementation of Real-Time Soldier Activity Detection ...

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IEEE Bombay Section Signature Conference (IBSSC)

作者： Nikhil B. Gaikwad Avinash G. Keskar Varun Tiwari NC Shivaprakash Electronics and Communication Department Visvesvaraya National Institute of Technology (VNIT) Nagpur India Department of Instrumentation and Applied Physics Indian Institute of Science (IISc) C V Raman Ave Bengaluru India

ISBN: (纸本)9781538674765

The wearable technology carries sufficient potential to incorporate smartness into working of the military workforces like the Military Control Unit, Medical Responders, Backup Unit and War Strategist. The proposed work focuses on real-time soldier activity detection, which is essential for the operation of the smart military suit. The customized Artificial Neural Network (ANN) IP core is developed for the soldier activity classification, which is an integral component of suit gateway design. The multilayer perceptron (7-5-4) classification algorithm is implemented on the low-cost (99$) FPGA evaluation platform by using Xilinx vivado and system generator development tools. The training (70%) and testing (30%) of this ANN design is performed on the UCI human activity dataset. The LabVIEW GUI and IP test design completed the hardware testing of this IP. The presented ANN IP is able to achieve 98.5% classification accuracy by utilizing minimal FPGA (Artix-7 xc7a35t) resources. The implemented ANN design requires only 285 nanoseconds for a classification and consumes 103 milliwatts of dynamic power. The system's accuracy at different development levels is also studied in this work.

关键词： Smart military suit Soldier activity detection Artificial neural network Smart sensor gateway Network centric warfare field programmable gate array field programmable gate arrays Artificial neural networks Soldiers Activity Detection Military Personnel Hardware Test brightness EIS IMPLEMENTATION PLANS Bayesian classifier Sorting algorithm

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