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FPGA-based research of monitoring MPDCPD-CSMA protocol in cognitive wireless networks

JOURNAL OF INTELLIGENT & FUZZY SYSTEMS 2018年第2期35卷 1353-1361页

作者： Xu, Zhi Ding, Hongwei Liu, Qianlin Yang, Zhijun Bao, Liyong Zhan, Gang Yunnan Univ Sch Informat Kunming 650504 Yunnan Peoples R China Yunnan Mil Command Reg Kunming Yunnan Peoples R China

In order to solve the contradiction between wireless network application requirements and increasingly scarce spectrum resources, cognitive wireless network technology emerged. Based on the characteristics of wireless network nodes and combining multiple hybrid control strategies, this paper proposes a multi-priority dual-clock probability detection CSMA(MPDCPD-CSMA) protocol with a monitoring mechanism. The field-programmable gate array (FPGA) hardware circuit is used as an experimental research platform for the first time. Cognitive wireless network MAC protocol design and implementation. The design took full advantage of the flexibility of the FPGA, using a hardware description language Verilog HDL and schematic input combined with the QuartusII9.0 circuit design. By comparing the statistical values of the circuit system with the theoretical values, it is verified that the design has the characteristics of good real-time performance, high reliability, and strong portability. It can effectively reduce system node energy consumption, improve system throughput, and can be applied to wireless networks.

关键词： cognitive wireless network hybrid control strategy field programmable gate array schematic input throughput

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Design and implementation of an RNS-based 2-D DWT processor

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2004年第1期50卷 376-385页

作者： Liu, Y Lai, EMK Nanyang Technol Univ Sch Comp Engn Ctr Multimedia & Network Technol Singapore 639798 Singapore

Discrete wavelet transform has been incorporated as part of the JPEG2000 image compression standard and is used in many consumer imaging products. This paper presents a 2-dimensional biorthogonal DWT processor design based on the residue number system. The symmetric extension scheme is employed to reduce distortion at image boundaries. Hardware complexity reduction and utilization improvement are achieved by hardware sharing. Our implementation results show that the design is able to fit into a 1,000,000-gate FPGA device and is able to complete a first level 2-D DWT decomposition of a 32x32-pixel image in 205mus(1).

关键词： discrete wavelet transform residue number system field programmable gate array

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Deep Neural Network-Based Cigarette Filter Defect Detection System with FPGA Acceleration for Online Recognition

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SENSORS 2024年第20期24卷 6752页

作者： Huang, Liang Shen, Qiongxia Jiang, Chao Yang, You Huazhong Univ Sci & Technol Sch Elect Informat & Commun Wuhan 430074 Peoples R China Fiberhome Telecommun Technol Co LTD Wuhan 430205 Peoples R China

In the cigarette manufacturing industry, machine vision and artificial intelligence algorithms have been employed to improve production efficiency by detecting product defects. However, achieving both high accuracy and real-time defect detection for cigarettes with complex patterns remains a challenge. To address these issues, this study proposes a model based on RESNET18, combined with a feature enhancement algorithm, to improve detection accuracy. Additionally, a method is designed to deploy the model on a field-programmable gate array (FPGA) with high parallel processing capabilities to achieve high-speed detection. Experimental results demonstrate that the proposed detection model achieves a detection accuracy of 95.88% on a cigarette filter defect dataset with an end-to-end detection speed of only 9.38 ms.

关键词： defect detection deep neural network field programmable gate array real-time

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High-speed parallel reconfigurable Fp multipliers for elliptic curve cryptography applications

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2022年第4期50卷 1160-1173页

作者： Javeed, Khalid Saeed, Kamran Gregg, David Trinity Coll Dublin Sch Comp Sci Dublin Ireland Bahria Univ Islamabad Dept Comp Engn Islamabad Pakistan

Elliptic curve cryptography (ECC) protocols due to higher security strength per bit have been widely accepted and deployed. Finite field multiplication is the most computational intensive operation in data security protocols developed using ECC. This paper presents two high-speed parallel re-configurable finite field multipliers: PIMD-2 and PIMD-3 over prime field (F-p) for ECC applications. The proposed designs are based on the new novel optimized interleaved multiplication algorithms. This work first identifies room of parallelism by investigating independent operations in the standard interleaved multiplication method and subsequently proposes high-speed hardware architectures that allow the parallel execution of these operations. Due to the introduced modifications, the critical path delays and clock cycle consumption in the PIMD-2 and PIMD-3 designs are reduced simultaneously. The proposed F-p multipliers are synthesized using Xilinx ISE Design Suite and implemented on Virtex-5 and Virtex-6 field programmable gate array (FPGA) platforms for common ECC key sizes 160-521 bits. The implementation results reveal that the proposed designs are highly efficient, provided up to 3x improvement in latency with lower area-delay product and higher throughput per FPGA slice as compared to the state-of-the-art.

关键词： elliptic curve cryptography field programmable gate array finite field multiplication hardware accelerators public key cryptography

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Fast Power and Performance Evaluation of FPGA-Based Wireless Communication Systems

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IEEE ACCESS 2016年 4卷 2005-2018页

作者： Lorandel, Jordane Prevotet, Jean-Christophe Helard, Maryline Natl Inst Appl Sci INSA IETR F-35708 Rennes France

In this paper, a new and efficient methodology is proposed to quickly and precisely evaluate the power consumption and performance of wireless communication base-band systems implemented in field-programmable gate arrays (FPGAs). As the complexity of such systems is still growing, being able to estimate both power and performance of a design has become a major issue. FPGA devices constitute a promising technology in this highly constrained context. However, to respect their power budget, designers need to explore the design space very soon in the design process. This is performed prior to any implementation. Based on the innovative definition of a scenario, which enables comparison among wireless communication applications in a formal manner, each parameter can be evaluated to meet the power-performance tradeoff. In this paper, the proposed methodology is realized in two steps using a low-level characterization process and high-level system modeling. Another major contribution consists in considering components' time activity to refine power estimations results. We demonstrate the effectiveness of the proposed methodology throughout several domain-specific use cases, with a focus on hardware base-band processing in the wireless communication domain. As compared with current low-level FPGAs vendor tools, an important speedup factor is obtained, and a maximal relative error lower than 5% is reached.

关键词： Wireless communication field programmable gate array power consumption system modelling SystemC

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An Efficient FPGA based Real-Time Implementation Shunt Active Power Filter for Current Harmonic Elimination and Reactive Power Compensation

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JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY 2015年第4期10卷 1655-1666页

作者： Charles, S. Vivekanandan, C. Sri Shakthi Inst Engn & Technol Dept Elect & Elect Engn Coimbatore Tamil Nadu India SNS Coll Engn Dept Elect & Elect Engn Coimbatore Tamil Nadu India

This paper proposes a new approach of field programmable gate array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

关键词： Digital control Shunt active power filter field programmable gate array Harmonic elimination Reactive power compensation Synchronous reference frame transformation

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Large-Scale Bio-Inspired FPGA Models for Path Planning

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2024年第1期18卷 51-62页

作者： Wang, Kuanchuan Wang, Jiang Hao, Xinyu Deng, Bin Zhang, Zhen Yi, Guosheng Tianjin Univ Sch Elect & Informat Engn Tianjin 300072 Peoples R China

The hippocampus provides significant inspiration for spatial navigation and memory in both humans and animals. Constructing large-scale spiking neural network (SNN) models based on the biological neural systems is an important approach to comprehend the computational principles and cognitive function of the hippocampus. Such models are usually implemented on neuromorphic computing platforms, which often have limited computing resources that constrain the achievable scale of the network. This work introduces a series of digital design methods to realize a field-programmable gate array (FPGA) friendly SNN model. The methods include FPGA-friendly nonlinear calculation modules and a fixed-point design algorithm. A brain-inspired large-scale SNN of similar to 21 k place cells for path planning is mapped on FPGA. The results show that the path planning tasks in different environments are finished in real-time and the firing activities of place cells are successfully reproduced. With these methods, the achievable network size on one FPGA chip is increased by 1595 times with higher resource usage efficiency and faster computation speed compared to the state-of-the-art.

关键词： field programmable gate array FPGA-friendly design fixed-point design path planning spiking neural network

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FPGA-based synchronising control system design for spinning disk confocal image scanning microscope

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ELECTRONICS LETTERS 2019年第23期55卷 1224-+页

作者： Qin, S. Georg August Univ Gottingen Inst Phys 3 Friedrich Hund Pl 1 D-37077 Gottingen Germany

In this Letter, a field programmable gate array (FPGA)-based synchronising control system design for spinning disk confocal image scanning microscope is described. Based on the analysis on the condition of laser triggering, the author simplifies the design by transforming the floating-point calculation formula to a very simple form of integer calculation, which can then be implemented by fixed-point calculation on FPGA without trimming any bit, for which there is no computational precision loss. The testing of simulation and experiment shows that the design is very accurate and reliable.

关键词： field programmable gate arrays synchronisation floating point arithmetic image scanners microscopes floating-point calculation formula fixed-point calculation field programmable gate array synchronising control system design FPGA spinning disk confocal image scanning microscope laser triggering integer calculation

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Simplified electronic signal processing in the small nuclear physics laboratory

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2005年第2-3期551卷 487-492页

作者： DeYoung, PA Peaslee, GF Hope Coll Dept Phys & Engn Holland MI 49422 USA

Small nuclear physics laboratories of all kinds traditionally have processed the signals from radiation detectors with a variety of discrete NIM- or CAMAC-based electronic modules. The logic signals associated with signal processing are often passed through gate generators, coincidence modules, fan-in/fan-out modules, delay units, counters, and other assorted logic modules. These multi-component systems generate gates for acquisition systems, gates for specific linear electronics modules (ADCs and TDCs), or measure count rates and dead times. This can involve a significant number of individual modules each of which can be quite costly and each of which provides only limited functions. We describe here an upgrade to our acquisition system where all the needed logic functions are performed in just a single unit: a Universal Logic Module based on a field programmable gate array (FPGA) from JTEC Corporation. This module also contains flash memory that holds three separate configurations allowing for rapid changes from one electronics configuration to a different one. Both CAMAC and VME versions of the unit are available. The system described here is just one example of the huge variety of functionality that can be programmed into this single module. It can accommodate very complicated circuits and is easily reprogrammed. In the small nuclear physics laboratory the Universal Logic Module can save cost when upgrading systems and reduce the number of instances where one has an insufficient number of channels of a particular function. (c) 2005 Elsevier B.V. All rights reserved.

关键词： field programmable gate array signal processing data acquisition

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Optimal hardware/software partitioning of a system on chip FPGA-based sensorless AC drive current controller

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MATHEMATICS AND COMPUTERS IN SIMULATION 2013年 90卷 145-161页

作者： Bahri, I. Idkhajine, L. Monmasson, E. Benkhelifa, M. E. A. UCP SATIE F-95031 Neuville Sur Oise France ENSEA ETIS F-95014 Cergy Pontoise France

The recent field programmable gate array (FPGA) system on chip devices offer a new degree of design freedom. Indeed, these digital components allow the combination of software treatment (by the on-chip processor cores) and hardware treatment (hardware architecture made by the interconnection of the FPGA logic cells). In the field of industrial control applications, this digital technology is appropriate to reach an optimum between the control performances, the controller algorithm complexity and the design flexibility. On the other hand, a co-design methodology is necessary to make an efficient partitioning of the control algorithm so as to define modules to be software-made and modules to be hardware-made. To this aim, this paper deals with a co-design methodology adapted to SoC FPGA-based controllers for embedded power applications. The case study is a sensorless current controller of a synchronous machine using an extended Kalman filter (EKF). This co-design development is based on two reference implementations: a full software implementation and a full hardware implementation that are also discussed. To find the optimal HW/SW partitioning, a non-dominated sorting genetic algorithm (NSGA-II) is used. (C) 2012 IMACS. Published by Elsevier B.V. All rights reserved.

关键词： field programmable gate array System on chip Co-design methodology NSGA-II Sensorless controller Extended Kalman filter Synchronous machine

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