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Towards Secure Runtime Customizable Trusted Execution Environment on FPGA-SoC

IEEE TRANSACTIONS ON COMPUTERS 2024年第4期73卷 1138-1151页

作者： Wang, Yanling Chang, Xiaolin Zhu, Haoran Wang, Jianhua Gong, Yanwei Li, Lin Beijing Jiaotong Univ Beijing Key Lab Secur & Privacy Intelligent Transp Beijing 100044 Peoples R China

Processing sensitive data and deploying well-designed Intellectual Property (IP) cores on remote field programmable gate array (FPGA) are prone to private data leakage and IP theft. One effective solution is constructing Trusted Execution Environment (TEE) and its secure boot process on FPGA-SoC (FPGA System on Chip). This paper aims to establish Secure Runtime Customizable TEE (SrcTEE) on FPGA-SoC through the design of a novel secure boot scheme and the design of the following three components: 1) CrloadIP, which enforces access control on TEE applications deploying IP at runtime such that SrcTEE can alleviate threats from unauthorized TEE applications and then SrcTEE can be adjusted dynamically and securely;2) CexecIP, which not only enables the execution of newly-installed IP cores without modifying the operating system of FPGA-SoC TEE, but also prevents insider attacks from executing IPs in SrcTEE;3) CremoAT, which can provide the newly-measured SrcTEE state and establish a secure communication path between remote verifiers and SrcTEE. Our secure boot scheme supports refreshable root trust key, and assures the authenticity and integrity of boot codes during the SrcTEE booting process. We conduct a security analysis of SrcTEE and its performance evaluation on Xilinx Zynq UltraScale+ XCZU15EG 2FFVB1156 MPSoC.

关键词： field programmable gate arrays Runtime IP networks Codes System-on-chip Access control Random access memory field programmable gate array intellectual property secure boot system on chip trusted execution environment

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Secured Authentication of RFID Devices Using Lightweight Block Ciphers on FPGA Platforms

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IEEE ACCESS 2023年 11卷 107472-107479页

作者： Anusha, R. Rao, P. Raghavendra Rai, N. Pratheksha Nitte Deemed Univ NMAM Inst Technol Dept Elect & Commun Engn Nitte 574110 Karnataka India Manipal Acad Higher Educ Dept Mechatron Manipal Inst Technol Manipal 576104 Karnataka India AJ Inst Engn & Technol Dept Elect & Commun Engn Mangalore 575006 India

Near field Communication (NFC) has emerged as a pivotal wireless technology for short-range data exchange between devices, including smartphones and wearables. Leveraging Radio Frequency (RF) signals and robust authentication, NFC ensures secure communication in proximity. Mutual authentication (MA) holds paramount importance for establishing trust between device pairs. A prime example of NFC technology is Radio Frequency Identification (RFID), wherein seamless communication occurs between a reader and a tag. However, security and privacy concerns are critical factors in RFID systems, necessitating effective authentication protocols. This paper introduces an efficient and secure MA mechanism for RFID devices, using lightweight block ciphers (LBCs). Specifically, the extended tiny encryption algorithm (XTEA) and the hummingbird algorithm (HBA) using the cipher block chaining (CBC) mode is designed. These tailored algorithms establish a secure communication channel between RFID tags and readers. Notably, the proposed RFID-MA using XTEA and HBA occupies less than 2% of the chip area, encompassing slices and lookup tables (LUTs), and achieves authentication with execution times of 11.6 mu s and 1.34 mu s, respectively. In comparison to the RFID-MA approach employing the XTEA methodology, the proposed algorithm reduces the chip area overhead by 24.6%, total power consumption by 3.5%, and execution time by 88.36%. The proposed algorithm is implemented using Verilog hardware description language (HDL) within the Xilinx environment and is realized on a Artix-7 field programmable gate array (FPGA) platform, utilizing the ModelSim simulator. The proposed research extensively presents simulation and synthesis results while considering the critical hardware constraints such as time, power, and area. Furthermore, this study has also conducted a comprehensive performance analysis, comparing essential metrics with existing LBC and authentication methodologies, showcasing substanti

关键词： Authentication ciphers cryptography encryption field programmable gate array nearfield communication performance analysis radio frequency identification simulation

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A multi-resolution approach for massively-parallel hardware-friendly optical flow estimation

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JOURNAL OF VISUAL COMMUNICATION AND IMAGE REPRESENTATION 2012年第8期23卷 1272-1283页

作者： Barranco, F. Diaz, J. Pino, B. Ros, E. Univ Granada ETSIIT CITIC Dep Arquitectura & Tecnol Comp E-18071 Granada Spain

This paper presents a novel hardware-friendly motion estimation for real-time applications such as robotics or autonomous navigation. Our approach is based on the well-known Lucas & Kanade local algorithm, whose main problem is the unreliability of its estimations for large-range displacements. This disadvantage is solved in the literature by adding the sequential multiscale-with-warping extension, although it dramatically increases the computational cost. Our choice is the implementation of a multiresolution scheme that avoids the warping computation and allows the estimation of large-range motion. This alternative allows the parallel computation of the scale-by-scale motion estimation which makes the whole computation lighter and significantly reduces the processing time compared with the multiscale-with-warping approach. Furthermore, this last fact also means reducing the hardware resource cost for its potential implementation in digital hardware devices such as GPUs, ASICs, or FPGAs. In the discussion, we analyze the speedup of the multiresolution approach compared to the multiscale-with-warping scheme. For an FPGA implementation, we obtain a reduction of latency between 40% and 50% and a resource reduction of 30%. The final solution copes with large-range motion estimations with a simplified architecture very well-suited for customized digital hardware datapath implementations as well as current multicore architectures. (c) 2012 Elsevier Inc. All rights reserved.

关键词： Image motion analysis Optical flow field programmable gate array Architectures for embedded systems Real-time systems Multiscale-with-warping optical flow Efficient multiresolution optical flow Fusion methods for multiresolution optical flow implementaiton

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GMMSO: game model-combined improved moth search optimization approach for reconfigurable asymmetric multi-processor system-on-chip architecture

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ENGINEERING OPTIMIZATION 2023年第4期55卷 685-702页

作者： Mariyappan, Isaivani Veluchamy, Malathi Anna Univ Dept Elect & Elect Engn Reg Campus Madurai Madurai Tamil Nadu India

Heterogeneous Multi-Processor System-on-Chip architectures are prevalent in modern embedded system applications that target high-performance needs. This work comprises two parts to optimize the multiprocessor system structure concerning system speed, power, and area requirements. The first part includes the game model concept, which is remarkably advantageous in generating strategic decisions on incoming signals and minimizes traffic delays coming from the input portion of the system. Secondly, an improved moth search optimization is proposed to explore the design space and optimize the system space and power consumption. This research is implemented in the field programmable gate array (FPGA) Xilinx Zynq and Virtex platforms and evaluated by ExPRESS benchmarks. The Game Model-combined improved Moth Search Optimization (GMMSO) technique showed performance improvements of 69.34% in delay measurement, 46% in data rate and 36.34% in static power consumption compared with the traditional HMILP (Heuristic Mixed Integer Linear Programming) methods.

关键词： Very large-scale integration multi-processor system-on-chip optimization game model moth search algorithm field programmable gate array

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Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network

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IET CIRCUITS DEVICES & SYSTEMS 2018年第5期12卷 542-550页

作者： Murty, Mahesh S. Shrestha, Rahul Int Inst Informat Technol Hyderabad CVEST Hyderabad Telangana India Indian Inst Technol Mandi SCEE Suran Himachal Prades India

This paper presents reconfigurable and hardware-efficient VLSI architecture of time domain cyclostationary-feature detector (TCD) for spectrum sensing in the cognitive-radio wireless network. It incorporates new architecture for autocorrelator that supports the entire range of subcarriers used by orthogonal frequency division multiplexing signals compliant to 4G LTE-Advanced wireless network. A novel scheme of overflow/underflow protection is proposed for the coordinate rotation digital computer engine of TCD. Additionally, hardware-efficient techniques have been introduced for the multiply-&-accumulate and accumulator architectures of suggested TCD design. Real-world signals are captured using universal software radio peripheral devices and are fed to its FPGA prototype. An application specific integrated circuit synthesis and post-layout simulation of the proposed detector have been performed using 65 nm-CMOS technology and it occupies 0.32 mm(2) of core area and consumes total power of 18.5 mW at 100 MHz clock frequency. In comparison with the state-of-the-art works, the proposed detector requires 34 and 93% lesser hardware resource and memory, respectively.

关键词： spectrum sensor time-domain cyclostationary-feature detector spectrum sensing 4G LTE-Advanced rotation digital computer engine hardware-efficient techniques accumulator architectures performance analysis additive white Gaussian noise channel environment signal-to-noise ratios real-world signals universal software radio peripheral devices application specific integrated circuit synthesis post-layout simulation VLSI design orthogonal frequency division multiplexing OFDM signals multiply-&-accumulate architecture TCD design clock frequency overflow-underflow protection next-generation LTE-A cognitive-radio wireless network hardware-efficient very large-scale integration architecture autocorrelator OFDM-based communication system field programmable gate array FPGA united-microelectronics-corporation complementary metal–oxide–semiconductor technology frequency 1.0 MHz time 5.12 ms size 65.0 nm power 18.5 mW frequency 100.0 MHz Orthogonal frequency division multiplexing application specific integrated circuits field programmable gate arrays Very large scale integration Autocorrelators AWGN channels Wireless networks clock frequency

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Compact energetic light particle detector and spectrometer

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JOURNAL OF SPACECRAFT AND ROCKETS 2004年第5期41卷 862-867页

作者： Green, BD Galica, GE Nakamura, T Sullivan, JD Abe, T Matsumoto, H Koshiishi, H Goka, T Kimoto, Y Phys Sci Inc Andover MA 01810 USA Phys Sci Inc San Ramon CA 94583 USA Boston Univ Boston MA 02215 USA Mitsubishi Electr Corp Kanagawa 247 Japan Mitsubishi Electr Corp Hyogo 6618661 Japan Natl Space Dev Agcy Japan Ibaraki 305 Japan

We have developed a megaelectron-volt class energetic charged-particle spectrometer based on a novel configuration and processing algorithm. The National Space Development Agency of Japan has undertaken a program to develop a particle monitor capable of discriminating and measuring protons in the range from 0.9 to 150 MeV, electrons in the range from 0.5 to >10 MeV and alpha particles >8 MeV, all within a single sensor called the standard dose monitor. The goal is to utilize sensors with nearly identical design and performance on several simultaneous missions to develop a clearer understanding of particle energies and their variability as a function of solar activity, latitude, and altitude. To date, four flight model sensors have been delivered. The sensors are designed to detect accurately the higher-energy particles and high count rates present during active solar periods. In addition, this sensor exhibits extremely efficient discrimination between low-energy electrons and protons. The sensors have been calibrated over nearly their entire particle-energy range. The design is described and calibration data are compared with the results of a Monte Carlo sensor performance model.

关键词： Spectrometers Photomultiplier Tube National Space Development Agency Solar Activity Geostationary Operational Environmental Satellite Combined Release and Radiation Effects Satellite Japanese Experiment Module field programmable gate array Earth Magnetosphere ISS

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On FPGA implementation in medical secret image sharing with data hiding

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MULTIMEDIA TOOLS AND APPLICATIONS 2022年第13期81卷 18755-18781页

作者： Bhattacharjee, Tapasi Maity, Hirak K. Maity, Santi P. Techno Main Salt Lake Dept Informat Technol Sect 5 Kolkata 700091 India Coll Engn & Management Dept Elect & Commun Engn Purba Medinipur 721171 India Indian Inst Engn Sci & Technol Dept Informat Technol PO Bot Garden Sibpur 711103 Howrah India

This work proposes an intelligent integration of secret image sharing (SIS) and data hiding to provide integrity and confidentiality on medical images. An n-variable affine Boolean classification is used to generate the shares from the secret medical image and a modification on difference expansion (DE) is proposed to embed the shares on the cover images. The logical operation in Boolean function and modification in binary priority bit plane for DE operation offer simple computation that enables simple hardware realization in field programmable gate array (FPGA) platform. To implement in hardware, Xilinx ISE design suite 14.5 (device family XC3S50-4PQ208) is used for a secret image of size MxN with 8 bits/pixel. The hardware design offers a maximum frequency of 111.5 MHz and a minimum clock period of 8.965 nanoseconds when the shares of the secret image of size 8x8 is embedded.

关键词： Secret image sharing Data hiding Difference expansion field programmable gate array

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Sparse convolutional neural network acceleration with lossless input feature map compression for resource-constrained systems

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IET COMPUTERS AND DIGITAL TECHNIQUES 2022年第1期16卷 29-43页

作者： Kwon, Jisu Kong, Joonho Munir, Arslan Kyungpook Natl Univ Sch Elect & Elect Engn Daegu 41566 South Korea Kansas State Univ Dept Comp Sci Manhattan KS USA

Many recent research efforts have exploited data sparsity for the acceleration of convolutional neural network (CNN) inferences. However, the effects of data transfer between main memory and the CNN accelerator have been largely overlooked. In this work, the authors propose a CNN acceleration technique that leverages hardware/software co-design and exploits the sparsity in input feature maps (IFMs). On the software side, the authors' technique employs a novel lossless compression scheme for IFMs, which are sent to the hardware accelerator via direct memory access. On the hardware side, the authors' technique uses a CNN inference accelerator that performs convolutional layer operations with their compressed data format. With several design optimization techniques, the authors have implemented their technique in a field-programmable gate array (FPGA) system-on-chip platform and evaluated their technique for six different convolutional layers in SqueezeNet. Results reveal that the authors' technique improves the performance by 1.1x-22.6x while reducing energy consumption by 47.7%-97.4% as compared to the CPU-based execution. Furthermore, results indicate that the IFM size and transfer latency are reduced by 34.0%-85.2% and 4.4%-75.7%, respectively, compared to the case without data compression. In addition, the authors' hardware accelerator shows better performance per hardware resource with less than or comparable power consumption to the state-of-the-art FPGA-based designs.

关键词： accelerator compression convolutional neural networks field programmable gate array input sparsity

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A reconfigurable computing framework for multi-scale cellular image processing

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MICROPROCESSORS AND MICROSYSTEMS 2007年第8期31卷 546-563页

作者： Porter, Reid Frigo, Jan Conti, Al Harvey, Neal Kenyon, Garrett Gokhale, Maya Los Alamos Natl Lab Int Space & Response Technol Div Space Data Syst Grp Los Alamos NM 87545 USA Los Alamos Natl Lab Int Space & Response Technol Div Space & Remote Sensing Sci Grp Los Alamos NM 87545 USA Los Alamos Natl Lab Div Phys Biophys Grp Los Alamos NM 87545 USA Los Alamos Natl Lab Adv Comp Grp Los Alamos NM 87545 USA

Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. These architectures are a good match for many image and video processing applications and can be substantially accelerated with Reconfigurable Computers. We present a flexible software/hardware framework for design, implementation and automatic synthesis of cellular image processing algorithms. The system provides an extremely flexible set of parallel, pipelined and time-multiplexed components which can be tailored through reconfigurable hardware for particular applications. The most novel aspects of our framework include a highly pipelined architecture for multi-scale cellular image processing as well as support for several different pattern recognition applications. In this paper, we will describe the system in detail and present our performance assessments. The system achieved speed-up of at least 100x for computationally expensive sub-problems and 10x for end-to-end applications compared to software implementations. (C) 2006 Elsevier B.V. All rights reserved.

关键词： field programmable gate array reconfigurable computing image processing cellular automata cellular nonlinear network

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FPGA-based Personal Authentication Using Fingerprints

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第2期66卷 153-189页

作者： Fons, Mariano Fons, Francisco Canto, Enrique Lopez, Mariano Univ Rovira & Virgili Dept Engn Elect Elect & Automat Tarragona Spain Univ Politecn Cataluna Dept Elect Engn Vilanova I La Geltru Spain

The current technological age demands the deployment of biometric security systems not only in those stringent and highly reliable fields (forensic, government, banking, etc.) but also in a wide range of daily use consumer applications (internet access, border control, health monitoring, mobile phones, laptops, etc.) accessible worldwide to any user. In order to succeed in the exploitation of biometric applications over the world, it is needed to make research on power-efficient and cost-effective computational platforms able to deal with those demanding image and signal operations carried out in the biometric processing. The present work deals with the evaluation of alternative system architectures to those existing PC (personal computers), HPC (high-performance computing) or GPU-based (graphics processing unit) platforms in one specific scenario: the physical implementation of an AFAS (automatic fingerprint-based authentication system) application. The development of automated fingerprint-based personal recognition systems in the way of compute-intensive and real-time embedded systems under SoPC (system-on-programmable-chip) devices featuring one general-purpose MPU (microprocessor unit) and one run-time reconfigurable FPGA (field programmable gate array) proves to be an efficient and cost-effective solution. The provided flexibility, not only in terms of software but also in terms of hardware thanks to the programmability and run-time reconfigurability performance exhibited by the suggested FPGA device, permits to build any application by means of hardware-software co-design techniques. The parallelism and acceleration performances inherent to the hardware design and the ability of reusing hardware resources along the application execution time are key factors to improve the performance of existing systems.

关键词： Biometrics field programmable gate array Flexible hardware Hardware-software co-design Real-time embedded system Run-time reconfigurable computing

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