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Truncation and Rounding-Based Scalable Approximate Multiplier Design for Computer Imaging Applications

Computers, Materials & Continua 2022年第12期73卷 5169-5184页

作者： S.Rooban A.Yamini Naga Ratnam M.V.S.Ramprasad N.Subbulakshmi R.Uma Mageswari Department of Electronics and Communication Engineering Koneru Lakshmaiah Education FoundationVaddeswaramGuntur522502Andhra PradeshIndia Department of EECE GITAM(Deemed to be University)VisakhapatnamAPIndia Department of Electronics and Communication Engineering Francis Xavier Engineering CollegeTirunelveli627003Tamil NaduIndia 4Department of Computer Science and Engineering Vardhaman College of EngineeringShamshabadHyderabad501218TelanganaIndia

Advanced technology used for arithmetic computing application,comprises greater number of approximatemultipliers and approximate *** and Rounding-based Scalable ApproximateMultiplier(TRSAM)distinguish a variety of modes based on height(h)and truncation(t)as TRSAM(h,t)in the *** TRSAM operation produces higher absolute error in Least Significant Bit(LSB)data shift unit.A new scalable approximate multiplier approach that uses truncation and rounding TRSAM(3,7)is proposed to increase themultiplier *** the help of foremost one bit architecture,the proposed scalable approximate multiplier approach reduces the partial *** proposed approximate TRSAM multiplier architecture gives better results in terms of area,delay,and *** accuracy of 95.2%and the energy utilization of 24.6 nJ is observed in the proposed multiplier *** proposed approach shows 0.11%,0.23%,and 0.24%less Mean Absolute Relative Error(MARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit *** also shows 0.13%,0.19%,and 0.2%less Variance of Absolute Relative Error(VARE)when compared with the existing approach for the input of 8-bit,16-bit,and 32-bit *** proposed approach is implemented with field-programmable gate array(FPGA)and shows the delay of 3.640,6.481,12.505,22.572,and 36.893 ns for the input of 8-bit,16-bit,32-bit,64-bit,and 128-bit *** proposed approach is applied in digital filters designwhich shows the Peak-Signal-to-NoiseRatio(PSNR)of 25.05 dB and Structural Similarity Index Measure(SSIM)of 0.98 with 393 pJ energy consumptions when used in image *** proposed approach is simulated with Xilinx and MATLAB and implemented with FPGA.

关键词： Truncation rounding based scalable approximate multiplier foremost one detector field programmable gate array peak-signal-to-noise-ratio structural similarity index measure

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Design and implementation of a power quality disturbance classifier: An Al approach

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JOURNAL OF INTELLIGENT & FUZZY SYSTEMS 2006年第6期17卷 623-631页

作者： Reaz, M. B. I. Choong, F. Sulaiman, M. S. Mohd-Yasin, F. Multimedia Univ Fac Engn Cyberjaya 63100 Selangor Malaysia

This paper presents a new intelligent system incorporating wavelet transform, artificial neural network and fuzzy logic to automate the classification of power quality disturbance. This novel and efficient method in hardware, based on FPGA technology showed improved performance over existing approaches for power quality disturbance detection and classification on six types of disturbances including sag, swell, transient, fluctuation, interruption and normal waveform. The approach obtained an average classification accuracy of 98.19%. The design was successfully implemented, tested and validated on Altera APEX EP20K200EBC652-1X FPGA utilizing 1209 logic cells and achieved a maximum frequency of 263.71 MHz.

关键词： artificial neural network wavelet transform fuzzy logic power quality field programmable gate array

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FPGA implementation of adaptive p-norm filter for non-stationary power signal parameter estimation

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2020年第2期14卷 206-219页

作者： Nanda, Sarita Pattnaik, Ansuman Dash, Pradipta Kishore KIIT Univ Sch Elect Engn Bhubaneswar Odisha India Siksha O Anusandhan Univ Multidisciplinary Res Cell Bhubaneswar Odisha India

A p-norm extreme learning machine (ELM) based on sparsity constraint is presented in this study for tracking of fundamental frequency, harmonic and dc in current power signals which finds application in phasor measurement units for wide area power network in smart grid environment. Real-time power applications typically are furnished with on-board controller and hence have constraints to stock a complex architecture. Moreover, the data from online practices are polluted by noises of diverse statistical features obtained on a sample-by-sample basis. Hence, approaches with improved learning paradigm and close model dealing with noises of varied statistical characteristics are essential. The proposed approach formulates a cost function with recursive p-norm error criterion and sparsity penalty that updates the output weights in succession besides adjusting some coefficients of the output weights to zeros that promotes quicker convergence and higher accuracy results. Exhaustive computer simulations have been carried out with synthetic signals and real-time signals to track the dynamic changes in the power signal amplitude, phase and frequency that demonstrate the accuracy, efficiency and robustness of the proposed p-norm ELM. Additionally, the new ELM network also is validated on a field programmable gate array (FPGA) hardware to prove its practicability towards current developments on phasor measurement units.

关键词： parameter estimation field programmable gate arrays power engineering computing phase measurement learning (artificial intelligence) smart power grids synthetic signals real-time signals power signal amplitude p-norm ELM ELM network field programmable gate array hardware phasor measurement units FPGA implementation p-norm filter nonstationary power signal parameter estimation p-norm extreme learning machine sparsity constraint fundamental frequency harmonic dc current power signals wide area power network smart grid environment real-time power applications on-board controller complex architecture online practices diverse statistical features sample-by-sample basis improved learning paradigm varied statistical characteristics p-norm error criterion sparsity penalty higher accuracy results recursive p-norm error criterion field programmable gate array

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Design of SSVEP Enhancement-Based Brain Computer Interface

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IEEE SENSORS JOURNAL 2021年第13期21卷 14330-14338页

作者： Lin, Bor-Shing Wang, Hsiao-An Huang, Yao-Kuang Wang, Yu-Lin Lin, Bor-Shyh Natl Taipei Univ Dept Comp Sci & Informat Engn New Taipei 23741 Taiwan Natl Chiao Tung Univ Inst Imaging & Biomed Photon Tainan 71150 Taiwan Chiayi Chang Gung Mem Hosp Div Cardiovasc Surg Puzi City 61363 Chiayi County Taiwan Chi Mei Med Ctr Dept Rehabil Tainan 71004 Taiwan

Brain computer interface (BCI) system is a communication bridge between the brain and the external device, and it has been rapidly developed in the recent years. Here, steady state visually evoked potential (SSVEP) is one of the most frequently used control methods for BCI due to its advantages of low training requirement and high stability. However, some people present unobvious SSVEP feature at the location of the primary visual cortex, and this will reduce the performance of SSVEP-based BCIs. In this study, a novel field programmable gate array (FPGA)-based brain computer interface with SSVEP enhancement is proposed to improve the above issue. In the proposed system, a SSVEP-enhancement active dry electrode is designed to acquire good quality of electroencephalography (EEG) without conductive gels, and further enhance the local EEG signal. The experimental results show the proposed system can effectively improve the signal-to-noise ratio of SSVEP and the information transfer rate. Moreover, compared with the current SSVEP-based BCIs in the previous studies, the proposed BCI system contains the advantages of local EEG enhancement, wearablility, wireless transmission, front-end BCI translation, and it contains the potential of applying in many BCI applications in daily life.

关键词： Electroencephalography Electrodes Pins Metals Skin Brain-computer interfaces Visualization Brain computer interface steady state visually evoked potentials field programmable gate array SSVEP enhancement

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Multiple perspectives on the hardware implementations of biological neuron models and programmable design aspects

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第3期24卷 1729-1746页

作者： Korkmaz, Nimet Ozturk, Ismail Kilic, Recai Erciyes Univ Fac Engn Dept Elect & Elect Engn Kayseri Turkey

A few individual design examples of programmable device-based biological neuron model implementations are available in the literature, but there is no comprehensive study that examines analog and digital programmable design examples of frequently studied biological neuron model implementations. The aim of this paper is to present a comparative study about programmable and reconfigurable implementations of the FitzHugh-Nagumo, Izhikevich, and Hindmarsh-Rose neuron models. Since field programmable analog array (FPAA) and field programmable gate array (FPGA) devices offer several advantages such as flexible design possibilities, reduction of the complexity of design, real-time modification, and software control for programmable and reconfigurable implementations of neuron models and neural structures, they are preferred in these implementations as analog and digital programmable devices. Experimental results agree with the numerical simulations and verify the design effectiveness of FPAA- and FPGA-based implementations.

关键词： Neuron models field programmable analog array field programmable gate array circuit implementation

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FPGA-based entropy neural processor for online detection of multiple combined faults on induction motors

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MECHANICAL SYSTEMS AND SIGNAL PROCESSING 2012年 30卷 123-130页

作者： Cabal-Yepez, E. Valtierra-Rodriguez, M. Romero-Troncoso, R. J. Garcia-Perez, A. Osornio-Rios, R. A. Miranda-Vidales, H. Alvarez-Salas, R. Univ Guanajuato Carr Salamanca Valle Div Ingn HSPdigital CA Telemat Procesamiento Digital Senal Guanajuato 36700 Mexico Univ Autonoma Queretaro Fac Ingn HSPdigital CA Mecatron San Juan Del Rio 76807 Queretaro Mexico Zona Univ Univ Autonoma San Luis Potosi Fac Ingn CA Elect Potencia & Control San Luis Potosi 78290 SLP Mexico

For industry, a faulty induction motor signifies production reduction and cost increase. Real-world induction motors can have one or more faults present at the same time that can mislead to a wrong decision about its operational condition. The detection of multiple combined faults is a demanding task, difficult to accomplish even with computing intensive techniques. This work introduces information entropy and artificial neural networks for detecting multiple combined faults by analyzing the 3-axis startup vibration signals of the rotating machine. A field programmable gate array implementation is developed for automatic online detection of single and combined faults in real time. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： Induction motors Multiple combined faults 3-axis vibration signals Information entropy Artificial neural networks field programmable gate array

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Real-time digital simulation of power electronics systems with Neutral Point Piloted multilevel inverter using FPGA

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ELECTRIC POWER SYSTEMS RESEARCH 2011年第2期81卷 687-698页

作者： Rakotozafy, Mamianja Poure, Philippe Saadate, Shahrokh Bordas, Cedric Leclere, Loic Fac Sci & Tech LIEN F-54506 Vandoeuvre Les Nancy France Fac Sci & Tech GREEN F-54506 Vandoeuvre Les Nancy France CONVERTEAM SAS F-90008 Belfort France

Most of actual real time simulation platforms have practically about ten microseconds as minimum calculation time step, mainly due to computation limits such as processing speed, architecture adequacy and modeling complexities. Therefore, simulation of fast switching converters' instantaneous models requires smaller computing time step. The approach presented in this paper proposes an answer to such limited modeling accuracies and computational bandwidth of the currently available digital *** an example, the authors present a low cost, flexible and high performance FPGA-based real-time digital simulator for a complete complex power system with Neutral Point Piloted (NPP) three-level inverter. The proposed real-time simulator can model accurately and efficiently the complete power system, reducing costs, physical space and avoiding any damage to the actual equipment in the case of any dysfunction of the digital controller prototype. The converter model is computed at a small fixed time step as low as 100 ns. Such a computation time step allows high precision account of the gating signals and thus avoids averaging methods and event compensations. Moreover, a novel high performance model of the NPP three-level inverter has also been proposed for FPGA implementation. The proposed FPGA-based simulator models the environment of the NPP converter: the dc link, the RLE load and the digital controller and gating signals. FPGA-based real time simulation results are presented and compared with offline results obtained using PLECS software. They validate the efficiency and accuracy of the modeling for the proposed high performance FPGA-based real-time simulation approach. This paper also introduces new potential FPGA-based applications such as low cost real time simulator for power systems by developing a library of flexible and portable models for power converters, electrical machines and drives. (C) 2010 Elsevier B.V. All rights reserved.

关键词： field programmable gate array Power electronics Real-time simulation Neutral Point Piloted three-level converter Power system simulation

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Non-linear behavioural modelling of device-level transients for complex power electronic converter circuit hardware realisation on FPGA

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IET POWER ELECTRONICS 2018年第9期11卷 1566-1574页

作者： Lin, Ning Shi, Bo Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB Canada

Detailed device-level models of the insulated-gate-bipolar-transistor (IGBT) and diode are essential for power converter design evaluation for providing insight into circuit and device behaviours, as well as to shorten the design cycle and reduce costs. In this study, the non-linear behavioural models of IGBT and power diode are utilised for emulating the modular multilevel converter (MMC) on the field programmable gate array. For digital hardware-in-the-loop (HIL) emulation, these time-domain continuous models are discretised and linearised prior to being designed into the corresponding hardware modules using the hardware description language VHDL that features a fully paralleled and pipelined implementation. A circuit partitioning approach is adopted according to the MMC structure to enhance computation efficiency and then, detailed information from the system-level performance to the specific features of individual switches is available. HIL emulation and the subsequent comparison with results from the commercial off-line simulation tools prove that the complex IGBT and diode models can be involved in the efficient simulation of large-scale power converters.

关键词： field programmable gate arrays power convertors power semiconductor switches insulated gate bipolar transistors power semiconductor diodes time-domain analysis hardware description languages nonlinear behavioural modelling of device level transient model complex power electronic converter circuit hardware FPGA insulated-gate-bipolar-transistor IGBT power diode modular multilevel converter field programmable gate array digital hardware-in-the-loop emulation HIL emulation time domain continuous model hardware description language VHDL pipelined implementation circuit partitioning approach MMC structure switch

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Very-large-scale integration design of a low-power and cost-effective context-based adaptive variable length coding decoder for H.264/AVC portable applications

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IET IMAGE PROCESSING 2012年第2期6卷 104-114页

作者： Huang, H-J. Fang, C-H. Fan, C-P. Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan Natl Chung Hsing Univ Dept Elect Engn Taichung 402 Taiwan

Context-based adaptive variable length coding (CAVLC) is a new and efficient entropy coding tool in H.264/AVC (advanced video coding). This study proposes a low-power and cost-effective CAVLC decoding architecture for the H.264/AVC baseline profile. Specifically, this study proposes an optimum two-layer power model for the variable length look-up table (VLUT) in the CAVLC decoder, and divides the decoding phase of the LUT into two-layer decoding to reduce power consumption. To achieve a cost-effective design, the proposed design merges common codewords to reduce the hardware cost among different LUTs in the second layer decoding. The proposed decoder is based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m CMOS technology, and was completely verified on a field-programmable gate array (FPGA) emulation platform. The proposed design meets the demands of the real-time CAVLC decoding and reduces power consumption by 44-48% more than previous low-power CAVLD schemes. Finally, the proposed low-power and cost-effective CAVLD design is suitable for H.264/AVC portable applications.

关键词： size 0.18 mum Codes table lookup variable length codes field programmable gate arrays Image and video coding entropy codes CMOS technology context-based adaptive variable length coding decoder entropy coding tool common codewords adaptive codes Logic circuits video coding Logic and switching circuits cost-effective CAVLC decoding variable length look-up table advanced video coding H.264/AVC portable applications two-layer decoding decoding CMOS integrated circuits VLSI Video signal processing Taiwan Semiconductor Manufacturing Company field programmable gate array low-power CAVLC decoding power consumption very large scale integration

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A routability driven technology mapping algorithm for LUT based FPGA designs

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2001年第11期E84A卷 2690-2696页

作者： Kao, CC Lai, YT Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

This paper presents a CAD technology mapping algorithm for LUT-based FPGAs. Since interconnections in an FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. To optimize routability, the goal of the algorithm is the production of a design with a minimum interconnection. The Min-cut algorithm [1]-[3] is first used to partition a graph representing a Boolean network into clusters so that the total number of interconnections between clusters is minimum. To decrease further the number of interconnect ions needed, clusters are then merged into larger clusters by a pairing technique. This algorithm has been tested on the MCNC benchmark circuits. Compared with other LUT-based FPGA mapping algorithms, the algorithm produces better routability characteristics.

关键词： technology mapping routability min-cut field programmable gate array

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