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Hardware Implementation of Reconfigurable 1D Convolution

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2016年第1期82卷 1-16页

作者： Rao, Lei Zhang, Bin Zhao, Jizhong Xi An Jiao Tong Univ Xian 710049 Shaanxi Peoples R China

Convolution has been extensively used in image processing and computer vision, including image enhancement, smoothing, and structure extraction. However, convolution operation typically requires a significant amount of computing resources. A novel one-dimensional (1D) convolution processor with reconfigurable architecture is implemented in this study. This processor is a combination of a line buffer, controller units, as well as a reconfigurable and separable convolution module. The use of a reconfigurable architecture and separable convolution approach improves the flexibility and performance of the convolution processor. The reconfigurable and separable convolution array, which is the main component of the processor, can simultaneously execute convolution operation with different kernels, with a maximum kernel size of up to 24 x 24. Experimental results show that the maximum frames rate of the processor is approximately 194 frames per second (fps), which exceeds the real-time requirement. Synthesis results show that the processor occupies 13.39 mm (2) at a 204 MHz system clock and consumes a power of 419 mW at maximum kernel size at a 120 MHz system clock in SMIC 0.18 mu m CMOS technology. Verification experiments on field programmable gate arrays (FPGAs) demonstrate that the processor is suitable for real-time image processing applications even for high-resolution images.

关键词： Convolution field programmable gate array Reconfigurable architecture

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ROSETTA: A Resource and Energy-Efficient Inference Processor for Recurrent Neural Networks Based on programmable Data Formats and Fine Activation Pruning

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IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING 2023年第3期11卷 650-663页

作者： Kim, Jiho Kim, Tae-Hwan Korea Aerosp Univ Sch Elect & Informat Engn Goyang 10540 Gyeonggi Do South Korea

Recurrent neural networks (RNNs) are extensively employed to perform inference based on the temporal features of the input data. However, their computational workload and power consumption involved in inference are prohibitively high in practice, which may be problematic to achieve a high-speed inference in devices with tight limitations in the available silicon resources and power supply. This paper presents an efficient inference processor for RNNs, named ROSETTA. ROSETTA supports multiple data formats programmable for each vector operand to achieve a wide range or high precision with a limited data size. ROSETTA consistently performs every vector operation based on homogeneous processing units with a high utilization rate. Moreover, ROSETTA skips operations and reduces memory accesses to achieve high energy efficiency by pruning the activation elements in a fine-grained manner. Implemented in a low-cost 28 nm field-programmable gate array, ROSETTA exhibits a resource and energy efficiency as high as 2.51 - 1.14 MOP/s/LUT and 434.01 - 113.29 GOP/s/W, respectively, while producing near-floating-point inference results. The resource and energy efficiency of ROSETTA are higher than those of the previous processor implemented in the same device by up to 206.1% and 304.0%, respectively. The functionality has been verified for several RNN models of various types under a fully-integrated inference system.

关键词： Logic gates field programmable gate arrays Speech recognition Energy efficiency Convolutional neural networks Recurrent neural networks Integrated circuit modeling Accelerator field programmable gate array inference microarchitecture recurrent neural networks

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HopliteRT*: Real-Time NoC for FPGA

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年第11期39卷 3650-3661页

作者： Gonzalez, Yilian Ribot Nelissen, Geoffrey Polytech Inst Porto ISEP CISTER Res Ctr P-4200465 Porto Portugal Eindhoven Univ Technol Dept Math & Comp Sci NL-5612 AZ Eindhoven Netherlands

With the increasing number of computation nodes integrated in multi and many-core platforms, network-on-chips (NoCs) emerged as a new communication medium in systems-on-chips (SoCs). HopliteRT is a new NoC design that was recently proposed to address the needs of real-time systems whilst respecting the constraints of field-programmable gate array (FPGA) platforms. In this article, we: 1) introduce priority-based routing in HopliteRT;2) change the network topology in order to improve the packets' worst-case traversal time (WCTT);3) identify a flaw in the existing timing analysis of HopliteRT;and 4) develop a new timing analysis that is proven correct. We also show by means of experiments that the modifications of HopliteRT proposed in this article allows for at least 2x improvement on the worst and average case traversal time of high priority packets, without impacting the quality of service of low-priority packets. The timing properties of high priority flows are greatly improved for negligible additional hardware costs. The proposed NoC has been implemented in Verilog and synthesized for a Xilinx Virtex-7 FPGA platform.

关键词： field programmable gate array network-onchips real-time embedded systems systems-on-chips timing analysis

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Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on programmable Logic Element With Nonvolatile Shadow Register

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2015年第9期50卷 2199-2211页

作者： Aoki, Takeshi Okamoto, Yuki Nakagawa, Takashi Kozuma, Munehiro Kurokawa, Yoshiyuki Ikeda, Takayuki Yamade, Naoto Okazaki, Yutaka Miyairi, Hidekazu Fujita, Masahiro Koyama, Jun Yamazaki, Shunpei Semicond Energy Lab Co Ltd Atsugi Kanagawa 2430036 Japan Univ Tokyo VDEC Tokyo 1130032 Japan

Normally-off computing (Noff computing) using a multicontext field programmable gate array (MC-FPGA) consisting of crystalline oxide semiconductor FETs has been developed. The Noff computing discussed in this paper is a control architecture for an MC-FPGA capable of performing fine-grained power gating on each programmable logic element (PLE) whose registers include a volatile register and also a nonvolatile shadow register for storing and loading data in the volatile register. The MC-FPGA performs fine-grained control of power supplied only to PLEs contributing to effective calculation, when context switching happens. With an MC-FPGA fabricated with a hybrid process of a 1.0 mu m crystalline oxide semiconductor FET on a 0.5 mu m CMOS FET, it has been confirmed that the proposed Noff computing can resume the previous task when a context switches back to it, increases PLE use efficiency, and reduces the power consumption by 27.7% at operating frequencies of 20 MHz with a driving voltage of 2.5 V.

关键词： CAAC-IGZO crystalline IGZO crystalline oxide semiconductor field programmable gate array multicontext nonvolatile memory normally-off computing oxide semiconductor power gating shadow register

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Systemic approach explored in the context of passive target tracking

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IET SIGNAL PROCESSING 2010年第3期4卷 314-323页

作者： Totir, F. Ioana, C. Serbanescu, A. Stopin, J. Anton, L. Stankovic, S. Mil Tech Acad Bucharest 050141 Romania INPG GIPSA Lab F-38402 St Martin Dheres France Univ Montenegro Podgorica 81000 Montenegro

For obvious reasons of cost, discretion and reliability costs, locating and tracking aerial targets under an electromagnetically completely passive paradigm, relying exclusively on illuminators of opportunity, is very appealing not only for military but also for civilian tasks. Such a passive radar system could exploit signals emitted by existing commercial television or radio stations or even satellite signals, such as the ones belonging to the global positioning system. This study considers target locating and tracking using a network of passive receivers and/or non-cooperative illuminators (a multi-static radar configuration) by making use of the Doppler shift only. A concept, the systemic approach, is used to combine and interpret information available from different sensors. Both the formalisation of the problem and the hardware and software implementation are presented. Implementation makes use of multi-component polynomial-phase signal models and genetic algorithms. For increased performance, implementation on field programmable gate array is envisaged.

关键词： passive radar system radar signal processing satellite signals global positioning system reliability costs field programmable gate array target locating discretion costs multicomponent polynomial-phase signal models target tracking Optimisation techniques Radar equipment, systems and applications Signal processing and detection genetic algorithms passive target tracking

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GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs

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IEEE TRANSACTIONS ON COMPUTERS 2018年第3期67卷 375-387页

作者： Wild, Alexander Moradi, Amir Gueneysu, Tim Ruhr Univ Bochum Horst Gortz Inst IT Secur D-44801 Bochum Germany Univ Bremen German Res Ctr Artificial Intelligence D-28359 Bremen Germany

Designers of secure hardware are required to harden their implementations against physical threats, such as power analysis attacks. In particular, cryptographic hardware circuits need to decorrelate their current consumption from the information inferred by processing (secret) data. A common technique to achieve this goal is the use of special logic styles that aim at equalizing the current consumption at each single processing step. However, since all hiding techniques like Dual-Rail Precharge (DRP) were originally developed for ASICs, the deployment of such countermeasures on FPGA devices with fixed and predefined logic structure poses a particular challenge. In this work, we propose and practically evaluate a new DRP scheme (GliFreD) that has been exclusively designed for FPGA platforms. GliFreD overcomes the well-known early propagation issue, prevents glitches, uses an isolated dual-rail concept, and mitigates imbalanced routings. With all these features, GliFreD significantly exceeds the level of physical security achieved by any previously reported, related countermeasures for FPGAs.

关键词： Dual-rail precharge logic field programmable gate array side-channel attack power analysis power-equalization hiding

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FPGA-Accelerated Quantum Computing Emulation and Quantum Key Distillation

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IEEE MICRO 2021年第4期41卷 49-57页

作者： Li, He Pang, Yaru Univ Cambridge Cambridge CB2 1TN England UCL London WC1E 6BT England

In the past decades, field-programmable gate arrays (FPGAs) have demonstrated an interesting physical platform to facilitate quantum information processing, particularly in the emergence of domain-specific hardware accelerators for quantum computing emulation and quantum key distillation. While conventional general-purpose hardware platforms have been used for quantum information processing, FPGAs promise deep pipeline parallelism, adaptable interface, and trivial support for custom-precision operation. Therefore, the time is ripe for describing recent development of quantum computing emulators and quantum key distillation accelerators on FPGAs. In this article, we provide a comprehensive review of the state-of-the-art in this active field, with a balance between theoretical, implementational, and technological results. Challenges and promising research opportunities are also discussed.

关键词： field programmable gate arrays Quantum Computing Quantum Cryptography Quantum Information Processing FPG As Quantum Computing Emulators Quantum Key Distillation Accelerators FPGA Accelerated Quantum Computing Emulation field programmable gate arrays Interesting Physical Platform Domain Specific Hardware Accelerators General Purpose Hardware Platforms Qubit Logic gates Quantum Computing field programmable gate arrays Hardware Computational Modeling Process Control field programmable gate array Quantum Information Processing Hardware Emulation

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Indirect sliding mode power control for three phase grid connected power converter

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IET POWER ELECTRONICS 2015年第6期8卷 977-985页

作者： Hemdani, Asma Dagbagi, Mohamed Naouar, Wissem Mohamed Idkhajine, Lahoucine Belkhodja, Ilhem Slama Monmasson, Eric Univ Tunis El Manar Ecole Natl Ingn Tunis Lab Syst Elect LR11ES15 Tunis 1002 Tunisia SATIE IUP GEII F-95031 Cergy Pontoise France

Grid connected power converters are widely used to interface between grid - on one side- and loads or renewable energy sources - on the other side. This work presents an indirect sliding mode power control (ISMPC) for three phase grid connected power converter. This control is characterised by improved robustness with regard to external disturbances and parameters changes, while insuring at the same time low current total harmonic distortion factor. The development and implementation of the ISMPC algorithm on low cost Microsemi SmartFusion digital solution is also described. This digital solution includes in the same chip a field programmable gate array (FPGA) fabric and a Cortex-M3 processor associated to large number of peripheral cores. The developed ISMPC is compared with standard and commonly used controls for grid connected converters to show its interest and advantages. Moreover, an overview of the experimental set-up, the description of the algorithm modular partitioning between FPGA and processor, the resources optimisation as well as the execution time reduction are presented. Selected experimental results corresponding to different operation steps are presented to illustrate performances and effectiveness of the proposed ISMPC algorithm.

关键词： variable structure systems power control power grids power convertors renewable energy sources harmonic distortion digital control field programmable gate arrays optimisation robust control indirect sliding mode power control three phase grid connected power converter ISMPC renewable energy source current total harmonic distortion factor Microsemi SmartFusion digital solution field programmable gate array FPGA Cortex-M3 processor modular partitioning resource optimisation execution time reduction

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FPGA implementation of NN based LMS-LMF control algorithm in DSTATCOM for power quality improvement

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CONTROL ENGINEERING PRACTICE 2020年 98卷 104378-000页

作者： Malathi, S. Jayachandran, J. SASTRA Deemed Univ Dept Elect & Elect Engn Thanjavur 613401 Tamil Nadu India

Neural Network (NN) based Least Mean Square (LMS)-Least Mean Fourth (LMF) control technique is developed and implemented in field programmable gate array (FPGA) for Shunt Active Power Filter (SAPF) to enhance Power Quality (PQ) in three-phase four wire distribution system. The PQ enhancement comprises the improvement of power factor, mitigation of harmonics and compensation of reactive power. The proposed control strategy is simulated in MATLAB/Simulink to determine the reference source currents and weights of active and reactive components. The simulation results of LMS-LMF control are compared with the other three control strategies. The NN control is developed as individual modules in FPGA. Thus it can be configured to any other research area which has identical requirements. The FPGA implementation overcomes the drawback of conventional controllers with a fast and accurate response. The FPGA based proposed control strategy for SAPF is developed as a laboratory prototype and the results obtained are analyzed. The results attained adhere to power quality standards.

关键词： Neural network Shunt active power filter Total harmonic distortion field programmable gate array Power quality

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Low Complexity Digital Quadrature Oscillators for Variable Frequency Applications

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2024年第9期71卷 10475-10485页

作者： Sengupta, Arkadeb Shahu, Vihan Kundu, Utsab John, Vinod Univ Kiel Chair Power Elect D-24143 Kiel Germany Indian Inst Sci Dept Elect Engn Bengaluru 560012 India

Switching frequency is utilized as a degree of freedom in digital control strategies for power converters. In addition to carrier-based schemes, quadrature oscillators offer an alternative method for the generation of variable frequency switching pulses. In this article, amplitude instability in a computationally simple digital quadrature oscillator is analyzed. Algorithms for stabilizing the oscillator are developed based on this. Further implementation issues arising are addressed and a systematic comparison to carrier-based schemes is executed. It is shown that the proposed approach can be implemented with only four additions and four comparison steps without resorting to multiplication. The studies are validated in system simulation and experiments on a commercial field programmable gate array board.

关键词： Amplitude stabilization field programmable gate array integrator discretization quadrature oscillator second order generalized integrator

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