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Signal processing at 250 MHz using high-performance FPGA's

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1998年第2期6卷 238-246页

作者： Von Herzen, B Rapid Prototypes Inc Carson City NV 89701 USA

This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250-MHz cross correlator for radio astronomy. Experimental results indicate that complementary metal-oxide-semiconductor (CMOS) field programmable gate arrays (FPGA's) can per form useful computation at 250 MHz. The notion of an "event horizon" for FPGA's leads to clear design constraints for highspeed application developers, and can be applied to a variety of real-time signal processing algorithms. Recent estimates indicate that higher performance FPGA's available early in 1998 can attain speeds of over 300 MHz using 20% fewer logic elements than current designs. The results of this design work provide important clues on how to improve FPGA architectures for signal processing at hundreds of MHz. Direct routing channels between logic elements can significantly increase performance. Routing architectures with four-way symmetry allow for rotations and reflections of subcircuits needed for optimal packing density. Experimental results indicate that clock buffering often limits the top speed of the FPGA. Wave pipelining of clock distribution network may improve FPGA performance.

关键词： correlators event horizon field programmable gate array manual partitioning and placement programmable logic real-time signal processing

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A Novel Ergodic Cellular Automaton Model of Gene-Protein Network: Theoretical Nonlinear Analyses and Efficient FPGA Implementation

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IEEE ACCESS 2023年 11卷 300-312页

作者： Shirafuji, Shogo Torikai, Hiroyuki Hosei Univ Grad Sch Sci & Engn Koganei Tokyo 1848584 Japan

A novel ergodic cellular automaton model of gene-protein network is presented. It is shown that the presented model can predict occurrences of typical nonlinear phenomena of a conventional ordinary differential equation gene-protein network model. In addition, theoretical analysis methods of the presented model are proposed. Using the analysis methods, an important advantage of the presented model is revealed: the ergodic cellular automaton is better suited to predict the occurrences of the nonlinear phenomena of the differential equation gene-protein network model compared to a regular (standard) cellular automaton. Furthermore, the presented model is implemented by a field programmable gate array and experiments validate its operations. It is then revealed that the presented model is much more hardware-efficient compared to a standard numerical integration formula of the differential equation model.

关键词： Integrated circuit modeling Biological system modeling Mathematical models Automata Bifurcation Orbits Computational modeling Gene-protein network cellular automaton nonlinear dynamics bifurcation phenomena field programmable gate array

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Partitioning sequential circuits on dynamically reconfigurable FPGAs

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IEEE TRANSACTIONS ON COMPUTERS 1999年第6期48卷 565-578页

作者： Chang, D Marek-Sadowska, M Everest Design Automat Fremont CA 94538 USA Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and interconnect are time-multiplexed. Thus. for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a different time. In this paper, the partitioning of sequential circuits for execution on a DRFPGA is studied. To determine how to correctly partition a sequential circuit and what are the costs in doing so, we propose a new gate-level model that handles time-multiplexed computation. We also introduce an enchanced force directed scheduling (FDS) algorithm to partition sequential circuits that finds a correct partition with low logic and communication costs, under the assumption that maximum performance is desired. We use our algorithm to partition seven large ISCAS '89 sequential benchmark circuits. The experimental results show that the enhanced FDS reduces communication costs by 27.5 percent with only a 1.1 percent increase in the gate cost compared to traditional FDS.

关键词： dynamically reconfigurable FPGAs field programmable gate array reconfigurable computing partitioning sequential circuit time-multiplexed FPGA Dharma DPGA force directed scheduling

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Accelerating Deep Neuroevolution on Distributed FPGAs for Reinforcement Learning Problems

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ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS 2021年第2期17卷 p1-17页

作者： Asseman, Alexis Antoine, Nicolas Ozcan, Ahmet S. IBM Almaden Res Ctr 650 Harry Rd San Jose CA 95120 USA

Reinforcement learning, augmented by the representational power of deep neural networks, has shown promising results on high-dimensional problems, such as game playing and robotic control. However, the sequential nature of these problems poses a fundamental challenge for computational efficiency. Recently, alternative approaches such as evolutionary strategies and deep neuroevolution demonstrated competitive results with faster training time on distributed CPU cores. Here we report record training times (running at about 1 million frames per second) for Atari 2600 games using deep neuroevolution implemented on distributed FPGAs. Combined hardware implementation of the game console, image preprocessing and the neural network in an optimized pipeline, multiplied with the system level parallelism enabled the acceleration. These results are the first application demonstration on the IBM Neural Computer, which is a custom designed system that consists of 432 Xilinx FPGAs interconnected in a 3D mesh network topology. In addition to high performance, experiments also showed improvement in accuracy for all games compared to the CPU implementation of the same algorithm.

关键词： Genetic algorithm field programmable gate array neuroevolution reinforcement learning artificial neural network

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Two-channel control of three-phase inverters for distortion reduction

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IET POWER ELECTRONICS 2013年第1期6卷 192-201页

作者： Padmavathi, Lakshmanan Janakiraman, Panapakkam Arumugam Cardiff Univ Sch Engn Inst Energy Cardiff CF10 3AX S Glam Wales IIT Madras Madras Tamil Nadu India

A new two-phase, independent control strategy for three-phase three-wire static inverters to reduce unbalance in output voltage is proposed. The three-phase voltage and current signals are processed by the ideal Clarke transform block to yield two single-phase signals, which contain information regarding unbalance and harmonics which may be present in the three-phase signals. If the two single-phase voltage signals could be controlled so that they become equal in magnitude with a phase shift of 90 degrees (ideal alpha beta signals), then the corresponding terminal three-phase voltage signals would become balanced. Single-phase observers are employed to control the fundamental components in the two identical d-q frames created. Simultaneously, when the harmonics are eliminated in the two single-phase channels, the corresponding three-phase voltage signals would become distortion free. Feed-forward compensation can be carried out using the equivalent series-impedance parameters, estimated on-line using a simple identification algorithm. This procedure is not sensitive to frequency and can take care of the voltage drop in the distribution transformer. The simulation and experimental results for a field programmable gate array (FPGA) controlled 60 V table top inverter fabricated in the laboratory are provided.

关键词： feedforward field programmable gate arrays observers power system control PWM invertors two-channel control distortion reduction two-phase independent control strategy three-phase three-wire static inverters current signals ideal Clarke transform block single-phase voltage signals phase shift single-phase observers single-phase channels three-phase voltage signals feed-forward compensation equivalent series-impedance parameters identification algorithm voltage drop distribution transformer field programmable gate array voltage 60 V

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Efficient FPGA-based VLSI architecture for detecting R-peaks in electrocardiogram signal by combining Shannon energy with Hilbert transform

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IET SIGNAL PROCESSING 2018年第6期12卷 748-755页

作者： Kumar, Madam Aravind Chari, Kamsali Manjunatha GVVIT Engn Coll Elect & Commun Engn Betapoodi Andhra Prades India GITAM Univ Elect & Commun Engn Visakhapatnam Andhra Prades India

Electrocardiogram (ECG) is a critical application in light of R-peak detection. The R-peaks are impacted by some QRS complex and noises in the current method. Basic testability, snappier execution, and confirmation choices are accomplished by the utilization of the field programmable gate array (FPGA). But, FPGA execution gives less accuracy. To battle execution trouble, another R-peak detector is proposed and relying upon the propelled peak finding logic, which incorporates a Bandpass filter and first-order differentiation process, which are done in the primary phase of the strategy. The noises in the input ECG signal are decreased in the first stage. In the subsequent stage, the smooth Shannon energy envelope (SEE) is acquired by utilizing SEE extraction and the zero phases filtering process. The false R peak is stifled by proposing a Hilbert transform (HT) in the third stage. The HT requires more hardware space and high-power utilization in the current technique. Due to this reason, Real valued Fast Fourier Transform (RFFT) and Inverse RFFT (IRFFT) techniques are proposed in the HT. In the fourth stage, R-peak acknowledgment is evaluated using Massachusetts Institute of Technology, Beth Israel Hospital (MIT-BIH) arrhythmia database and produced the average accuracy of 99.86%, sensitivity of 99.95% and the positive predictivity of 99.90%.

关键词： field programmable gate arrays biomedical electronics VLSI medical signal detection medical signal processing electrocardiography Hilbert transforms band-pass filters fast Fourier transforms feature extraction inverse transforms FPGA-based VLSI architecture R-peak detection electrocardiogram signal Shannon energy Hilbert transform snappier execution ECG QRS complex confirmation choices field programmable gate array R-peak pointer propelled peak finding logic bandpass filter first-order differentiation process smooth Shannon energy envelope SEE extraction zero phases filtering process high-power utilisation hardware space real valued fast Fourier transform strategy RFFT inverse RFFT techniques MIT-BIH arrhythmia database

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FPGA-based Fused Smart Sensor for Real-Time Plant-Transpiration Dynamic Estimation

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SENSORS 2010年第9期10卷 8316-8331页

作者： Roberto Millan-Almaraz, Jesus de Jesus Romero-Troncoso, Rene Gerardo Guevara-Gonzalez, Ramon Miguel Contreras-Medina, Luis Valentin Carrillo-Serrano, Roberto Alfredo Osornio-Rios, Roque Duarte-Galvan, Carlos Angel Rios-Alcaraz, Miguel Torres-Pacheco, Irineo Univ Autonoma Queretaro CA Ingn Biosistemas Div Investigac & Posgrado Fac Ingn Queretaro 76010 Qro Mexico Univ Guanajuato HSPdigital CA Telemat DICIS Salamanca 36885 Gto Mexico Univ Autonoma Queretaro HSPdigital CA Mecatron Fac Ingn San Juan Del Rio 76807 Qro Mexico Univ Autonoma Queretaro Div Investigac & Posgrado Fac Ingn Queretaro 76010 Qro Mexico

Plant transpiration is considered one of the most important physiological functions because it constitutes the plants evolving adaptation to exchange moisture with a dry atmosphere which can dehydrate or eventually kill the plant. Due to the importance of transpiration, accurate measurement methods are required;therefore, a smart sensor that fuses five primary sensors is proposed which can measure air temperature, leaf temperature, air relative humidity, plant out relative humidity and ambient light. A field programmable gate array based unit is used to perform signal processing algorithms as average decimation and infinite impulse response filters to the primary sensor readings in order to reduce the signal noise and improve its quality. Once the primary sensor readings are filtered, transpiration dynamics such as: transpiration, stomatal conductance, leaf-air-temperature-difference and vapor pressure deficit are calculated in real time by the smart sensor. This permits the user to observe different primary and calculated measurements at the same time and the relationship between these which is very useful in precision agriculture in the detection of abnormal conditions. Finally, transpiration related stress conditions can be detected in real time because of the use of online processing and embedded communications capabilities.

关键词： smart sensor transpiration stomatal conductance precision agriculture phytomonitoring water stress field programmable gate array

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Design and Implementation of Special-Purpose Computer for Incoherent Digital Holography

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IEEE ACCESS 2022年 10卷 76906-76912页

作者： Hara, Takayuki Kakue, Takashi Shimobaba, Tomoyoshi Ito, Tomoyoshi Chiba Univ Grad Sch Engn Chiba 2638522 Japan Natl Inst Technol Nagano Coll Dept Engn Nagano 3818550 Japan

We designed and implemented a special-purpose computer for incoherent digital holography for application in three-dimensional (3D) microscopy. We focused on multiwavelength-multiplexed phase-shifting incoherent color digital holography as a method for acquiring 3D color-reconstructed images. This method records holograms faster than conventional temporal division methods. However, the reconstruction calculation of this method requires a significant amount of time, similar to the conventional method. Therefore, we designed a circuit for high-speed image reconstruction. We designed a Fresnel diffraction circuit that requires repetitive calculations to obtain a 3D color image but incurs a high calculation cost. We implemented the circuit on a field-programmable gate array (FPGA) and successfully calculated reconstructed images that were of the same quality as those calculated by the central processing unit (CPU) of a personal computer (PC). The calculation time was approximately 2.6 times faster than that of the CPU.

关键词： Image reconstruction Holography Three-dimensional displays Optical diffraction Diffraction Optical imaging Image color analysis Digital holography incoherent holography field programmable gate array

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An FPGA-Based electronic cochlea

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EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING 2003年第7期2003卷 629-638页

作者： Leong, MP Jin, CT Leong, PHW Chinese Univ Hong Kong Dept Comp Sci & Engn Shatin Hong Kong Peoples R China Univ Sydney Dept Elect & Informat Engn Sydney NSW 2006 Australia

A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed-point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

关键词： field programmable gate array electronic cochlea VHDL modules

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A parallel Viterbi decoder for block cyclic and convolution codes

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SIGNAL PROCESSING 2006年第2期86卷 273-278页

作者： Reeve, JS Amarasinghe, K Univ Southampton Dept Elect & Comp Sci Southampton SO17 1BJ Hants England

We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from any processor cannot exceed four for BCH codes. The resulting algorithm works in lock step making it suitable for implementation on a systolic processor array, which we have implemented on a field programmable gate array and have demonstrated the perfect scaling of the algorithm for two exemplar BCH codes. The parallelisation strategy is applicable to all cyclic codes and convolution codes. We also present a novel method for generating the state transition diagrams for these codes. (C) 2005 Elsevier B.V. All rights reserved.

关键词： Viterbi decoding BCH codes field programmable gate array parallel algorithms

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