In this paper, a new design and flexible energy management strategy are presented for microgrids. The proposed intelligent energy management system (IEMS) achieves effective integration between the resilient microcont...
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In this paper, a new design and flexible energy management strategy are presented for microgrids. The proposed intelligent energy management system (IEMS) achieves effective integration between the resilient microcontroller, chosen for its rapid response speed and its capability to perform multiple operations simultaneously, and the optimization techniques to enhance the power quality. The IEMS is designed using the FPGA board, chosen for its flexibility and capability to handle multiple and complex operations simultaneously. The experimental testing of the IEMS demonstrates a significant level of effectiveness in managing energy. To enhance system performance and ensure cost-effective reliability, advanced optimization techniques are employed. This study deals with a complex multi-objective optimization problem involving the limitations of energy generation, load demand, and a hydrogen-battery hybrid energy storage system. The moth-flame optimization (MFO) algorithm is chosen to solve this optimization problem due to its rapid convergence rate and accuracy. The effectiveness of the MFO algorithm is assessed by comparing it with several new algorithms. The obtained results show the robust performance of the IEMS and its high responsiveness to dynamic operational scenarios. It can observe, gather, and analyze data in real-time. It achieves a remarkable 1.287 % reduction in operating costs within a short timeframe.
We propose a dynamic parameter decoding algorithm for polar turbo product codes (polar-TPC), obtaining performance gains of up to 0.1 dB without additional complexity. Employing field programmable gate array (FPGA) em...
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ISBN:
(纸本)9781665481557
We propose a dynamic parameter decoding algorithm for polar turbo product codes (polar-TPC), obtaining performance gains of up to 0.1 dB without additional complexity. Employing field programmable gate array (FPGA) emulations, the performance of polar-TPC at ultra-low bit error rate (BER) is verified. In addition, we construct a 16.7% concatenated polar-TPC and Reed-Solomon (RS) code with a pre-forward-error-correction BER of 2.05x10(-2), applicable to optical fiber communications.
For a current measurement with the goals of a high bandwidth and a high sampling rate, a filter with minimal phase shift is proposed. The filter is analytically derived using the differential equation of an induction ...
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ISBN:
(纸本)9789075815399
For a current measurement with the goals of a high bandwidth and a high sampling rate, a filter with minimal phase shift is proposed. The filter is analytically derived using the differential equation of an induction machine (IM) model and is based on the difference in the stator current behaviour of machines with and without iron losses. To use this filter, only two parameters need to be set.
This article describes rapid prototyping using the Xilinx system generator (XSG) of a direct field oriented control (DFOC) strategy based on improved super twisting sliding mode controllers (ISTSMCs) of an asynchronou...
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This article describes rapid prototyping using the Xilinx system generator (XSG) of a direct field oriented control (DFOC) strategy based on improved super twisting sliding mode controllers (ISTSMCs) of an asynchronous machine to succeed a hardware implementation on a field programmable gate array (FPGA) board. The main goal is to enhance regulation loops governing rotor speed, rotor flux, and stator current components within the classical DFOC structure. These ISTSMCs replace integral proportional controllers, resulting in improved system dynamics, faster speed and torque responses, and heightened robustness against load and rotor resistance variations, surpassing other control methods. Additionally, the article aims to implement this DFOC-ISTSMC method on an FPGA board to reduce control system sampling time and loop delays, leveraging the FPGA's parallel processing capabilities. The hardware architecture is designed using XSG in the MATLAB/Simulink environment, enabling effective simulation, testing, discrete algorithm creation, and VHDL code generation for FPGA implementation via the hardware-in-the-loop (HIL) process. Assessment involves digital simulation studies and HIL processes using XSG with a Xilinx FPGA Zynq 7000 under MATLAB/Simulink, demonstrating improved system performance, reduced time delays, and efficient FPGA utilization. This approach validates the effectiveness of the proposed DFOC-ISTSMC algorithm in enhancing control strategy for asynchronous machines.
Atomic-scale imaging using scanning probe microscopy is a pivotal method for investigating the morphology and physico-chemical properties of nanostructured surfaces. Time resolution represents a significant limitation...
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Atomic-scale imaging using scanning probe microscopy is a pivotal method for investigating the morphology and physico-chemical properties of nanostructured surfaces. Time resolution represents a significant limitation of this technique, as typical image acquisition times are on the order of several seconds or even a few minutes, while dynamic processes-such as surface restructuring or particle sintering, to be observed upon external stimuli such as changes in gas atmosphere or electrochemical potential-often occur within timescales shorter than a second. In this article, we present a fully redesigned field programmable gate array (FPGA)-based instrument that can be integrated into most commercially available standard scanning probe microscopes. This instrument not only significantly accelerates the acquisition of atomic-scale images by orders of magnitude but also enables the tracking of moving features such as adatoms, vacancies, or clusters across the surface ("atom tracking") due to the parallel execution of sophisticated control and acquisition algorithms and the fast exchange of data with an external processor. Each of these measurement modes requires a complex series of operations within the FPGA that are explained in detail.
Heterogeneous coexistence of multiple attractors was exhibited by a two-dimensional (2-D) non-autonomous model of adaptive synapse neuron with external excitation. Considering that electromagnetic induction (EMI) is a...
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Heterogeneous coexistence of multiple attractors was exhibited by a two-dimensional (2-D) non-autonomous model of adaptive synapse neuron with external excitation. Considering that electromagnetic induction (EMI) is an unavoidable interference in the electrophysiological environment, and memristors are often used to simulate the EMI induced by neuron membrane potentials, can the memristive EMI current be used instead of the external excitation current in the 2-D non-autonomous adaptive synapse neuron model? To this end, this paper proposes a three-dimensional (3-D) autonomous model of memristor-based adaptive synapse neuron (MASN) considering EMI. The MASN model has extremely many equilibrium points with complicated stability evolutions, resulting in the heterogeneous coexistence of extremely many attractors. The heterogeneously coexisting behaviors of the MASN model are investigated through some numerical methods, and the globally coexisting bifurcation behaviors, initials-relied kinetic distributions, and initials-sensitive riddled basins of attraction are thereby demonstrated. Furthermore, based on field programmable gate array (FPGA) platform, the MASN model is digitally implemented and the correctness of the numerical results is verified by hardware experiments.
Automatic ship detection from spaceborne systems such as satellites or aircrafts, raises considerable attention in sea surface monitoring because of the several applications in military and civilian field. In this con...
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Automatic ship detection from spaceborne systems such as satellites or aircrafts, raises considerable attention in sea surface monitoring because of the several applications in military and civilian field. In this context, processing satellite images on-board would reduce the latency time especially for emergency situations. In this paper, an hardware-oriented (HO) ship detection system based on a customized Convolutional Neural Network (CNN), here referred to as HO-ShipNet, , is proposed and tested on a revised version of the "Ships in Satellite Imagery"(SSI) Kaggle dataset, reporting detection accuracy of up to 95%. Furthermore, the explainability of HO-ShipNet is investigated by means of explainable Artificial Intelligence (xAI) techniques (i.e., Local Interpretable Model-Agnostic Explanation (LIME) and Occlusion Sensitivuty Analysis (OSA)), in order to understand the reasoning behind the HO-ShipNet decisions by detecting the most important input features and consequently ensure the trustworthiness of the model itself. Finally, HO-ShipNet is also implemented on the heterogeneous Xilinx xc7z045ffg900-2 SoC field programmable gate array (FPGA) outperforming stateof-the-art FPGA-based accelerators dealing with high-resolution frames. The promising results encourage the potential deployment of the proposed system for on-board applications.
The field of motor drive makes extensive use of electronic power modeling and simulation of three-phase IGBT full-bridge inverter circuits. The accuracy and computational efficiency of these models have a direct impac...
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The field of motor drive makes extensive use of electronic power modeling and simulation of three-phase IGBT full-bridge inverter circuits. The accuracy and computational efficiency of these models have a direct impact on the dependability of the motor control system. The majority of earlier research focused solely on static processes of turning on and off in IGBTs, disregarding the transient proesses that occur when three-phase IGBT full-bridge inverter circuits are switched at high frequencies. This has an impact on the circuits' accuracy in real-time simulation. Therefore, this paper proposes and builds a field-programmable logic gatearray (FPGA)-based steady-state and transient dual-phase three-phase IGBT full-bridge inverter circuit model for the static and transient characteristics of the insulated gate bipolar transistor (IGBT) element in the circuit. Depending on whether or not the switching states of the six IGBTs in the three-phase IGBT fullbridge inverter circuit are altered, the simulation process is split into steady state and transient phases. In the steady state phase with large step size, the circuit is d iscretized using the binary L/ C approach. In the transient phase, the transient process is divided into several small-step-long time domains. Real-time simulation waveforms are generated by interleaving and combining the multistage fitting method's solution of the circuit's transient waveforms at tiny step lengths with the steady state phase. Finally, in order to demonstrate the accuracy of the circuit model in this work, the simulation results of the two-stage three-phase IGBT full-bridge inverter circuit model based on FPGA are compared with those of the conventional ideal model for waveform comparison and data analysis.
In contemporary warfare, radar countermeasures have become multifunctional and intelligent, rendering the conventional jamming method and platform unsuitable for the modern radar countermeasures battlefield due to the...
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In contemporary warfare, radar countermeasures have become multifunctional and intelligent, rendering the conventional jamming method and platform unsuitable for the modern radar countermeasures battlefield due to their limited efficiency. Reinforcement learning has been proven to be a practical solution for cognitive jamming decision-making in the cognitive electronic warfare. In this paper, we proposed a radar-jamming decision-making algorithm based on an improved Q-Learning algorithm. This improved Q-Learning algorithm ameliorated the problem of overestimating the Q-value that exists in the Q-Learning algorithm by introducing a second Q-table. At the same time, we performed a comprehensive design and implementation based on the classical Q-Learning algorithm, deploying it to a field programmable gate array (FPGA) hardware. We decomposed the implementation of the reinforcement learning algorithm into individual steps and described each step using a hardware description language. Then, the reinforcement learning algorithm can be computed on FPGA by linking the logic modules with valid signals. Experiments show that the proposed Q-Learning algorithm obtains considerable improvement in performance over the classical Q-Learning algorithm. Additionally, they confirm that the FPGA hardware can achieve great efficiency improvement on the radar-jamming decision-making algorithm implementation.
The deployment of Convolutional Neural Networks (CNNs) on resource-constrained edge devices for inference is challenging due to its computation, memory, energy, and bandwidth requirements. To address these issues, FPG...
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ISBN:
(纸本)9781665484855
The deployment of Convolutional Neural Networks (CNNs) on resource-constrained edge devices for inference is challenging due to its computation, memory, energy, and bandwidth requirements. To address these issues, FPGAs are commonly used to implement CNNs because of their high flexibility and low power consumption. This paper proposes a methodology that provides a technique to benchmark CNNs using HDMI input and output in real-time with 720p high definition (HD) resolution. This methodology can be utilized in a classroom set up to teach CNN and computer vision fundamentals. To illustrate the effectiveness of the proposed methodology, several object detection and image classification CNNs were deployed on the Xilinx ZCU104 FPGA board. Video is provided to the FPGA in real-time from an HDMI input source. The output of a given CNN is converted to an HDMI stream and displayed on a separate monitor at 720p HD resolution. The experimental results show that this methodology can perform object detection and image classification on real-time video at speeds of around 10 FPS and 30 FPS, respectively.
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