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A novel autonomous low-cost on-board data handling architecture for a pin-point planetary lander

ACTA ASTRONAUTICA 2011年第7-8期68卷 811-829页

作者： Vladimirova, Tanya Fayyaz, Muhammad Sweeting, Martin N. Vitanov, Valentin I. Univ Surrey Dept Elect Engn Surrey Space Ctr Guildford GU2 7XH Surrey England Univ Durham Sch Engn & Comp Sci Durham DH1 3LE England

There has been increased interest in the exploration of the Moon in recent years. Pinpoint precision landing is highly desirable for future lunar missions. This paper is concerned with the design of the on-board data handling (OBDH) subsystem for the pinpoint lunar lander of the Magnolia-1 project, funded by NASA. Four proposed on-board data handling architectures are outlined and compared in terms of power consumption, performance and reliability. Implementation results are presented, which are obtained from prototyping of the flight computer for the optimal OBDH architecture option on a Xilinx Virtex-5 field programmable gate array. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： On-board data handling Pin-point planetary lander field programmable gate array

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Rapid prototyping of hardware/software codesign for embedded signal processing

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JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 1998年第3期14卷 605-632页

作者： Hwang, YT Wang, YH Hwang, JS Natl Yunlin Univ Sci & Technol Dept Elect Engn Yunlin 640 Taiwan

In this paper, we propose a target board architecture suitable for embedded signal processing applications based on hardware software codesign. The target board, which serves as a system attached to a host PC via a PCI bus interface, contains a TMS320C30 DSP processor and up to four Xilinx XC5204 FPGAs. The software and hardware sections of the codesign can be easily implemented using C and VHDL programming in the C30 processor and FPGAs, respectively. Based on the proposed target board architecture, the interface circuitry and the communication protocols between the hardware (FPGAs) and software (C30) sections are first derived. The interface circuitry is described in VHDL code and will be added to the FPGA design for high level synthesis. Five types of HW/SW communications are supported. A HW/SW codesign flow is also exploited, and a partitioning verification procedure is developed. To illustrate the merits of the proposed system, a HW/SW codesign, implementation example based on the G.728 LD-CELP decoder for speech compression is described.

关键词： hardware/software codesign communication interface embedded system hardware/software partitioning hardware description language target board rapid prototyping field programmable gate array

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An Unbiased MCMC FPGA-Based Accelerator in the Land of Custom Precision Arithmetic

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IEEE TRANSACTIONS ON COMPUTERS 2017年第5期66卷 745-758页

作者： Liu, Shuanglong Mingas, Grigorios Bouganis, Christos-Savvas Imperial Coll Dept Elect & Elect Engn London SW7 2AZ England

Markov Chain Monte Carlo (MCMC) based methods have been the main tool used for Bayesian Inference by practitioners and researchers due to their flexibility and theoretical properties that guarantee unbiased sampling-based estimates. Nevertheless, with the availability of large data sets and the constant need to develop more complex models that better capture the targeted problem, significant computational challenges have been presented. Current approaches, based on multi-core CPUs, GPUs, and FPGAs, aim to accelerate the execution time of the MCMC methods using subsampling techniques or custom precision arithmetic, resulting to biased estimates. In this work, a novel FPGA-based construction is proposed that utilises the custom precision support of FPGA devices in order to accelerate the computations, guaranteeing at the same time asymptotically unbiased estimates. Key to this approach is the extension of the parameter space by an extra parameter that indicates the required precision in the computation of the likelihood of a data point. The work proposes an FPGA architecture for the above algorithm, as well as discuss its tuning for maximising the performance of the system. The performance of the FPGA-mapped sampler is evaluated using two Bayesian logistic regression case studies of varying complexity, which show significant speedups compared to existing FPGA- and CPU-based works that utilise double floating point arithmetic, without any bias on the sampling-based estimates.

关键词： field programmable gate array Markov chain Monte Carlo custom arithmetic precision logistic regression MNIST database

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Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

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MICROPROCESSORS AND MICROSYSTEMS 2007年第1期31卷 1-14页

作者： Galanis, M. D. Milidonis, A. Theodoridis, G. Soudris, D. Goutis, C. E. Univ Patras VLSI Design Lab Elect & Comp Engn Dept Rion Greece Aristotle Univ Thessaloniki Dept Phys Sect Elect GR-54006 Thessaloniki Greece Democritus Univ VLSI Design Ctr Elect & Comp Engn Dept Xanthi Greece

In this paper, we present a software framework that implements a formalized methodology for partitioning Digital Signal Processing applications between reconfigurable hardware blocks of different granularity. A hybrid generic reconfigurable architecture is considered, so that the methodology is applicable to a large variety of hybrid reconfigurable systems. The developed framework is composed of analysis, partitioning, and mapping tools. Although, the framework is parametrical in respect to the mapping procedures for the fine and coarse-grain reconfigurable units, we provide specific mapping algorithms for these types of hardware. In this work, the methodology is validated using five real-world digital signal processing applications;an orthogonal frequency division multiplexing transmitter, a cavity detector, a video compression technique, a JPEG encoder, and a wavelet-based image compressor. The experiments report that an average clock cycles decrease of 60.7%, relative to an all fine-grain mapping solution, is achieved using the developed framework for the considered applications. (c) 2006 Elsevier B.V. All rights reserved.

关键词： hybrid reconfigurable platform partitioning methodology mapping analysis coarse-grain reconfigurable hardware field programmable gate array performance

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FPGA-based methodology for depth-of-field extension in a single image

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DIGITAL SIGNAL PROCESSING 2017年 70卷 14-23页

作者： Lopez-Ramirez, M. Ledesma-Carrillo, L. M. Cabal-Yepez, E. Botella, G. Rodriguez-Donate, C. Ledesma, Sergio Univ Guanajuato Div Ingn Campus Irapuato SalamancaAve Univ SN Guanajuato 38944 Mexico Univ Complutense Madrid Dept Arquitectura Comp & Automat Ave Complutense S-N E-28040 Madrid Spain

Computer vision applications rely upon high resolution images with extended depth of field (DoF). Most approaches contain arrays of lenses and computing intensive algorithms that must be calibrated every time, to reach in-focus images;however, by changing directly the system focal length, resolution and information are lost. Traditional methods consist in taking a great number of images varying the optical system pupil aperture, whereas, the post processing system demands a great amount of computational resources with long processing time and high implementation cost. In this work a novel methodology for DoF extension that applies a complex-amplitude mask during a single image pre-processing taken at full pupil aperture, and a Wiener filter for the image recovery without focalization errors, during post-processing, is introduced. An FPGA-based implementation shows the feasibility of the proposed methodology for real-time DoF extension. Obtained results demonstrate qualitatively and quantitatively the effectiveness of the proposed FPGA-based method, which offers a reconfigurable solution for online DoF extension on a single image, in real time. (C) 2017 Elsevier Inc. All rights reserved.

关键词： Complex-amplitude mask Extended depth of field field programmable gate array High-resolution imaging One single image processing Wiener filter

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Development of a FPGA based fuzzy neural network system for early diagnosis of critical health condition of a patient

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COMPUTERS IN BIOLOGY AND MEDICINE 2010年第2期40卷 190-200页

作者： Chowdhury, Shubhajit Roy Saha, Hiranmay Jadavpur Univ Dept Elect & Telecommun Engn IC Design & Fabricat Ctr Kolkata 700032 W Bengal India

The paper describes the design and training of a fuzzy neural network used for early diagnosis of a patient through an FPGA based implementation of a smart instrument. The system employs a fuzzy interface cascaded with a feed-forward neural network. In order to obtain an optimum decision regarding the future pathophysiological state of a patient, the optimal weights of the synapses between the neurons have been determined by using inverse delayed function model of neurons. The neurons that are considered in the proposed network are devoid of self connections instead of commonly used self connected neurons. The current work also find out the optimal number of neurons in the hidden layer for accurate diagnosis as against the available number of CLB in the FPGA. The system has been trained and tested with renal data of patients taken at 10 days interval of time. Applying the methodology, the chance of attainment of critical renal condition of a patient has been predicted with an accuracy of 95.2%, 30 days ahead of actually attaining the critical condition. The system has also been tested for pathophysiological state prediction of patients at multiple time steps ahead and the prediction at the next instant of time stands out to be the most accurate. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： Medical diagnosis Fuzzy neural network field programmable gate array Critical condition

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Real-time emulation of a three-phase Vienna rectifier with DC voltage control and power factor correction

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ELECTRICAL ENGINEERING 2020年第1期102卷 97-106页

作者： Aiello, G. Cacciato, M. Scarcella, G. Scelba, G. Gennaro, F. Aiello, N. DIEEI Univ Catania Catania Italy STMicroelectronics Syst Res & Applicat Catania Italy

The paper deals with the accomplishment of a FPGA-based dynamic model of a three-phase Vienna rectifier controlled in order to feature unity power factor operations. Such a model has been developed for the Hardware In the Loop (HIL) implementation of a test rig in which the power converter is replaced with an embedded system using a FPGA board. The proposed approach has been fostered mainly to test different converter control algorithms in a fast and safe way. Such solution is based on a software platform environment with a high-level abstraction that ensures a good trade-off between accuracy and hardware resources, also allowing a fast prototyping procedure. The results obtained by the HIL implementation have been compared with those of a fully hardware experimental rig, confirming a very good agreement in terms of accuracy and dynamic behavior.

关键词： PWM rectifiers Grid-connected application field programmable gate array Hardware in the loop Power factor correction Power converters modeling

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Design and FPGA Implementation of a Novel Efficient FRM-Based Channelized Receiver Structure

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IEEE ACCESS 2019年 7卷 114778-114787页

作者： Zhang, Wenxu Yao, Yushuang Zhao, Zhongkai Zhao, Wentong He, Junxi Harbin Engn Univ Coll Informat & Commun Engn Harbin 150001 Peoples R China

The main application of the filter bank in radar signal processing is the wideband digital channelized receiver. In order to save hardware resources of the field programmable gate array (FPGA), the efficient channelized receiver structure using polyphase filter has been designed. However, when the number of channels is greatly increased or the transition bandwidth of the filter bank (FB) becomes very narrow, it still consumes large amounts of hardware resources. Therefore, a novel efficient channelized receiver structure based on frequency response masking (FRM) and modulation filter bank is proposed in this paper. The proposed novel structure has less computational complexity in implementing FB with narrow transition bandwidth (NTB). Compared with other efficient FRM-based structures, the proposed novel structure is more suitable for wideband digital channelization receiver. The proposed novel structure is verified correctly by Matlab simulation. The FPGA implementation of the polyphase channelized receiver structure and the proposed novel efficient FRM-based channelized receiver structure are completed by Xilinx System Generator. The result shows that the proposed novel efficient FRM-based channelized receiver structure can save 48.09% of the DSP48E1 hardware resources compared with the polyphase channelized receiver structure and has low group delay characteristic.

关键词： Frequency response masking narrow transition bandwidth channelized receiver field programmable gate array

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FPGA-based embedded platform for fiber optic gyroscope signal denoising

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2014年第7期42卷 744-757页

作者： Peesapati, Rangababu Sabat, Samrat L. Karthik, K. P. Narasimhappa, M. Giribabu, N. Nayak, J. Univ Hyderabad Sch Phys Hyderabad 500046 Andhra Pradesh India Res Ctr Imarat Hyderabad 500069 Andhra Pradesh India

This paper presents System on Chip (SoC) implementation of a proposed denoising algorithm for fiber optic gyroscope (FOG) signal. The SoC is developed using an Auxillary Processing Unit of the proposed algorithm and implemented in the Xilinx Virtex-5-FXT-1136 field programmable gate array. SoC implementation of this application is first of its kind. The proposed algorithm namely adaptive moving average-based dual-mode Kalman filter (AMADMKF) is a hybrid of adaptive moving average and Kalman filter (KF) technique. The performance of the proposed AMADMKF algorithm is compared with the discrete wavelet transform and KF of different gains. Allan variance analysis, standard deviation and signal to noise ratio (SNR) are used to measure the efficiency of the algorithm. The experimental result shows that AMADMKF algorithm reduces the standard deviation or drift of the signal by an order of 100 and improves the SNR approximately by 80 dB. The Allan variance analysis result shows that this algorithmalso reduces different types of random errors of the signal significantly. The proposed algorithm is found to be the best suited algorithm for denoising the FOG signal in both the static and dynamic environments. Copyright (c) 2013 John Wiley & Sons, Ltd.

关键词： fiber optic gyroscope discrete wavelet transform Kalman filter Allan variance field programmable gate array auxiliary processing unit system on chip

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Design and Analysis of Linear Phase Finite Impulse Response Filter Using Water Strider Optimization Algorithm in FPGA

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2022年第9期41卷 5254-5282页

作者： Karthick, R. Senthilselvi, A. Meenalochini, P. Senthil Pandi, S. Sethu Inst Technol Dept Elect & Commun Engn Pulloor Tamil Nadu India SRM Inst Sci & Technol Dept Comp Sci & Engn Ramapuram campus Chennai Tamil Nadu India Sethu Inst Technol Dept Elect & Elect Engn Pulloor Tamil Nadu India Mohamed Sathak A J Coll Engn Dept Comp Sci & Engn Chennai Tamil Nadu India

In this manuscript, an optimal linear phase finite impulse response (FIR) filter is designed using water strider optimization algorithm and implemented in the field programmable gate array (FPGA). The initiative behind the linear phase FIR filter design is "to estimate the coefficients of optimum filter." Here, the water strider optimization algorithm is proposed to evaluate the optimal filter coefficients (LPFIR-WSOA filter). The proposed LPFIR-WSOA filter attains 32.57, 19.09, 28.07, 27.42, 24.91 and 12.72% lower maximum pass ripple compared with the existing linear phase FIR filter. Finally, the proposed LPFIR-WSOA filter is implemented in FPGA for real-time application with the target families of Virtex 6 and Virtex 7. For target FPGA families Virtex 6, the FPGA-LPFIR-WSOA filter provides 16.7910, 15.074 and 18.065% lower maximum clock frequency (MHz);62.3837, 41.9554 and 56.078% lower delay;and 23.7172, 20.324 and 26.417% lower memory usage compared with the existing LPFIR filters like global best steered quantum-inspired cuckoo search algorithm in FPGA (FPGA-FIR-GQICSA), modified artificial bee colony optimization-based FIR filter design in FPGA (FPGA-FIR-MABCO) and hybrid artificial bee colony algorithm-based FIR filter design in FPGA (FPGA-FIR-HABCA), respectively.

关键词： Linear phase finite impulse response filter Water strider optimization field programmable gate array Filter coefficients Ripples Attenuation

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