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Two-dimensional mechanically resonating fiber optic scanning display system

OPTICAL ENGINEERING 2010年第9期49卷

作者： Wang, Wei-Chih Tsui, Chi-Leung Univ Washington Dept Mech Engn Seattle WA 98195 USA Univ Washington Dept Elect Engn Seattle WA 98195 USA

A microdisplay system based on an optical fiber driven by a 2-D piezoelectric actuator is presented. An optical fiber is extended from the free end of a 2-D piezoelectric actuator (free length 4.3 mm). A field programmable gate array (FPGA) drives the actuator using a triangular waveform to deflect the optical fiber in orthogonal directions. The FPGA also controls a LED light source, and the light is coupled into a chemically tapered single-mode fiber (SMF-28, core diameter 10 mu m). At a preset pairing of near-resonance frequencies (horizontal 22 Hz, vertical 5070 Hz), the deflected optical fiber in combination with controlled light produces an output image with an approximate dimension of 0.1 x 0.1 mm(2), and a potential resolution of 400 lines per scan. This work details the design and fabrication of the microdisplay system. The mechanical and optical design for the microresonating scanner is discussed. In addition, the mechanical and optical performance and the resulting output of the 2-D scanner is presented. (C) 2010 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3487745]

关键词： optical display system optical scanner field programmable gate array

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HopliteRT*: Real-Time NoC for FPGA

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年第11期39卷 3650-3661页

作者： Gonzalez, Yilian Ribot Nelissen, Geoffrey Polytech Inst Porto ISEP CISTER Res Ctr P-4200465 Porto Portugal Eindhoven Univ Technol Dept Math & Comp Sci NL-5612 AZ Eindhoven Netherlands

With the increasing number of computation nodes integrated in multi and many-core platforms, network-on-chips (NoCs) emerged as a new communication medium in systems-on-chips (SoCs). HopliteRT is a new NoC design that was recently proposed to address the needs of real-time systems whilst respecting the constraints of field-programmable gate array (FPGA) platforms. In this article, we: 1) introduce priority-based routing in HopliteRT;2) change the network topology in order to improve the packets' worst-case traversal time (WCTT);3) identify a flaw in the existing timing analysis of HopliteRT;and 4) develop a new timing analysis that is proven correct. We also show by means of experiments that the modifications of HopliteRT proposed in this article allows for at least 2x improvement on the worst and average case traversal time of high priority packets, without impacting the quality of service of low-priority packets. The timing properties of high priority flows are greatly improved for negligible additional hardware costs. The proposed NoC has been implemented in Verilog and synthesized for a Xilinx Virtex-7 FPGA platform.

关键词： field programmable gate array network-onchips real-time embedded systems systems-on-chips timing analysis

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Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2021年第4期29卷 691-701页

作者： Baskaran, Saambhavi Sampson, Jack Penn State Univ Sch Elect Engn & Comp Sci Dept Comp Sci & Engn University Pk PA 16802 USA

The electrostrictive 2-D field-effect transistor (EFET) is a steep-slope device that promises to offer aggressive length and voltage scalability. Two key features of this device are its high-drive strength with high ON-OFF current ratio and the isolated back-gate terminal, which provides us the fourth knob to control the transistor drive strength. The disadvantage of the technology is the increased device capacitance incurred due to the additional piezoelectric layer in the transistor structure. Second, although the back-gate biasing of EFETs provides us the fourth knob of control, statically biasing the back gate increases the static power consumption. Despite the idiosyncrasies of the technology, this work shows the use of EFETs in field-programmable gate arrays (FPGAs) to be advantageous because the added energy cost of device capacitance gets amortized by the improvement in performance and energy efficiency of using high-drive EFET transistors in the FPGA interconnect architecture. We also show that co-optimization of back-bias voltage along with transduction efficiency is essential in the FPGA subcircuit level for achieving an energy-efficient architecture. This work highlights the specific design approach tradeoffs that differ from prior CMOS approaches and provides guidance for the engineering parameters necessary for EFETs to evolve as a competitive technology.

关键词： field programmable gate arrays Capacitance Logic gates Strain Photonic band gap Delays Routing Electrostrictive field-effect technology field programmable gate array integrated circuit technology beyond CMOS two-dimensional materials

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Tunable FPGA Bitstream Obfuscation with Boolean Satisfiability Attack Countermeasure

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2020年第2期25卷 1–22页

作者： Olney, Brooks Karam, Robert 4202 E Fowler Ave ENG 030 Tampa FL 33620 USA

field programmable gate arrays (FPGAs) are seeing a surge in usage in many emerging application domains, where the in-field reconfigurability is an attractive characteristic for diverse applications with dynamic design requirements, such as cloud computing, automotive, IoT, and aerospace. The security of the FPGA configuration file, or bitstream, is critical, especially for devices with long in-field lifetimes, where attackers may attempt to extract valuable Intellectual Property (IP) from within. In this article, we propose a tunable obfuscation approach that protects IP from typical bitstream attacks while enabling designers to trade off security with acceptable overhead. We also consider two potential attacks on this protection mechanism: Boolean SAT Attacks on the obfuscation and removal attacks on the protection circuitry. The obfuscation and SAT countermeasure are integrated in a custom CAD framework within a commercial FPGA toolflow and together provide mathematically strong protection against common bitstream attacks. Further, we quantify the difficulty of a removal attack on the protection circuitry through pattern matching and direct bitstream manipulation. The average area, power, and delay overhead for obfuscation with 95% mismatch probability are 18%, 16%, and 8%, respectively, for small combinational circuits, and 1%, 2%, and 5% for larger arithmetic modules.

关键词： field programmable gate array obfuscation SAT attack removal attack overheads

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CORDIC-based window implementation to minimise area and pipeline depth

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IET SIGNAL PROCESSING 2013年第5期7卷 427-435页

作者： Aggarwal, Supriya Khare, Kavita MANIT Dept Elect & Commun Engn Bhopal India

Filtering is one of the most important modules in signal processing paradigm. This study presents a field-programmable gate array implementation of various window functions using coordinate rotation digital computer (CORDIC) algorithm to minimise area-delay product. First, the authors modify the Taylor series approximation order used in the scaling-free CORDIC, to completely eliminate the scale-factor and, yet, preserve the range of convergence spanning across the entire coordinate space. Secondly, the authors propose a new generalised technique for micro-rotation sequence identification to reduce the number of iterations required by the pipelined CORDIC processor. Then, this circular CORDIC processor is used to realise window functions. The existing window architecture uses a linear CORDIC processor in series with circular CORDIC processor, resulting in long pipeline. The authors replace the linear CORDIC with multiple optimised shift-add networks to reduce area and pipeline depth. As a result, the proposed window architecture, on an average requires approximately 64.34% less pipeline stages and saves up to 48% area. The authors have designed the processor to implement Hanning, Hamming and Blackman window families. The implementation of the proposed architecture is detailed in this study.

关键词： field programmable gate array Logic and switching circuits linear CORDIC processor CORDIC based window implementation Logic circuits coordinate rotation digital computer window functions window filtering pipelined CORDIC processor shift-add networks field programmable gate arrays Filtering methods in signal processing Hamming window area delay product Hanning window Signal processing theory Taylor series approximation filtering microrotation sequence identification Blackman window signal processing circular CORDIC processor pipeline processing filtering theory scale factor

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Systemic approach explored in the context of passive target tracking

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IET SIGNAL PROCESSING 2010年第3期4卷 314-323页

作者： Totir, F. Ioana, C. Serbanescu, A. Stopin, J. Anton, L. Stankovic, S. Mil Tech Acad Bucharest 050141 Romania INPG GIPSA Lab F-38402 St Martin Dheres France Univ Montenegro Podgorica 81000 Montenegro

For obvious reasons of cost, discretion and reliability costs, locating and tracking aerial targets under an electromagnetically completely passive paradigm, relying exclusively on illuminators of opportunity, is very appealing not only for military but also for civilian tasks. Such a passive radar system could exploit signals emitted by existing commercial television or radio stations or even satellite signals, such as the ones belonging to the global positioning system. This study considers target locating and tracking using a network of passive receivers and/or non-cooperative illuminators (a multi-static radar configuration) by making use of the Doppler shift only. A concept, the systemic approach, is used to combine and interpret information available from different sensors. Both the formalisation of the problem and the hardware and software implementation are presented. Implementation makes use of multi-component polynomial-phase signal models and genetic algorithms. For increased performance, implementation on field programmable gate array is envisaged.

关键词： passive radar system radar signal processing satellite signals global positioning system reliability costs field programmable gate array target locating discretion costs multicomponent polynomial-phase signal models target tracking Optimisation techniques Radar equipment, systems and applications Signal processing and detection genetic algorithms passive target tracking

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GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs

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IEEE TRANSACTIONS ON COMPUTERS 2018年第3期67卷 375-387页

作者： Wild, Alexander Moradi, Amir Gueneysu, Tim Ruhr Univ Bochum Horst Gortz Inst IT Secur D-44801 Bochum Germany Univ Bremen German Res Ctr Artificial Intelligence D-28359 Bremen Germany

Designers of secure hardware are required to harden their implementations against physical threats, such as power analysis attacks. In particular, cryptographic hardware circuits need to decorrelate their current consumption from the information inferred by processing (secret) data. A common technique to achieve this goal is the use of special logic styles that aim at equalizing the current consumption at each single processing step. However, since all hiding techniques like Dual-Rail Precharge (DRP) were originally developed for ASICs, the deployment of such countermeasures on FPGA devices with fixed and predefined logic structure poses a particular challenge. In this work, we propose and practically evaluate a new DRP scheme (GliFreD) that has been exclusively designed for FPGA platforms. GliFreD overcomes the well-known early propagation issue, prevents glitches, uses an isolated dual-rail concept, and mitigates imbalanced routings. With all these features, GliFreD significantly exceeds the level of physical security achieved by any previously reported, related countermeasures for FPGAs.

关键词： Dual-rail precharge logic field programmable gate array side-channel attack power analysis power-equalization hiding

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Practical VHDL optimization for timing critical FPGA applications

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MICROPROCESSORS AND MICROSYSTEMS 1999年第8-9期23卷 459-469页

作者： Kuusilinna, K Hämäläinen, T Saarinen, J Tampere Univ Technol Signal Proc Lab FIN-33720 Tampere Finland

This paper gives a hands-on example of how low-level optimization of the VHSIC Hardware Description Language (VHDL) code is extremely difficult within a contemporary field programmable gate array (FPGA) design how. However, low-level optimization can be accomplished, and by changing the VHDL coding style synthesis results can be improved. The design flow is considered from high-level descriptions (bubble diagrams), through logic synthesis to the point where hand optimization is required. For performance benchmarking a state machine from a contemporary computer bus, PCI, implemented in a Xilinx FPGA, is used. Practical design issues applied to time-critical implementations using FPGAs, especially the trade-offs of high-level versus low-level synthesis, are analyzed. Performance evaluation results of several PCI target state machines, coded using different styles and design methods are given in terms of time and area efficiency. Based on these findings improvements to the FPGA design methodology are proposed. (C) 1999 Elsevier Science B.V. All rights reserved.

关键词： VHDL field programmable gate array synthesis PCI electronic design automation

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Fast OMP algorithm and its FPGA implementation for compressed sensing-based sparse signal acquisition systems

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IET CIRCUITS DEVICES & SYSTEMS 2021年第6期15卷 511-521页

作者： Roy, Shirshendu Acharya, Debiprasad P. Sahoo, Ajit K. Natl Inst Technol Elect & Commun Rourkela Odisha India

Compressed sensing-based radio frequency signal acquisition systems call for higher reconstruction speed and low dynamic power. In this study, a novel low power fast orthogonal matching pursuit (LPF-OMP) algorithm is proposed for faster reconstruction of sparse signals from their compressively sensed samples and the reconstruction circuit consumes very low dynamic power. The searching time to find the best column is reduced by reducing the number of columns to be searched in successive iterations. A novel architecture of the proposed LPF-OMP algorithm is also presented here. The proposed architecture is implemented on field programmable gate array for demonstrating the performance enhancement. Computation of pseudoinverse in OMP is avoided to save time and storage requirement to store the pseudoinverse matrix. The proposed design incorporates a novel strategy to stop the algorithm without consuming any extra circuitry. A case study is carried out to reconstruct the RADAR test pulses. The design is implemented for K = 256, N = 1024 using XILINX Virtex6 device and supports maximum of K/4 iterations. The proposed design is faster, hardware efficient and consumes very less dynamic power than the previous implementations of OMP. In addition, the proposed implementation proves to be efficient in reconstructing low sparse signals.

关键词： LPF-OMP algorithm searching time compressed sensing compressed sensing-based radio frequency signal acquisition systems field programmable gate array signal detection low sparse signals compressively sensed samples logic design reconstruction circuit faster reconstruction compressed sensing-based sparse signal acquisition systems storage requirement low dynamic power higher reconstruction speed field programmable gate arrays low-pass filters image reconstruction FPGA implementation low power fast orthogonal matching pursuit fast OMP algorithm

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A FPGA CORE GENERATOR FOR EMBEDDED CLASSIFICATION SYSTEMS

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2011年第2期20卷 263-282页

作者： Anguita, Davide Carlino, Luca Ghio, Alessandro Ridella, Sandro Univ Genoa Dept Biophys & Elect Engn I-16145 Genoa Italy

We describe in this work a Core Generator for Pattern Recognition tasks. This tool is able to generate, according to user requirements, the hardware description of a digital architecture, which implements a Support Vector Machine, one of the current state-of-the-art algorithms for Pattern Recognition. The output of the Core Generator consists of a high-level language hardware core description, suitable to be mapped on a reconfigurable device, like a field programmable gate array (FPGA). As an example of the use of our tool, we compare different solutions, by targeting several reconfigurable devices, and implement the recognition part of a machine vision system for automotive applications.

关键词： Core generator pattern recognition machine learning Support Vector Machine field programmable gate array

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