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Real-time emulation of a three-phase Vienna rectifier with DC voltage control and power factor correction

ELECTRICAL ENGINEERING 2020年第1期102卷 97-106页

作者： Aiello, G. Cacciato, M. Scarcella, G. Scelba, G. Gennaro, F. Aiello, N. DIEEI Univ Catania Catania Italy STMicroelectronics Syst Res & Applicat Catania Italy

The paper deals with the accomplishment of a FPGA-based dynamic model of a three-phase Vienna rectifier controlled in order to feature unity power factor operations. Such a model has been developed for the Hardware In the Loop (HIL) implementation of a test rig in which the power converter is replaced with an embedded system using a FPGA board. The proposed approach has been fostered mainly to test different converter control algorithms in a fast and safe way. Such solution is based on a software platform environment with a high-level abstraction that ensures a good trade-off between accuracy and hardware resources, also allowing a fast prototyping procedure. The results obtained by the HIL implementation have been compared with those of a fully hardware experimental rig, confirming a very good agreement in terms of accuracy and dynamic behavior.

关键词： PWM rectifiers Grid-connected application field programmable gate array Hardware in the loop Power factor correction Power converters modeling

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FPGA-based embedded platform for fiber optic gyroscope signal denoising

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2014年第7期42卷 744-757页

作者： Peesapati, Rangababu Sabat, Samrat L. Karthik, K. P. Narasimhappa, M. Giribabu, N. Nayak, J. Univ Hyderabad Sch Phys Hyderabad 500046 Andhra Pradesh India Res Ctr Imarat Hyderabad 500069 Andhra Pradesh India

This paper presents System on Chip (SoC) implementation of a proposed denoising algorithm for fiber optic gyroscope (FOG) signal. The SoC is developed using an Auxillary Processing Unit of the proposed algorithm and implemented in the Xilinx Virtex-5-FXT-1136 field programmable gate array. SoC implementation of this application is first of its kind. The proposed algorithm namely adaptive moving average-based dual-mode Kalman filter (AMADMKF) is a hybrid of adaptive moving average and Kalman filter (KF) technique. The performance of the proposed AMADMKF algorithm is compared with the discrete wavelet transform and KF of different gains. Allan variance analysis, standard deviation and signal to noise ratio (SNR) are used to measure the efficiency of the algorithm. The experimental result shows that AMADMKF algorithm reduces the standard deviation or drift of the signal by an order of 100 and improves the SNR approximately by 80 dB. The Allan variance analysis result shows that this algorithmalso reduces different types of random errors of the signal significantly. The proposed algorithm is found to be the best suited algorithm for denoising the FOG signal in both the static and dynamic environments. Copyright (c) 2013 John Wiley & Sons, Ltd.

关键词： fiber optic gyroscope discrete wavelet transform Kalman filter Allan variance field programmable gate array auxiliary processing unit system on chip

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Design and Analysis of Linear Phase Finite Impulse Response Filter Using Water Strider Optimization Algorithm in FPGA

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2022年第9期41卷 5254-5282页

作者： Karthick, R. Senthilselvi, A. Meenalochini, P. Senthil Pandi, S. Sethu Inst Technol Dept Elect & Commun Engn Pulloor Tamil Nadu India SRM Inst Sci & Technol Dept Comp Sci & Engn Ramapuram campus Chennai Tamil Nadu India Sethu Inst Technol Dept Elect & Elect Engn Pulloor Tamil Nadu India Mohamed Sathak A J Coll Engn Dept Comp Sci & Engn Chennai Tamil Nadu India

In this manuscript, an optimal linear phase finite impulse response (FIR) filter is designed using water strider optimization algorithm and implemented in the field programmable gate array (FPGA). The initiative behind the linear phase FIR filter design is "to estimate the coefficients of optimum filter." Here, the water strider optimization algorithm is proposed to evaluate the optimal filter coefficients (LPFIR-WSOA filter). The proposed LPFIR-WSOA filter attains 32.57, 19.09, 28.07, 27.42, 24.91 and 12.72% lower maximum pass ripple compared with the existing linear phase FIR filter. Finally, the proposed LPFIR-WSOA filter is implemented in FPGA for real-time application with the target families of Virtex 6 and Virtex 7. For target FPGA families Virtex 6, the FPGA-LPFIR-WSOA filter provides 16.7910, 15.074 and 18.065% lower maximum clock frequency (MHz);62.3837, 41.9554 and 56.078% lower delay;and 23.7172, 20.324 and 26.417% lower memory usage compared with the existing LPFIR filters like global best steered quantum-inspired cuckoo search algorithm in FPGA (FPGA-FIR-GQICSA), modified artificial bee colony optimization-based FIR filter design in FPGA (FPGA-FIR-MABCO) and hybrid artificial bee colony algorithm-based FIR filter design in FPGA (FPGA-FIR-HABCA), respectively.

关键词： Linear phase finite impulse response filter Water strider optimization field programmable gate array Filter coefficients Ripples Attenuation

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Efficient implementation of iterative multi-input-multi-output orthogonal frequency-division multiplexing receiver using minimum-mean-square error interference cancellation

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IET COMMUNICATIONS 2014年第7期8卷 990-999页

作者： Han, Bing Yang, Zengli Zheng, Yahong Rosa Missouri Univ Sci & Technol Dept Elect & Comp Engn Rolla MO 65409 USA

An efficient hardware implementation scheme is proposed for iterative multi-input-multi-output orthogonal frequency-division multiplexing receiver which includes an MMSE-IC (minimum-mean-square error interference cancellation) detector, a channel estimator, a low-density parity-check (LDPC) decoder and other supporting modules. The proposed implementation uses the QR decomposition (QRD) of the complex-valued matrices with four coordinate rotation digital computer (CORDIC) cores and a back substitution to solve the MMSE-IC equations while the existing systolic array architectures require 15-38 CORDIC cores to achieve a similar throughput. The proposed 4-CORDIC QRD architecture can be configured as a 16-matrix or a 64-matrix pipelining by using a different number of multipliers combined with one-dimensional (1D) or 2D arrays of the back substitution, respectively. The channel estimator implements a commonly-used frequency domain least squares channel estimation with the canonic-signed-digits method, thanks to the character of the Zadroff-Chu sequence used as the pilot. In the LDPC decoder, the min-sum algorithm is implemented for the quasicyclic LDPC decoding. The two schemes for the MMSE-IC detector with different throughput and resource usages have been implemented in a field programmable gate array for a complete baseband turbo receiver. Their resource usages, throughputs and latencies are compared with the classic systolic array architectures, which demonstrate that the proposed receiver architecture achieves the best tradeoff between the throughput and the resource usage.

关键词： iterative methods MIMO communication OFDM modulation least mean squares methods interference suppression channel estimation parity check codes digital arithmetic systolic arrays frequency-domain analysis field programmable gate arrays cyclic codes decoding radiofrequency interference iterative multiple-input multiple-output orthogonal frequency-division multiplexing receiver minimum mean square error interference cancellation hardware implementation scheme MMSE-IC detector low-density parity-check decoder LDPC decoder QR decomposition complex-valued matrices coordinate rotation digital computer cores CORDIC cores MMSE-IC equations 4-CORDIC QRD architecture one-dimensional arrays 2D arrays 1D arrays frequency domain least square channel estimation canonic-signed-digit method Zadroff-Chu sequence character min-sum algorithm quasicyclic LDPC decoding resource usages field programmable gate array baseband turbo receiver classic systolic array architectures receiver architecture

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Bio-inspired optic flow sensors based on FPGA:: Application to Micro-Air-Vehicles

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MICROPROCESSORS AND MICROSYSTEMS 2007年第6期31卷 408-419页

作者： Aubepart, F. Franceschini, N. CNRS Movement & Percept Inst Biorobot Lab F-13288 Marseille France Univ Mediterranean F-13288 Marseille France

Tomorrow's Micro-Air-Vehicles (MAVs) could be used as scouts in many civil and military missions without any risk to human life. MAVs have to be equipped with sensors of several kinds for stabilization and guidance purposes. Many recent findings have shown, for example, that complex tasks such as 3-D navigation can be performed by insects using optic flow (OF) sensors although insects' eyes have a rather poor spatial resolution. At our Laboratory, we have been performing electrophysiological, micro-optical, neuroanatomical and behavioral studies for several decades on the housefly's visual system, with a view to understanding the neural principles underlying OF detection and establishing how OF sensors might contribute to performing basic navigational tasks. Based on these studies, we developed a functional model for an Elementary Motion Detector (EMD), which we first transcribed into electronic terms in 1986 and subsequently used onboard several terrestrial and aerial robots. Here we present a field programmable gate array (FPGA) implementation of an EMD array, which was designed for estimating the OF in various parts of the visual field of a MAV. FPGA technology is particularly suitable for applications of this kind, where a single Integrated Circuit (IC) can receive inputs from several photoreceptors of similar (or different) shapes and sizes located in various parts of the visual field. In addition, the remarkable characteristics of present-day FPGA applications (their high clock frequency, large number of system gates, embedded RAM blocks and Intellectual Property (IP) functions, small size, light weight, low cost, etc.) make for the flexible design of a multi-EMD visual system and its installation onboard MAVs with extremely low permissible avionic payloads. (c) 2007 Elsevier B.V. All rights reserved.

关键词： optic flow sensor elementary motion detector field programmable gate array Micro-Air-Vehicle biorobotics

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Parallel design of SFO optimization algorithm based on FPGA

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JOURNAL OF SUPERCOMPUTING 2024年第8期80卷 10796-10817页

作者： Naji, Hamid Reza Shadravan, Soodeh Jafarabadi, Hossien Mousa Momeni, Hossien Grad Univ Adv Technol Dept Comp & Informat Technol Kerman Iran Islamic Azad Univ Dept Comp Engn Bardsir Branch Bardsir Iran Islamic Azad Univ Dept Math Bardsir Branch Bardsir Iran

Taking a lot of time to solve optimization problems has become a challenge for metaheuristic algorithms. Due to independence of the metaheuristics components, parallel processing is a good option to reduce the computational time and to find high quality solutions that are close to the optimum with an acceptable cost. One of these metaheuristic algorithms is the Sailfish Optimizer (SFO) which is inspired by a group of hunting sailfish. The SFO algorithm uses a simple method to provide a dynamic balance between exploration and exploitation phases, creates a swarm diversity, avoids local optima, and guarantees high convergence speed. It has been shown that the SFO algorithm outperforms various state-of-art metaheuristic algorithms for multimodal and high dimensional benchmark functions and complicated real-world optimization problems in terms of accuracy and speed by CPU and GPU implementation. In this paper, to speedup this algorithm and increase its performance we propose a reconfigurable hardware version of SFO implemented on field programmable gate array (FPGA). The FPGA-based SFO can be a very good option in many applications with massive calculations. Due to the inherent parallelism and high computing capabilities of FPGA, the SFO algorithm gains optimum computational time despite the complexity of optimization problems. We have compared the performance of the proposed FPGA-based SFO with its CPU and GPU implementation and some other metaheuristic algorithms. The results show the FPGA implementation is considerably faster than the CPU and GPU implementation. Also, it outperforms other compared FPGA-based metaheuristic algorithms in terms of execution time and convergence speed.

关键词： SFO algorithm Metaheuristic algorithm field programmable gate array Finite state machine Parallel programming

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TRNG-PUF Integration Utilizing programmable Delay Logics on FPGAs

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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2024年第3期24卷 240-248页

作者： Yang, Heehun Park, Jiho Lee, Jooseung Oh, Hui-Myoung Lee, Soonwoo Yoo, Hoyoung Chungnam Natl Univ Elect Engn Daejeon 305764 South Korea

paper introduces a novel TRNG-PUF structure using programmable Delay Logic (PDL)performance for both True Random Number Generators (TRNGs) and Physical Unclonable Functions (PUFs). Unlike previous approaches utilizing standard ROs, our design employs PDL to fine-tune the ROs, enabling effective harnessing of entropy for TRNGs and providing unique identification for PUFs. The proposed TRNG-PUF structure is implemented and tested on a Xilinx Artix-7 100T FPGA, demonstrating superior area efficiency and performance. In terms of hardware complexity, it showed the highest hardware efficiency among various designs. Particularly, compared to the conventional structure without shared sources, the proposed TRNGPUF structure reduces the area of LUT and flip-flops by 41% and 24%, respectively. Moreover, the TRNG component of the structure is evaluated using the NIST SP 800-22 test, and it successfully passed all 15 tests. In contrast, previous TRNG-PUF designs only achieved assessed through Hamming distance measurements, designs.

关键词： field programmable gate array ring oscillator true random number generator physically unclonable function

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Efficient FPGA implementation of sharp FIR filters using the FRM technique

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IEICE ELECTRONICS EXPRESS 2009年第23期6卷 1656-1662页

作者： Li, Shuguo Zhang, Jian Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China

A high-performance field programmable gate array (FPGA) implementation of full pipelined computation structure is proposed for sharp finite-impulse -response (FIR) filters using the frequency response masking (FRM) technique. The FRM-based FIR (FFIR) filter consists of a novel symmetrical systolic array of a interpolated FIR (IFIR) filter in cascade to a pair of nonsymmetrical systolic arrays of masking FIR filters mainly. These filters are designed based on inner-product computation involving MAC operation which can be realized by the DSP block in the latest FPGA device efficiently. The realization results on a Xilinx Virtex-5 chip show that the proposed FPGA implementation can obtain higher throughput but consumes less resource compared to the equivalent conventional sharp FIR (CSFIR) filter that developed by the Core Generator software tool.

关键词： frequency response masking technique FIR filter field programmable gate array systolic array

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Parallel-Pipelined-Memory-Based Blowfish Design with Reduced FPGA Utilization for Secure ZigBee Real-Time Transmission

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WIRELESS PERSONAL COMMUNICATIONS 2019年第1期104卷 471-489页

作者： Ahmad, Rafidah Kho, Daniel Abd Manaf, Asrulnizam Ismail, Widad Univ Sains Malaysia Collaborat Microelect Design Excellence Ctr CEDEC Engn Campus Nibong Tebal 14300 Penang Malaysia Multimedia Univ Persiaran Multimedia Fac Engn Cyberjaya 63100 Selangor Malaysia Univ Sains Malaysia Sch Elect & Elect Engn AutoID Lab Engn Campus Nibong Tebal 14300 Penang Malaysia

Data security is currently become a serious concern in wireless communication system for both the users and providers. Without a secure medium, the data transmission is exposed to various types of wireless attacks. Therefore, this paper focuses on the development of a high performance parallel-pipelined-memory-based ((PM)-M-2) Blowfish as a security design with reduced field programmable gate array (FPGA) utilization, which is the best security design to be embedded in the mobile devices. Through FPGA platform, the performance of the proposed Blowfish shows that a throughput increases by 10.5%, with the hardware utilization and power consumption decrease by 3.5% and 21%, respectively. The (PM)-M-2 Blowfish was validated in two-way communication channel by using FPGA-based radio platform together with ZigBee technology and the real-time transmission was measured in terms of bit-error-rate, received power and communication range. These characteristics have proven that the proposed (PM)-M-2 Blowfish possesses the ability to replace the advanced encryption standard which is known as a complex algorithm employed by most of the wireless communication standards.

关键词： Power-throughput Blowfish field programmable gate array ZigBee Bit-error-rate

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High-performance position detection and velocity adaptive measurement for closed-loop position control

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 1998年第4期47卷 978-985页

作者： Lygouras, JN Lalakos, KA Tsalides, PG Democritus Univ Thrace Dept Elect Engn Div Elect & Informat Syst Technol GR-67100 Xanthi Greece

This paper presents a new solution for processing the pulses from an optical encoder attached to a motor shaft, and deriving the rotational speed information. An adaptive method allows the evaluation of the motor rotational speed with very good accuracy even at very low speeds, The adaptation also of the sampling period, according to the instant rotational speed, results in better response times at medium or high rotational speeds. The measurement accuracy at low speeds using the proposed method is improved, compared to currently known methods. Another significant advantage of using the proposed circuit is that it can be implemented in specific hardware, thus, reserving the full computational power of the controlling digital signal processor (DSP) for high-level control tasks and for future software expansions.

关键词： adaptive signal processing closed-loop systems digital signal processor field programmable gate array position control velocity measurement

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