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Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第1期69卷 75-85页

作者： He, Ke Crockett, Louise Stewart, Robert Univ Strathclyde EEE Dept Glasgow G1 1XW Lanark Scotland

Partial Reconfiguration (PR) is a method for field programmable gate array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design.

关键词： field programmable gate array Software defined radio Partial reconfiguration Dynamic reconfigurable port 3GPP LTE IEEE 802.16 IEEE 802.11 3GPP WCDMA

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HLS-Based Large Scale Self-Organizing Feature Maps

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IEEE ACCESS 2024年 12卷 142459-142474页

作者： Porrmann, Florian Hagemeyer, Jens Porrmann, Mario Bielefeld Univ Cognitron & Sensor Syst Grp CITEC D-33615 Bielefeld Germany Osnabruck Univ Inst Comp Sci Comp Engn Grp D-49090 Osnabruck Germany

The Self-Organizing Map (SOM) algorithm is a clustering algorithm used in a wide variety of application domains. Over the last few decades, it has been accelerated using various hardware architectures, including FPGAs, CPUs, and GPUs. This publication presents an High-Level Synthesis-based implementation that utilizes multiple processing elements to realize a high-performance system architecture. An extensive design space exploration was conducted to evaluate the performance range of the architecture. For this, vector dimensions ranging from 8 up to 512 and map sizes from 16x 16 to 512x512 were used. The evaluation was performed using two different AMD/Xilinx UltraScale+ FPGA systems, the VCU128 PCIe-based accelerator card and the ZCU106 stand-alone evaluation kit. From the achieved results, it can be seen that the performance scales nearly linearly for a given vector dimension when the map size is increased. In addition, the energy efficiency for both FPGAs was analyzed, revealing that while the ZCU106 is less powerful in terms of raw compute power, it requires up to 4x less power and, depending on the configuration, can be 2x more energy efficient compared to the VCU128. One of the main reasons for this is that it does not require a dedicated host system but utilizes its internal ARM cores. Finally, a comparison against state-of-the-art SOM implementations was conducted. The proposed design achieves a speed-up of up to 458.7, 1,630.4 , and 4.9 compared to other CPU, GPU, and FPGA realizations, respectively.

关键词： Neurons Computer architecture Clustering algorithms Training Graphics processing units Statistical analysis Space exploration Heterogeneous networks field programmable gate array hardware acceleration machine learning reconfigurable architectures reconfigurable computing heterogeneous computing heterogeneous architectures self-organizing feature maps optimization design space exploration heterogeneous architectures self-organizing feature maps optimization design space exploration

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Modified impedance source inverter for power conditioning system

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SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES 2017年第3期42卷 353-364页

作者： Suganthi, J. Rajaram, M. Govt Coll Engn Dept Elect & Elect Engn Tirunelveli 627007 India Anna Univ Madras 600025 Tamil Nadu India

Based on classical impedance source inverter concept, this paper presents a modified impedance source inverter controlled by different pulse width modulation control strategies for solar PV/battery-powered applications. A brief topology analysis, generalized discussion and design of impedance network elements are presented. Comparison with the classical impedance source inverter is presented. Using simulation, analytical results are presented that ensure stability. The proposed voltage type inverter has reduced inrush current at startup, less capacitor voltage stress and minimum inductor current ripples. DC link voltage boost, reduced total harmonic distortion of output current and voltage, better voltage gain and wide range of output voltage control can be achieved easily with improved power quality. Experimental set-up of the modified impedance source inverter with field programmable gate array (FPGA) controller has been constructed to ascertain the results.

关键词： Modified impedance source inverter power conditioning system cross conduction period modified space vector pulse width modulation field programmable gate array

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Hardware-software co-design architecture for Joint Photo Expert Graphic XR encoder

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IET IMAGE PROCESSING 2012年第9期6卷 1284-1292页

作者： Tseng, C. -F. Lai, Y. -T. Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

In recent years, because of to the fast growing of internet and digital multi-media, new image compression algorithms are needed to reduce the transferring bandwidth and the decay of image quality. Joint Photo Expert Graphic (JPEG) extended range (XR) is a new standard for still image compression. Compared to previous standards, it provides better image quality and plentiful pixel format. However, the better image quality often comes with the higher computation complexity. In this study, the authors propose a hardware-software co-design architecture for JPEG XR encoder. For photo overlap transform (POT), and photo core transform (PCT), the complicated parts of JPEG XR, the authors propose new algorithms which eliminate data dependency in the basic filters of POT and PCT so that operations can be executed in parallel. The processing rate of the new algorithms is much faster. The authors also demonstrate a basic filter with multiple functions, which can be time-shared by POT and PCT;the hardware cost can be therefore reduced. Moreover, a memory saving scheme is proposed. Therefore the proposed architecture is suitable for stand-alone application-specific integrated circuit (ASIC). In our co-design, POT and PCT are implemented in hardware and then mapped to field programmable gate array (FPGA), whereas the other procedures of JPEG XR such as quantisation are executed by ARM926-EJ processor. The overall performance of our hardware architecture is 50 fps for 4:4:4 HDTV format at 166 MHz.

关键词： frequency 166 MHz image quality ASIC Filtering methods in signal processing photo core transform ARM926-EJ processor data compression hardware-software codesign digital multimedia image compression algorithm JPEG XR encoder field programmable gate arrays Hardware-software codesign Internet Electronic engineering computing FPGA joint photo expert graphic XR encoder Computer vision and image processing techniques computer architecture Image and video coding still image compression application specific integrated circuits image coding hardware architecture photo overlap transform data dependency Integral transforms POT quantisation (signal) Logic circuits Computer architecture computation complexity quantisation JPEG extended range stand-alone application-specific integrated circuit PCT Logic and switching circuits memory saving scheme HDTV format filtering theory filter bandwidth transfer hardware-software co-design architecture field programmable gate array Digital circuit design, modelling and testing transforms

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Design of a Real Time FPGA-Based Three Dimensional Positioning Algorithm

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2011年第1期58卷 26-33页

作者： Johnson-Williams, Nathan G. Miyaoka, Robert S. Li, Xiaoli Lewellen, Tom K. Hauck, Scott Univ Washington Dept Elect Engn Seattle WA 98195 USA Univ Washington Dept Radiol Seattle WA 98195 USA Univ Washington Dept Phys Seattle WA 98195 USA

We report on the implementation and hardware platform of a real time Statistics-Based Positioning (SBP) method with depth of interaction processing for a positron emission tomography detector. The processing method works in conjunction with continuous miniature crystal element (cMiCE) detectors using a sensor on the entrance surface design. Our group previously reported on a field programmable gate array (FPGA) SBP implementation that provided a two dimensional (2D) detector positioning solution [1]. This new implementation extends that work to take advantage of three dimensional (3D) look up tables to provide a 3D positioning solution that improves intrinsic spatial resolution. Resolution is most improved along the edges of the crystal, an area where the 2D algorithm's performance suffers. The algorithm allows an intrinsic spatial resolution of similar to 0.90 mm FWHM in X and Y and a resolution of similar to 1.90 mm FWHM in Z (i.e., the depth of the crystal) based upon DETECT2000 simulation results that include the effects of Compton scatter in the crystal. A pipelined FPGA implementation is able to process events in excess of 220 K events per second, which is greater than the maximum expected coincidence rate for an individual detector. In contrast to all detectors being processed at a centralized host (as in the current system) a separate FPGA is available at each detector, thus dividing the computational load. A prototype design has been implemented and tested on an Altera Stratix II FPGA using a reduced word size due to memory limitations of our commercial prototyping board.

关键词： Data acquisition field programmable gate array maximum likelihood estimation

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FPGA-based SOC for hardware implementation of a local histogram-based video shot detector

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2017年第4期25卷 3300-3318页

作者： Ben Abdelali, Abdessalem Krifa, Mohamed Nidhal Mtibaa, Abdellatif Univ Monastir Lab Elect & Microelect Monastir Tunisia

In this paper, we present a video application example and its implementation in a reconfigurable system-on chip (SOC) platform. The proposed platform employs the benefits of field programmable gate array (FPGA) technology. A prototype based on a Xilinx Virtex-5 FPGA is developed. The application includes a video shot boundary detection module based on the local histogram (LH) technique. Diverse hardware module versions corresponding to different quantization levels and architectural solutions for an LH-based shot detection system are presented. The developed modules have different hardware resource occupations and can be used in a dynamic way to allow flexible management of the target hardware system. They also show high execution time efficiency and can reach an important bandwidth that can support the most recent high-resolution video formats with a high rate of frames per second. A complete SOC-based demonstration for video summarization based on the LH is also developed. It includes the LH extraction, shot boundary detection, and key frame visualization.

关键词： Hardware implementation field programmable gate array system on chip partial dynamic reconfiguration real time local histogram shot boundary detection video summarization

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Hardware co simulation of LTE physical layer for mobile network applications

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2019年 99卷 124-133页

作者： Venkataramanan, V. Lakshmi, S. Sathyabama Inst Sci & Technol Sch Elect & Elect Engn Dept Elect & Commun Chennai 119 Tamil Nadu India

Due to the rapid growth of wireless technology, it has become possible to provide solutions for fading, interference, and multipath. Long term evolution and Long term evolution Advanced systems describe the standards based on 3rd Generation partnership project to overcome issues related to wireless technology. These techniques mitigate the latency and improves the system capacity. The Long term evolution physical layer uses orthogonal frequency division multiple access for downlink, and Single carrier-frequency division multiple access for uplink. Therefore this study provides a comprehensive investigation of orthogonal frequency division multiple access and Single carrier-frequency division multiple access transmission model and investigate physical layer performance of Long term evolution system using MATLAB - Simulink - Xilinx system generator platform based on releases, simulation implementation;results may be discussed in terms of Register transfer level design, power estimation, and resource estimation. For synthesis and implementation of the above architecture Plan ahead tool on Virtex, device board is used. (C) 2018 Published by Elsevier B.V.

关键词： field programmable gate array Hardware co-simulation Long term evolution Multiple input multiple output Orthogonal frequency division multiplexing The 3rd generation partnership project

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Distortion correction for a wide-angle on real-time lens based digital image processing

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OPTICAL ENGINEERING 2003年第7期42卷 2029-2039页

作者： Jiang, J Zhang, GJ Zhou, FQ Yu, DY Xie, HB Liu, H Beijing Univ Aeronaut & Astronaut Beijing Sch Automat Sci & Elect Engn Beijing 100083 Peoples R China Tianjin Univ Sch Precis Instrument & Optoelect Engn Tianjin 300072 Peoples R China

Images captured with wide-angle lenses suffer from spatial distortion, which prevents accurate measure and feature extraction. In this work, a mathematical model based on polynomial mapping is used to map the images from distorted image space onto the corrected image space. The model parameters include the polynomial coefficients, distortion center, and dot center. A new technique to estimate the distortion center based on the evaluation function is presented. In dot center estimation, a seed fill algorithm is used to traverse all pixels. The expansion polynomial was obtained by using cubic spline interpolation. With a field programmable gate array (FPGA), the real-time distortion correction is implemented, which is independent of a computer. The major benefit using FPGA is that the same circuit can be used for other circularly symmetric wide-angle lenses without being modified. (C) 2003 Society of Photo-Optical Instrumentation Engineers.

关键词： distortion correction real-time digital image processing wide-angle lens field programmable gate array

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Development of an FPGA-based system for real-time simulation of photovoltaic modules

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MICROELECTRONICS JOURNAL 2009年第7期40卷 1094-1102页

作者： Koutroulis, Eftichios Kalaitzakis, Kostas Tzitzilonis, Vasileios Tech Univ Crete Dept Elect & Comp Engn GR-73100 Khania Crete Greece

Photovoltaic (PV) simulators are indispensable for the operational evaluation of PV energy production system components (e.g. battery chargers, DC/AC inverters, etc.), in order to avoid the time-consuming and expensive field-testing process. In this paper, the development of a novel real-time PV simulator based on field programmable gate arrays (FPGAs), is presented. The proposed system consists of a Buck-type DC/DC power converter, which is controlled by an FPGA-based unit using the Pulse Width Modulation (PWM) principle. The system operator is able to define both the PV module type to be simulated and the environmental conditions under which the selected PV module operates. The proposed design method enhances the rapid system prototyping capability and enables the reduction of the power converter size and cost due to the high clock speed feature of the FPGA-based control unit. The experimental results indicate that, using the proposed method, the PV module current-voltage characteristics examined are reproduced with an average accuracy of 1.03%. (C) 2008 Elsevier Ltd. All rights reserved.

关键词： Photovoltaic system Simulator DC/DC converter field programmable gate array Rapid system prototyping

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Hardware Architectures for Computing Eigendecomposition-Based Discrete Fractional Fourier Transforms with Reduced Arithmetic Complexity

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2024年第1期43卷 593-614页

作者： Bispo, Breno C. de Oliveira Neto, Jose R. Lima, Juliano B. Univ Fed Pernambuco Dept Elect & Syst Recife PE Brazil Univ Fed Pernambuco Dept Mech Engn Recife PE Brazil

The fractional Fourier transform (FrFT) is a useful mathematical tool for signal and image processing. In some applications, the eigendecomposition-based discrete FrFT (DFrFT) is suitable due to its properties of orthogonality, additivity, reversibility and approximation of continuous FrFT. Although recent studies have introduced reduced arithmetic complexity algorithms for DFrFT computation, which are attractive for real-time and low-power consumption practical scenarios, reliable hardware architectures in this context are gaps in the literature. In this paper, we present two hardware architectures based on the referred algorithms to obtain N-point DFrFT (N = 4L, L is a positive integer). We validate and compare the performance of such architectures by employing field-programmable gate array implementations, co-designed with an embedded hard processor unit. In particular, we carry out computer experiments where synthesis, error and latency analyses are performed, and consider an application related to compact signal representation.

关键词： field programmable gate array Discrete fractional Fourier transform Hardware implementation Arithmetic complexity

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