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Timing error detection and correction for power efficiency: an aggressive scaling approach

IET CIRCUITS DEVICES & SYSTEMS 2018年第6期12卷 707-712页

作者： Rathnala, Prasanthi Wilmshurst, Tim Kharaz, Ahmad Univ Derby Dept Elect Comp & Math Coll Engn & Technol Derby DE22 3AW England

Low-power consumption has become an important aspect of processors and systems design. Many techniques ranging from architectural to system level are available. Voltage scaling or frequency boosting methods are the most effective to achieve low-power consumption as the dynamic power is proportional to the frequency and to the square of the supply voltage. The basic principle of operation of aggressive voltage scaling is to adjust the supply voltage to the lowest level possible to achieve minimum power consumption while maintaining reliable operations. Similarly, aggressive frequency boosting is to alter the operating frequency to achieve optimum performance improvement. In this study, an aggressive technique which employs voltage or frequency varying hardware circuit with the time-borrowing feature is presented. The proposed technique double samples the data to detect any timing violations as the frequency/voltage is scaled. The detected violations are masked by phase delaying the flip-flop clock to capture the late arrival data. This makes the system timing error tolerant without incurring error correction timing penalty. The proposed technique is implemented in a field programmable gate array using a two-stage arithmetic pipeline. Results on various benchmarks clearly demonstrate the achieved power savings and performance improvement.

关键词： error correction error detection power consumption flip-flops clocks field programmable gate arrays low-power electronics power efficiency aggressive scaling approach low-power consumption system level dynamic power supply voltage aggressive voltage scaling minimum power consumption aggressive frequency boosting time-borrowing feature system timing error tolerant error correction timing penalty power savings systems design processors error detection timing frequency varying hardware circuit flip-flop latch combination timing violation detection phase delaying field programmable gate array two-stage arithmetic pipeline

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A new methodology for single event transient suppression in flash FPGAs

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MICROPROCESSORS AND MICROSYSTEMS 2013年第3期37卷 313-318页

作者： Smith, Farouk Nelson Mandela Metropolitan Univ Summerstrand ZA-6031 Port Elizabeth South Africa

This paper describes a Single Event Transient (SET) suppression design technique for hardening combinational circuits against SETs in non-volatile field programmable gate arrays (FPGAs). The proposed method adds a SET suppressor circuit that is insensitive to SETs, to each primary output of a combinational circuit. The SET suppressor circuit consists of three components;an AND gate to suppress an SET reaching the primary output, when the primary output is logic '0', and an OR gate when the primary output is logic '1'. The third component is a simple two input multiplexer with its output connected to its own select line such that it will select the AND gate output when the combinational circuit primary output is logic '0' and the OR gate output when the primary output is logic '1'. A delay element is used to split each primary output of the combinational circuit into two signals. The two signals, one being the original primary output and the other a delayed copy of it, is sent to input one and input two of the SET suppressor. An alternative embodiment of the SET suppressor circuit is to use Double Modular Redundancy (DMR) instead of the delay element implementation. The SET Suppressor method is thoroughly tested on MCNC'91 benchmarks using the ModelSim simulator. The SET Suppressor circuit provides total immunity against SETs, however it does so with an area savings of 11.6-62.2% with respect to TMR when the delay element technique is use. When the DMR SET Suppressor technique is used, the area savings with respect TMR is between 16.1% and 31.9%. (c) 2012 Elsevier B.V. All rights reserved.

关键词： field programmable gate array Single event transient Single event upset Tripple Modular Redundancy Application Specific Integrated Circuits

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Heavy-Ion Micro Beam and Simulation Study of a Flash-Based FPGA Microcontroller Implementation

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2017年第1期64卷 504-511页

作者： Evans, Adrian Ortega, Carlos Urbina Marinis, Kostas Costenaro, Enrico Laroussi, Houssem Obbe, Kay-Voss Magistrati, Giorgio Ferlet-Cavrois, Veronique IROC Technol F-38000 Grenoble France European Space Agcy NL-2200 AG Noordwijk Netherlands Helmholtzzentrum Schwerionenforsch GSI D-64291 Darmstadt Germany

Flash-based FPGAs are frequently used in space applications and it is now common for such designs to include a small microcontroller. In this paper, we present the results of a detailed study of two implementations of an ARM (R) Cortex (R)-M0+ processor. The first implementation uses a standard design flow while the second implementation is protected with RHBD techniques including TMR flip-flops. Both designs were tested using a heavy-ion micro-beam using a methodology which enables individual ions to be localized both in space and time. The rate of silent data corruption (SDC) was only reduced by 5x in the protected version. Many, but not all, of the error scenarios were reproduced using simulation based fault injection. Overall, the results suggest that the contribution of single event transients (SETs) can not be neglected and the results show the limitations of flip-flop based TMR.

关键词： Embedded systems embedded processor field programmable gate array radiation hardening reliability single event transient (SET) single event upset (SEU) single event

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Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第1期69卷 75-85页

作者： He, Ke Crockett, Louise Stewart, Robert Univ Strathclyde EEE Dept Glasgow G1 1XW Lanark Scotland

Partial Reconfiguration (PR) is a method for field programmable gate array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design.

关键词： field programmable gate array Software defined radio Partial reconfiguration Dynamic reconfigurable port 3GPP LTE IEEE 802.16 IEEE 802.11 3GPP WCDMA

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HLS-Based Large Scale Self-Organizing Feature Maps

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IEEE ACCESS 2024年 12卷 142459-142474页

作者： Porrmann, Florian Hagemeyer, Jens Porrmann, Mario Bielefeld Univ Cognitron & Sensor Syst Grp CITEC D-33615 Bielefeld Germany Osnabruck Univ Inst Comp Sci Comp Engn Grp D-49090 Osnabruck Germany

The Self-Organizing Map (SOM) algorithm is a clustering algorithm used in a wide variety of application domains. Over the last few decades, it has been accelerated using various hardware architectures, including FPGAs, CPUs, and GPUs. This publication presents an High-Level Synthesis-based implementation that utilizes multiple processing elements to realize a high-performance system architecture. An extensive design space exploration was conducted to evaluate the performance range of the architecture. For this, vector dimensions ranging from 8 up to 512 and map sizes from 16x 16 to 512x512 were used. The evaluation was performed using two different AMD/Xilinx UltraScale+ FPGA systems, the VCU128 PCIe-based accelerator card and the ZCU106 stand-alone evaluation kit. From the achieved results, it can be seen that the performance scales nearly linearly for a given vector dimension when the map size is increased. In addition, the energy efficiency for both FPGAs was analyzed, revealing that while the ZCU106 is less powerful in terms of raw compute power, it requires up to 4x less power and, depending on the configuration, can be 2x more energy efficient compared to the VCU128. One of the main reasons for this is that it does not require a dedicated host system but utilizes its internal ARM cores. Finally, a comparison against state-of-the-art SOM implementations was conducted. The proposed design achieves a speed-up of up to 458.7, 1,630.4 , and 4.9 compared to other CPU, GPU, and FPGA realizations, respectively.

关键词： Neurons Computer architecture Clustering algorithms Training Graphics processing units Statistical analysis Space exploration Heterogeneous networks field programmable gate array hardware acceleration machine learning reconfigurable architectures reconfigurable computing heterogeneous computing heterogeneous architectures self-organizing feature maps optimization design space exploration heterogeneous architectures self-organizing feature maps optimization design space exploration

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Modified impedance source inverter for power conditioning system

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SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES 2017年第3期42卷 353-364页

作者： Suganthi, J. Rajaram, M. Govt Coll Engn Dept Elect & Elect Engn Tirunelveli 627007 India Anna Univ Madras 600025 Tamil Nadu India

Based on classical impedance source inverter concept, this paper presents a modified impedance source inverter controlled by different pulse width modulation control strategies for solar PV/battery-powered applications. A brief topology analysis, generalized discussion and design of impedance network elements are presented. Comparison with the classical impedance source inverter is presented. Using simulation, analytical results are presented that ensure stability. The proposed voltage type inverter has reduced inrush current at startup, less capacitor voltage stress and minimum inductor current ripples. DC link voltage boost, reduced total harmonic distortion of output current and voltage, better voltage gain and wide range of output voltage control can be achieved easily with improved power quality. Experimental set-up of the modified impedance source inverter with field programmable gate array (FPGA) controller has been constructed to ascertain the results.

关键词： Modified impedance source inverter power conditioning system cross conduction period modified space vector pulse width modulation field programmable gate array

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Hardware-software co-design architecture for Joint Photo Expert Graphic XR encoder

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IET IMAGE PROCESSING 2012年第9期6卷 1284-1292页

作者： Tseng, C. -F. Lai, Y. -T. Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

In recent years, because of to the fast growing of internet and digital multi-media, new image compression algorithms are needed to reduce the transferring bandwidth and the decay of image quality. Joint Photo Expert Graphic (JPEG) extended range (XR) is a new standard for still image compression. Compared to previous standards, it provides better image quality and plentiful pixel format. However, the better image quality often comes with the higher computation complexity. In this study, the authors propose a hardware-software co-design architecture for JPEG XR encoder. For photo overlap transform (POT), and photo core transform (PCT), the complicated parts of JPEG XR, the authors propose new algorithms which eliminate data dependency in the basic filters of POT and PCT so that operations can be executed in parallel. The processing rate of the new algorithms is much faster. The authors also demonstrate a basic filter with multiple functions, which can be time-shared by POT and PCT;the hardware cost can be therefore reduced. Moreover, a memory saving scheme is proposed. Therefore the proposed architecture is suitable for stand-alone application-specific integrated circuit (ASIC). In our co-design, POT and PCT are implemented in hardware and then mapped to field programmable gate array (FPGA), whereas the other procedures of JPEG XR such as quantisation are executed by ARM926-EJ processor. The overall performance of our hardware architecture is 50 fps for 4:4:4 HDTV format at 166 MHz.

关键词： frequency 166 MHz image quality ASIC Filtering methods in signal processing photo core transform ARM926-EJ processor data compression hardware-software codesign digital multimedia image compression algorithm JPEG XR encoder field programmable gate arrays Hardware-software codesign Internet Electronic engineering computing FPGA joint photo expert graphic XR encoder Computer vision and image processing techniques computer architecture Image and video coding still image compression application specific integrated circuits image coding hardware architecture photo overlap transform data dependency Integral transforms POT quantisation (signal) Logic circuits Computer architecture computation complexity quantisation JPEG extended range stand-alone application-specific integrated circuit PCT Logic and switching circuits memory saving scheme HDTV format filtering theory filter bandwidth transfer hardware-software co-design architecture field programmable gate array Digital circuit design, modelling and testing transforms

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Design of a Real Time FPGA-Based Three Dimensional Positioning Algorithm

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2011年第1期58卷 26-33页

作者： Johnson-Williams, Nathan G. Miyaoka, Robert S. Li, Xiaoli Lewellen, Tom K. Hauck, Scott Univ Washington Dept Elect Engn Seattle WA 98195 USA Univ Washington Dept Radiol Seattle WA 98195 USA Univ Washington Dept Phys Seattle WA 98195 USA

We report on the implementation and hardware platform of a real time Statistics-Based Positioning (SBP) method with depth of interaction processing for a positron emission tomography detector. The processing method works in conjunction with continuous miniature crystal element (cMiCE) detectors using a sensor on the entrance surface design. Our group previously reported on a field programmable gate array (FPGA) SBP implementation that provided a two dimensional (2D) detector positioning solution [1]. This new implementation extends that work to take advantage of three dimensional (3D) look up tables to provide a 3D positioning solution that improves intrinsic spatial resolution. Resolution is most improved along the edges of the crystal, an area where the 2D algorithm's performance suffers. The algorithm allows an intrinsic spatial resolution of similar to 0.90 mm FWHM in X and Y and a resolution of similar to 1.90 mm FWHM in Z (i.e., the depth of the crystal) based upon DETECT2000 simulation results that include the effects of Compton scatter in the crystal. A pipelined FPGA implementation is able to process events in excess of 220 K events per second, which is greater than the maximum expected coincidence rate for an individual detector. In contrast to all detectors being processed at a centralized host (as in the current system) a separate FPGA is available at each detector, thus dividing the computational load. A prototype design has been implemented and tested on an Altera Stratix II FPGA using a reduced word size due to memory limitations of our commercial prototyping board.

关键词： Data acquisition field programmable gate array maximum likelihood estimation

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FPGA-based SOC for hardware implementation of a local histogram-based video shot detector

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2017年第4期25卷 3300-3318页

作者： Ben Abdelali, Abdessalem Krifa, Mohamed Nidhal Mtibaa, Abdellatif Univ Monastir Lab Elect & Microelect Monastir Tunisia

In this paper, we present a video application example and its implementation in a reconfigurable system-on chip (SOC) platform. The proposed platform employs the benefits of field programmable gate array (FPGA) technology. A prototype based on a Xilinx Virtex-5 FPGA is developed. The application includes a video shot boundary detection module based on the local histogram (LH) technique. Diverse hardware module versions corresponding to different quantization levels and architectural solutions for an LH-based shot detection system are presented. The developed modules have different hardware resource occupations and can be used in a dynamic way to allow flexible management of the target hardware system. They also show high execution time efficiency and can reach an important bandwidth that can support the most recent high-resolution video formats with a high rate of frames per second. A complete SOC-based demonstration for video summarization based on the LH is also developed. It includes the LH extraction, shot boundary detection, and key frame visualization.

关键词： Hardware implementation field programmable gate array system on chip partial dynamic reconfiguration real time local histogram shot boundary detection video summarization

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Hardware co simulation of LTE physical layer for mobile network applications

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2019年 99卷 124-133页

作者： Venkataramanan, V. Lakshmi, S. Sathyabama Inst Sci & Technol Sch Elect & Elect Engn Dept Elect & Commun Chennai 119 Tamil Nadu India

Due to the rapid growth of wireless technology, it has become possible to provide solutions for fading, interference, and multipath. Long term evolution and Long term evolution Advanced systems describe the standards based on 3rd Generation partnership project to overcome issues related to wireless technology. These techniques mitigate the latency and improves the system capacity. The Long term evolution physical layer uses orthogonal frequency division multiple access for downlink, and Single carrier-frequency division multiple access for uplink. Therefore this study provides a comprehensive investigation of orthogonal frequency division multiple access and Single carrier-frequency division multiple access transmission model and investigate physical layer performance of Long term evolution system using MATLAB - Simulink - Xilinx system generator platform based on releases, simulation implementation;results may be discussed in terms of Register transfer level design, power estimation, and resource estimation. For synthesis and implementation of the above architecture Plan ahead tool on Virtex, device board is used. (C) 2018 Published by Elsevier B.V.

关键词： field programmable gate array Hardware co-simulation Long term evolution Multiple input multiple output Orthogonal frequency division multiplexing The 3rd generation partnership project

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