检索结果-内蒙古大学图书馆

A general-purpose framework for FPGA-accelerated genetic algorithms

INTERNATIONAL JOURNAL OF BIO-INSPIRED COMPUTATION 2015年第6期7卷 361-375页

作者： Guo, Liucheng Funie, Andreea Ingrid Xie, Zhongliu Thomas, David Luk, Wayne Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2AZ England

FPGA-based genetic algorithms (GAs) can effectively optimise complex applications, but require extensive hardware architecture customisation. To promote these accelerated GAs to potential users without hardware design experience, this study proposes a general-purpose automated framework for creating and executing a GA system on FPGAs. This framework contains scalable and customisable hardware architectures while providing a unified platform for different chromosomes. At compile-time, only a high-level input of the target application needs to be provided, without any hardware-specific code being necessary. At run-time, application inputs and GA parameters can be tuned, without time-consuming recompilation, for finding further good configurations of GA execution. The framework was tested on a high performance FPGA platform using nine problems and benchmarks, including the travelling salesman problem, a locating problem and the NP-hard set covering problem. Experiments show the system's flexibility and an average speedup of 29 times over a multi-core CPU.

关键词： genetic algorithm field programmable gate array FPGA automated framework

来源：评论

学校读者我要写书评

暂无评论

Distributed Deep Learning With GPU-FPGA Heterogeneous Computing

引用

IEEE MICRO 2021年第1期41卷 15-22页

作者： Tanaka, Kenji Arikawa, Yuki Ito, Tsuyoshi Morita, Kazutaka Nemoto, Naru Terada, Kazuhiko Teramoto, Junji Sakamoto, Takeshi NTT Corp NTT Device Technol Labs Atsugi Kanagawa 2430198 Japan NTT Corp NTT Software Innovat Ctr Tokyo 1808585 Japan

In distributed deep learning (DL), collective communication algorithms, such as Allreduce, used to share training results between graphical processing units (GPUs) are an inevitable bottleneck. We hypothesize that a cache access latency occurred at every Allreduce is a significant bottleneck in the current computational systems with high-bandwidth interconnects for distributed DL. To reduce this frequency of latency, it is important to aggregate data at the network interfaces. We implement a data aggregation circuit in a field-programmable gate array (FPGA). Using this FPGA, we proposed novel Allreduce architecture and training strategy without accuracy degradation. Results of the measurement show Allreduce latency reduction to 1/4. Our system can also conceal about 90% of the communication overhead and improve scalability by 20%. The end-to-end time consumed for training in distributed DL with ResNet-50 and ImageNet is reduced to 87.3% without any degradation in validation accuracy.

关键词： Cache Storage Data Aggregation Deep Learning Artificial Intelligence field programmable gate arrays Graphics Processing Units Neural Chips Distributed Deep Learning GPU FPGA Heterogeneous Computing Collective Communication Algorithms Graphical Processing Units Cache Access Latency High Bandwidth Interconnects Network Interfaces field programmable gate array Novel Allreduce Architecture Communication Overhead Distributed DL Training Strategy Allreduce Latency Reduction Res Net 50 Image Net field programmable gate arrays Random Access Memory Graphics Processing Units Training Data Distributed Databases Bandwidth Data Aggregation Deep Learning

来源：评论

学校读者我要写书评

暂无评论

Practical VHDL optimization for timing critical FPGA applications

引用

MICROPROCESSORS AND MICROSYSTEMS 1999年第8-9期23卷 459-469页

作者： Kuusilinna, K Hämäläinen, T Saarinen, J Tampere Univ Technol Signal Proc Lab FIN-33720 Tampere Finland

This paper gives a hands-on example of how low-level optimization of the VHSIC Hardware Description Language (VHDL) code is extremely difficult within a contemporary field programmable gate array (FPGA) design how. However, low-level optimization can be accomplished, and by changing the VHDL coding style synthesis results can be improved. The design flow is considered from high-level descriptions (bubble diagrams), through logic synthesis to the point where hand optimization is required. For performance benchmarking a state machine from a contemporary computer bus, PCI, implemented in a Xilinx FPGA, is used. Practical design issues applied to time-critical implementations using FPGAs, especially the trade-offs of high-level versus low-level synthesis, are analyzed. Performance evaluation results of several PCI target state machines, coded using different styles and design methods are given in terms of time and area efficiency. Based on these findings improvements to the FPGA design methodology are proposed. (C) 1999 Elsevier Science B.V. All rights reserved.

关键词： VHDL field programmable gate array synthesis PCI electronic design automation

来源：评论

学校读者我要写书评

暂无评论

Designing and FPGA evaluation of modified discrete Fourier transform for fault currents filtering

引用

JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS 2007年第1期30卷 173-178页

作者： Yu, Chi-Shan Natl Def Univ Chung Cheng Inst Technol Dept Elect Engn Tao Yuan 325 Taiwan

In protection relaying, the discrete Fourier transform (DFT) is the most widely used technique to obtain the fundamental phasor. However, when the fault current contains a decaying dc component, DFT can't obtain an accurate fundamental phasor. This work develops a modified discrete-Fourier-transform (MDFT) algorithm for fault currents filtering. Meanwhile, the field-programmable gate array (FPGA) is also used to evaluate the filter performance. Recursive computation is also developed to reduce the computation burden and FPGA logic elements utilization. The proposed algorithm is evaluated by some test cases in an FPGA environment. The results indicate that the proposed algorithm is accurate and has potential for practical applications.

关键词： fundamental phasor distance relay discrete Fourier transform field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Performance analysis of free space optical communication in open-atmospheric turbulence conditions with beam wandering compensation control

引用

IET COMMUNICATIONS 2016年第9期10卷 1096-1103页

作者： Anthonisamy, Arockia Bazil Raj Durairaj, Padmavathi Paul, Lancelot James Def Inst Adv Technol Elect Engn Pune Maharashtra India Thiagarajar Coll Engn Comp Sci & Engn Madurai Tamil Nadu India Indian Inst Astrophys Opt Div Bangalore Karnataka India

Among various atmospheric effects, beam wandering is the main cause for the major power loss in free space optical communication (FSOC) which cannot be resolved without incorporating the beam wandering compensation (BWC) control. To prove this prerequisite, a 155 Mbps data transmission experimental setup is built with necessary optoelectronic components for the link range of 0.5 km at an altitude of 15.25 m. A neuro-controller is developed inside the field programmable gate array and used to stabilise the received beam at the centre of the detector plane so as to perfectly couple the power in the bucket to the optical detector. The Q-factor and bit error rate variation profiles are calculated using the signal statistics obtained from the eye-diagram. The performance improvements on the FSOC system due to the incorporation of BWC control are investigated and discussed in terms of various communication quality assessment key parameters.

关键词： free-space optical communication optoelectronic devices field programmable gate arrays neurocontrollers beam steering compensation Q-factor error statistics atmospheric turbulence telecommunication computing performance analysis free space optical communication FSOC system open-atmospheric turbulence conditions beam wandering compensation control atmospheric effects power loss optoelectronic components neurocontroller field programmable gate array optical detector Q-factor bit error rate variation profiles signal statistics altitude 15 25 m bit rate 155 Mbit s

来源：评论

学校读者我要写书评

暂无评论

Modeling, simulation, and implementation issues of CPGs for neuromorphic engineering applications

引用

COMPUTER APPLICATIONS IN ENGINEERING EDUCATION 2018年第4期26卷 782-803页

作者： Korkmaz, Nimet Ozturk, Ismail Kilic, Recai Erciyes Univ Dept Elect & Elect Engn TR-38039 Kayseri Turkey Amasya Univ Dept Elect & Elect Engn Amasya Turkey

Neuromorphic engineering is a discipline used to develop hardware, which can mimic the characteristics and abilities of biological systems by investigating their physiological structures and data transfer mechanisms. The recent studies about the neuromorphic systems mostly consist of robotic applications whose designs are inspired by Central Pattern Generators (CPGs). CPGs are special neural networks which can produce coordinated rhythmic activity patterns and these rhythmic movements are modeled mathematically, tested with simulation programs and verified by hardware implementations. A reconfigurable hardware platform (field programmable gate array FPGA) is compatible with numerical simulation tools, allows software control over hardware, has a user-friendly interface and allows real time modifications. Thus, recently, it is preferred in CPG based robotic applications. In this study, the details of the modeling, simulation and implementation stages of several CPG structures are introduced by using a digital reconfigurable hardware platform. In order to show the conceptual learning achievements of these stages and to assess the contribution to the modeling, simulation and implementation skills of the students, a training course has been planned for the undergraduate students at Erciyes University. This process has been held in an educative manner supported by a survey and an experimental examination, so that this training course has been evaluated by the trainees in terms of the advantage, practicality, and challenge.

关键词： Central Pattern Generators engineering education field programmable gate array neuromorphic engineering

来源：评论

学校读者我要写书评

暂无评论

Real-time simulation of modular multilevel converters for controller hardware-in-the-loop testing

引用

IET POWER ELECTRONICS 2016年第1期9卷 42-50页

作者： Matar, Mahmoud Paradis, Dominic Iravani, Reza Univ Toronto Ctr Appl Power Elect Toronto ON Canada Ain Shams Univ Elect Power & Machines Dept Cairo Egypt Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

This study presents a field programmable gate array (FPGA)-based real-time simulation platform for realistic-size modular multilevel converters (MMCs). This development is primarily intended for controller hardware-in-the-loop (HIL) testing for MMC-based high-voltage direct current (HVDC) transmission systems. Although the real-time simulation of MMC-based systems is particularly challenging due to the presence of thousands of power electronic switches, yet, it is still possible based on adopting a computationally efficient MMC model and the use of a high-performance parallel computational engine. This study focuses on the design and implementation of the parallel computational engine that solves the mathematical model of an enhanced computationally efficient MMC model on the FPGA platform. Moreover, provided are the implementation results and their verifications corresponding to the real-time simulation of a 401-level MMC and the HIL testing of the controllers of the 401-level MMC-HVDC link between France and Spain.

关键词： field programmable gate arrays HVDC power transmission power convertors real-time simulation modular multilevel converters controller hardware-in-the-loop testing field programmable gate array FPGA-based real-time simulation platform realistic-size modular multilevel converters HIL testing MMC-based high-voltage direct current transmission systems HVDC transmission systems power electronic switches parallel computational engine

来源：评论

学校读者我要写书评

暂无评论

FPGA-Based Web Services - Infinite Potential or a Road to Nowhere?

引用

IEEE INTERNET COMPUTING 2016年第1期20卷 44-51页

作者： Brzoza-Woch, Robert Nawrocki, Piotr AGH Univ Sci & Technol Dept Comp Sci PL-30059 Krakow Poland

field-programmable gate array (FPGA) technology could have significant potential in the construction of Web services, but it generates multiple issues that software and hardware designers must overcome first. As a Web service hardware platform, the FPGA could be an experimental yet interesting and powerful alternative to standard solutions based on microprocessors and microcontrollers. Here, the authors share their thoughts about the possibility of using FPGA chips to implement environment-aware embedded Web services.

关键词： field programmable gate arrays Internet Web Services Economics Distributed Processing Ubiquitous Computing Internet Of Things Ubiquitous Computing Internet Web Technologies Io T Internet Of Things FPGA field programmable gate array Web Services Distributed Systems Data Path Design

来源：评论

学校读者我要写书评

暂无评论

Jitter-Quantizing-Based TRNG Robust Against PVT Variations

引用

IEEE ACCESS 2020年 8卷 108482-108490页

作者： Lu, Yingchun Liang, Huaguo Yao, Liang Wang, Xinyu Qi, Haochen Yi, Maoxiang Jiang, Cuiyun Huang, Zhengfeng Hefei Univ Technol Sch Elect Sci & Appl Phys Hefei 230009 Peoples R China Hefei Univ Technol Sch Math Hefei 230009 Peoples R China

Security is critical to the growing popularity of the Internet of Things(IoT), and true random number generator (TRNG) plays an increasingly important role in information security systems. Conventional TRNGs use natural physical stochastic processes including thermal noise, chaos-based circuit, and so on to generate random numbers. These analog circuits based TRNG structures often consume excessive hardware resources. Meanwhile, it is difficult to incorporate them into digital system. In this paper, a novel all-digital true random number generator in SRAM-based FPGAs is proposed by using Vernier technique that precisely quantize random edge jitter. The proposed TRNG design is implemented on Xilinx Virtex-6 XC6VLX240T-1FF1156 FPGA and shows a high quality of randomness which has passed the NIST test suite with relatively high p-values, achieves a high throughput of 127 Mbps with occupying 32 slices. Experimental results show a good tolerance to bias phenomenon induced by process, voltage, and temperature variations.

关键词： True random number generator Vernier technique field programmable gate array high throughput

来源：评论

学校读者我要写书评

暂无评论

Generic systolic array for genetic algorithms

引用

IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1997年第2期144卷 107-119页

作者： Megson, GM Bland, IM Laboratory of Chromatography DEPg.Fac.Quimica Universidad Nacional Autonoma de Mexico Circuito interior Cd Universitaria/CP 04510 Mexico D.F.Mexico

The authors present a systolic design for a simple GA mechanism which provides high throughput and unidirectional pipelining by exploiting the inherent parallelism in the genetic operators. The design computes in O(N + G) time steps using O(N-2) cells where N is the population size and G is the chromosome length. The area of the device is independent of the chromosome length and so can be easily scaled by replicating the arrays or by employing fine-grain migration. The array is generic in the sense that it does not rely on the fitness function and can be used as an accelerator for any GA application using uniform crossover between pairs of chromosomes. The design can also be used in hybrid systems as an complement existing designs and fitness function acceleration and island-style population management.

关键词： field programmable gate array optimisation algorithm systolic array

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：