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Distortion correction for a wide-angle on real-time lens based digital image processing

OPTICAL ENGINEERING 2003年第7期42卷 2029-2039页

作者： Jiang, J Zhang, GJ Zhou, FQ Yu, DY Xie, HB Liu, H Beijing Univ Aeronaut & Astronaut Beijing Sch Automat Sci & Elect Engn Beijing 100083 Peoples R China Tianjin Univ Sch Precis Instrument & Optoelect Engn Tianjin 300072 Peoples R China

Images captured with wide-angle lenses suffer from spatial distortion, which prevents accurate measure and feature extraction. In this work, a mathematical model based on polynomial mapping is used to map the images from distorted image space onto the corrected image space. The model parameters include the polynomial coefficients, distortion center, and dot center. A new technique to estimate the distortion center based on the evaluation function is presented. In dot center estimation, a seed fill algorithm is used to traverse all pixels. The expansion polynomial was obtained by using cubic spline interpolation. With a field programmable gate array (FPGA), the real-time distortion correction is implemented, which is independent of a computer. The major benefit using FPGA is that the same circuit can be used for other circularly symmetric wide-angle lenses without being modified. (C) 2003 Society of Photo-Optical Instrumentation Engineers.

关键词： distortion correction real-time digital image processing wide-angle lens field programmable gate array

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Development of an FPGA-based system for real-time simulation of photovoltaic modules

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MICROELECTRONICS JOURNAL 2009年第7期40卷 1094-1102页

作者： Koutroulis, Eftichios Kalaitzakis, Kostas Tzitzilonis, Vasileios Tech Univ Crete Dept Elect & Comp Engn GR-73100 Khania Crete Greece

Photovoltaic (PV) simulators are indispensable for the operational evaluation of PV energy production system components (e.g. battery chargers, DC/AC inverters, etc.), in order to avoid the time-consuming and expensive field-testing process. In this paper, the development of a novel real-time PV simulator based on field programmable gate arrays (FPGAs), is presented. The proposed system consists of a Buck-type DC/DC power converter, which is controlled by an FPGA-based unit using the Pulse Width Modulation (PWM) principle. The system operator is able to define both the PV module type to be simulated and the environmental conditions under which the selected PV module operates. The proposed design method enhances the rapid system prototyping capability and enables the reduction of the power converter size and cost due to the high clock speed feature of the FPGA-based control unit. The experimental results indicate that, using the proposed method, the PV module current-voltage characteristics examined are reproduced with an average accuracy of 1.03%. (C) 2008 Elsevier Ltd. All rights reserved.

关键词： Photovoltaic system Simulator DC/DC converter field programmable gate array Rapid system prototyping

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Distributed Deep Learning With GPU-FPGA Heterogeneous Computing

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IEEE MICRO 2021年第1期41卷 15-22页

作者： Tanaka, Kenji Arikawa, Yuki Ito, Tsuyoshi Morita, Kazutaka Nemoto, Naru Terada, Kazuhiko Teramoto, Junji Sakamoto, Takeshi NTT Corp NTT Device Technol Labs Atsugi Kanagawa 2430198 Japan NTT Corp NTT Software Innovat Ctr Tokyo 1808585 Japan

In distributed deep learning (DL), collective communication algorithms, such as Allreduce, used to share training results between graphical processing units (GPUs) are an inevitable bottleneck. We hypothesize that a cache access latency occurred at every Allreduce is a significant bottleneck in the current computational systems with high-bandwidth interconnects for distributed DL. To reduce this frequency of latency, it is important to aggregate data at the network interfaces. We implement a data aggregation circuit in a field-programmable gate array (FPGA). Using this FPGA, we proposed novel Allreduce architecture and training strategy without accuracy degradation. Results of the measurement show Allreduce latency reduction to 1/4. Our system can also conceal about 90% of the communication overhead and improve scalability by 20%. The end-to-end time consumed for training in distributed DL with ResNet-50 and ImageNet is reduced to 87.3% without any degradation in validation accuracy.

关键词： Cache Storage Data Aggregation Deep Learning Artificial Intelligence field programmable gate arrays Graphics Processing Units Neural Chips Distributed Deep Learning GPU FPGA Heterogeneous Computing Collective Communication Algorithms Graphical Processing Units Cache Access Latency High Bandwidth Interconnects Network Interfaces field programmable gate array Novel Allreduce Architecture Communication Overhead Distributed DL Training Strategy Allreduce Latency Reduction Res Net 50 Image Net field programmable gate arrays Random Access Memory Graphics Processing Units Training Data Distributed Databases Bandwidth Data Aggregation Deep Learning

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A general-purpose framework for FPGA-accelerated genetic algorithms

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INTERNATIONAL JOURNAL OF BIO-INSPIRED COMPUTATION 2015年第6期7卷 361-375页

作者： Guo, Liucheng Funie, Andreea Ingrid Xie, Zhongliu Thomas, David Luk, Wayne Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2AZ England

FPGA-based genetic algorithms (GAs) can effectively optimise complex applications, but require extensive hardware architecture customisation. To promote these accelerated GAs to potential users without hardware design experience, this study proposes a general-purpose automated framework for creating and executing a GA system on FPGAs. This framework contains scalable and customisable hardware architectures while providing a unified platform for different chromosomes. At compile-time, only a high-level input of the target application needs to be provided, without any hardware-specific code being necessary. At run-time, application inputs and GA parameters can be tuned, without time-consuming recompilation, for finding further good configurations of GA execution. The framework was tested on a high performance FPGA platform using nine problems and benchmarks, including the travelling salesman problem, a locating problem and the NP-hard set covering problem. Experiments show the system's flexibility and an average speedup of 29 times over a multi-core CPU.

关键词： genetic algorithm field programmable gate array FPGA automated framework

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Hardware Architectures for Computing Eigendecomposition-Based Discrete Fractional Fourier Transforms with Reduced Arithmetic Complexity

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2024年第1期43卷 593-614页

作者： Bispo, Breno C. de Oliveira Neto, Jose R. Lima, Juliano B. Univ Fed Pernambuco Dept Elect & Syst Recife PE Brazil Univ Fed Pernambuco Dept Mech Engn Recife PE Brazil

The fractional Fourier transform (FrFT) is a useful mathematical tool for signal and image processing. In some applications, the eigendecomposition-based discrete FrFT (DFrFT) is suitable due to its properties of orthogonality, additivity, reversibility and approximation of continuous FrFT. Although recent studies have introduced reduced arithmetic complexity algorithms for DFrFT computation, which are attractive for real-time and low-power consumption practical scenarios, reliable hardware architectures in this context are gaps in the literature. In this paper, we present two hardware architectures based on the referred algorithms to obtain N-point DFrFT (N = 4L, L is a positive integer). We validate and compare the performance of such architectures by employing field-programmable gate array implementations, co-designed with an embedded hard processor unit. In particular, we carry out computer experiments where synthesis, error and latency analyses are performed, and consider an application related to compact signal representation.

关键词： field programmable gate array Discrete fractional Fourier transform Hardware implementation Arithmetic complexity

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Designing and FPGA evaluation of modified discrete Fourier transform for fault currents filtering

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JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS 2007年第1期30卷 173-178页

作者： Yu, Chi-Shan Natl Def Univ Chung Cheng Inst Technol Dept Elect Engn Tao Yuan 325 Taiwan

In protection relaying, the discrete Fourier transform (DFT) is the most widely used technique to obtain the fundamental phasor. However, when the fault current contains a decaying dc component, DFT can't obtain an accurate fundamental phasor. This work develops a modified discrete-Fourier-transform (MDFT) algorithm for fault currents filtering. Meanwhile, the field-programmable gate array (FPGA) is also used to evaluate the filter performance. Recursive computation is also developed to reduce the computation burden and FPGA logic elements utilization. The proposed algorithm is evaluated by some test cases in an FPGA environment. The results indicate that the proposed algorithm is accurate and has potential for practical applications.

关键词： fundamental phasor distance relay discrete Fourier transform field programmable gate array

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Practical VHDL optimization for timing critical FPGA applications

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MICROPROCESSORS AND MICROSYSTEMS 1999年第8-9期23卷 459-469页

作者： Kuusilinna, K Hämäläinen, T Saarinen, J Tampere Univ Technol Signal Proc Lab FIN-33720 Tampere Finland

This paper gives a hands-on example of how low-level optimization of the VHSIC Hardware Description Language (VHDL) code is extremely difficult within a contemporary field programmable gate array (FPGA) design how. However, low-level optimization can be accomplished, and by changing the VHDL coding style synthesis results can be improved. The design flow is considered from high-level descriptions (bubble diagrams), through logic synthesis to the point where hand optimization is required. For performance benchmarking a state machine from a contemporary computer bus, PCI, implemented in a Xilinx FPGA, is used. Practical design issues applied to time-critical implementations using FPGAs, especially the trade-offs of high-level versus low-level synthesis, are analyzed. Performance evaluation results of several PCI target state machines, coded using different styles and design methods are given in terms of time and area efficiency. Based on these findings improvements to the FPGA design methodology are proposed. (C) 1999 Elsevier Science B.V. All rights reserved.

关键词： VHDL field programmable gate array synthesis PCI electronic design automation

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Modeling, simulation, and implementation issues of CPGs for neuromorphic engineering applications

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COMPUTER APPLICATIONS IN ENGINEERING EDUCATION 2018年第4期26卷 782-803页

作者： Korkmaz, Nimet Ozturk, Ismail Kilic, Recai Erciyes Univ Dept Elect & Elect Engn TR-38039 Kayseri Turkey Amasya Univ Dept Elect & Elect Engn Amasya Turkey

Neuromorphic engineering is a discipline used to develop hardware, which can mimic the characteristics and abilities of biological systems by investigating their physiological structures and data transfer mechanisms. The recent studies about the neuromorphic systems mostly consist of robotic applications whose designs are inspired by Central Pattern Generators (CPGs). CPGs are special neural networks which can produce coordinated rhythmic activity patterns and these rhythmic movements are modeled mathematically, tested with simulation programs and verified by hardware implementations. A reconfigurable hardware platform (field programmable gate array FPGA) is compatible with numerical simulation tools, allows software control over hardware, has a user-friendly interface and allows real time modifications. Thus, recently, it is preferred in CPG based robotic applications. In this study, the details of the modeling, simulation and implementation stages of several CPG structures are introduced by using a digital reconfigurable hardware platform. In order to show the conceptual learning achievements of these stages and to assess the contribution to the modeling, simulation and implementation skills of the students, a training course has been planned for the undergraduate students at Erciyes University. This process has been held in an educative manner supported by a survey and an experimental examination, so that this training course has been evaluated by the trainees in terms of the advantage, practicality, and challenge.

关键词： Central Pattern Generators engineering education field programmable gate array neuromorphic engineering

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Performance analysis of free space optical communication in open-atmospheric turbulence conditions with beam wandering compensation control

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IET COMMUNICATIONS 2016年第9期10卷 1096-1103页

作者： Anthonisamy, Arockia Bazil Raj Durairaj, Padmavathi Paul, Lancelot James Def Inst Adv Technol Elect Engn Pune Maharashtra India Thiagarajar Coll Engn Comp Sci & Engn Madurai Tamil Nadu India Indian Inst Astrophys Opt Div Bangalore Karnataka India

Among various atmospheric effects, beam wandering is the main cause for the major power loss in free space optical communication (FSOC) which cannot be resolved without incorporating the beam wandering compensation (BWC) control. To prove this prerequisite, a 155 Mbps data transmission experimental setup is built with necessary optoelectronic components for the link range of 0.5 km at an altitude of 15.25 m. A neuro-controller is developed inside the field programmable gate array and used to stabilise the received beam at the centre of the detector plane so as to perfectly couple the power in the bucket to the optical detector. The Q-factor and bit error rate variation profiles are calculated using the signal statistics obtained from the eye-diagram. The performance improvements on the FSOC system due to the incorporation of BWC control are investigated and discussed in terms of various communication quality assessment key parameters.

关键词： free-space optical communication optoelectronic devices field programmable gate arrays neurocontrollers beam steering compensation Q-factor error statistics atmospheric turbulence telecommunication computing performance analysis free space optical communication FSOC system open-atmospheric turbulence conditions beam wandering compensation control atmospheric effects power loss optoelectronic components neurocontroller field programmable gate array optical detector Q-factor bit error rate variation profiles signal statistics altitude 15 25 m bit rate 155 Mbit s

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FPGA-Based Web Services - Infinite Potential or a Road to Nowhere?

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IEEE INTERNET COMPUTING 2016年第1期20卷 44-51页

作者： Brzoza-Woch, Robert Nawrocki, Piotr AGH Univ Sci & Technol Dept Comp Sci PL-30059 Krakow Poland

field-programmable gate array (FPGA) technology could have significant potential in the construction of Web services, but it generates multiple issues that software and hardware designers must overcome first. As a Web service hardware platform, the FPGA could be an experimental yet interesting and powerful alternative to standard solutions based on microprocessors and microcontrollers. Here, the authors share their thoughts about the possibility of using FPGA chips to implement environment-aware embedded Web services.

关键词： field programmable gate arrays Internet Web Services Economics Distributed Processing Ubiquitous Computing Internet Of Things Ubiquitous Computing Internet Web Technologies Io T Internet Of Things FPGA field programmable gate array Web Services Distributed Systems Data Path Design

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