Images captured with wide-angle lenses suffer from spatial distortion, which prevents accurate measure and feature extraction. In this work, a mathematical model based on polynomial mapping is used to map the images f...
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Images captured with wide-angle lenses suffer from spatial distortion, which prevents accurate measure and feature extraction. In this work, a mathematical model based on polynomial mapping is used to map the images from distorted image space onto the corrected image space. The model parameters include the polynomial coefficients, distortion center, and dot center. A new technique to estimate the distortion center based on the evaluation function is presented. In dot center estimation, a seed fill algorithm is used to traverse all pixels. The expansion polynomial was obtained by using cubic spline interpolation. With a field programmable gate array (FPGA), the real-time distortion correction is implemented, which is independent of a computer. The major benefit using FPGA is that the same circuit can be used for other circularly symmetric wide-angle lenses without being modified. (C) 2003 Society of Photo-Optical Instrumentation Engineers.
This paper gives a hands-on example of how low-level optimization of the VHSIC Hardware Description Language (VHDL) code is extremely difficult within a contemporary field programmable gate array (FPGA) design how. Ho...
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This paper gives a hands-on example of how low-level optimization of the VHSIC Hardware Description Language (VHDL) code is extremely difficult within a contemporary field programmable gate array (FPGA) design how. However, low-level optimization can be accomplished, and by changing the VHDL coding style synthesis results can be improved. The design flow is considered from high-level descriptions (bubble diagrams), through logic synthesis to the point where hand optimization is required. For performance benchmarking a state machine from a contemporary computer bus, PCI, implemented in a Xilinx FPGA, is used. Practical design issues applied to time-critical implementations using FPGAs, especially the trade-offs of high-level versus low-level synthesis, are analyzed. Performance evaluation results of several PCI target state machines, coded using different styles and design methods are given in terms of time and area efficiency. Based on these findings improvements to the FPGA design methodology are proposed. (C) 1999 Elsevier Science B.V. All rights reserved.
In protection relaying, the discrete Fourier transform (DFT) is the most widely used technique to obtain the fundamental phasor. However, when the fault current contains a decaying dc component, DFT can't obtain a...
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In protection relaying, the discrete Fourier transform (DFT) is the most widely used technique to obtain the fundamental phasor. However, when the fault current contains a decaying dc component, DFT can't obtain an accurate fundamental phasor. This work develops a modified discrete-Fourier-transform (MDFT) algorithm for fault currents filtering. Meanwhile, the field-programmablegatearray (FPGA) is also used to evaluate the filter performance. Recursive computation is also developed to reduce the computation burden and FPGA logic elements utilization. The proposed algorithm is evaluated by some test cases in an FPGA environment. The results indicate that the proposed algorithm is accurate and has potential for practical applications.
FPGA-based genetic algorithms (GAs) can effectively optimise complex applications, but require extensive hardware architecture customisation. To promote these accelerated GAs to potential users without hardware design...
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FPGA-based genetic algorithms (GAs) can effectively optimise complex applications, but require extensive hardware architecture customisation. To promote these accelerated GAs to potential users without hardware design experience, this study proposes a general-purpose automated framework for creating and executing a GA system on FPGAs. This framework contains scalable and customisable hardware architectures while providing a unified platform for different chromosomes. At compile-time, only a high-level input of the target application needs to be provided, without any hardware-specific code being necessary. At run-time, application inputs and GA parameters can be tuned, without time-consuming recompilation, for finding further good configurations of GA execution. The framework was tested on a high performance FPGA platform using nine problems and benchmarks, including the travelling salesman problem, a locating problem and the NP-hard set covering problem. Experiments show the system's flexibility and an average speedup of 29 times over a multi-core CPU.
In distributed deep learning (DL), collective communication algorithms, such as Allreduce, used to share training results between graphical processing units (GPUs) are an inevitable bottleneck. We hypothesize that a c...
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In distributed deep learning (DL), collective communication algorithms, such as Allreduce, used to share training results between graphical processing units (GPUs) are an inevitable bottleneck. We hypothesize that a cache access latency occurred at every Allreduce is a significant bottleneck in the current computational systems with high-bandwidth interconnects for distributed DL. To reduce this frequency of latency, it is important to aggregate data at the network interfaces. We implement a data aggregation circuit in a field-programmablegatearray (FPGA). Using this FPGA, we proposed novel Allreduce architecture and training strategy without accuracy degradation. Results of the measurement show Allreduce latency reduction to 1/4. Our system can also conceal about 90% of the communication overhead and improve scalability by 20%. The end-to-end time consumed for training in distributed DL with ResNet-50 and ImageNet is reduced to 87.3% without any degradation in validation accuracy.
field-programmablegatearray (FPGA) technology could have significant potential in the construction of Web services, but it generates multiple issues that software and hardware designers must overcome first. As a Web...
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field-programmablegatearray (FPGA) technology could have significant potential in the construction of Web services, but it generates multiple issues that software and hardware designers must overcome first. As a Web service hardware platform, the FPGA could be an experimental yet interesting and powerful alternative to standard solutions based on microprocessors and microcontrollers. Here, the authors share their thoughts about the possibility of using FPGA chips to implement environment-aware embedded Web services.
This study presents a field programmable gate array (FPGA)-based real-time simulation platform for realistic-size modular multilevel converters (MMCs). This development is primarily intended for controller hardware-in...
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This study presents a field programmable gate array (FPGA)-based real-time simulation platform for realistic-size modular multilevel converters (MMCs). This development is primarily intended for controller hardware-in-the-loop (HIL) testing for MMC-based high-voltage direct current (HVDC) transmission systems. Although the real-time simulation of MMC-based systems is particularly challenging due to the presence of thousands of power electronic switches, yet, it is still possible based on adopting a computationally efficient MMC model and the use of a high-performance parallel computational engine. This study focuses on the design and implementation of the parallel computational engine that solves the mathematical model of an enhanced computationally efficient MMC model on the FPGA platform. Moreover, provided are the implementation results and their verifications corresponding to the real-time simulation of a 401-level MMC and the HIL testing of the controllers of the 401-level MMC-HVDC link between France and Spain.
Security is critical to the growing popularity of the Internet of Things(IoT), and true random number generator (TRNG) plays an increasingly important role in information security systems. Conventional TRNGs use natur...
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Security is critical to the growing popularity of the Internet of Things(IoT), and true random number generator (TRNG) plays an increasingly important role in information security systems. Conventional TRNGs use natural physical stochastic processes including thermal noise, chaos-based circuit, and so on to generate random numbers. These analog circuits based TRNG structures often consume excessive hardware resources. Meanwhile, it is difficult to incorporate them into digital system. In this paper, a novel all-digital true random number generator in SRAM-based FPGAs is proposed by using Vernier technique that precisely quantize random edge jitter. The proposed TRNG design is implemented on Xilinx Virtex-6 XC6VLX240T-1FF1156 FPGA and shows a high quality of randomness which has passed the NIST test suite with relatively high p-values, achieves a high throughput of 127 Mbps with occupying 32 slices. Experimental results show a good tolerance to bias phenomenon induced by process, voltage, and temperature variations.
The fractional Fourier transform (FrFT) is a useful mathematical tool for signal and image processing. In some applications, the eigendecomposition-based discrete FrFT (DFrFT) is suitable due to its properties of orth...
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The fractional Fourier transform (FrFT) is a useful mathematical tool for signal and image processing. In some applications, the eigendecomposition-based discrete FrFT (DFrFT) is suitable due to its properties of orthogonality, additivity, reversibility and approximation of continuous FrFT. Although recent studies have introduced reduced arithmetic complexity algorithms for DFrFT computation, which are attractive for real-time and low-power consumption practical scenarios, reliable hardware architectures in this context are gaps in the literature. In this paper, we present two hardware architectures based on the referred algorithms to obtain N-point DFrFT (N = 4L, L is a positive integer). We validate and compare the performance of such architectures by employing field-programmablegatearray implementations, co-designed with an embedded hard processor unit. In particular, we carry out computer experiments where synthesis, error and latency analyses are performed, and consider an application related to compact signal representation.
Among various atmospheric effects, beam wandering is the main cause for the major power loss in free space optical communication (FSOC) which cannot be resolved without incorporating the beam wandering compensation (B...
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Among various atmospheric effects, beam wandering is the main cause for the major power loss in free space optical communication (FSOC) which cannot be resolved without incorporating the beam wandering compensation (BWC) control. To prove this prerequisite, a 155 Mbps data transmission experimental setup is built with necessary optoelectronic components for the link range of 0.5 km at an altitude of 15.25 m. A neuro-controller is developed inside the field programmable gate array and used to stabilise the received beam at the centre of the detector plane so as to perfectly couple the power in the bucket to the optical detector. The Q-factor and bit error rate variation profiles are calculated using the signal statistics obtained from the eye-diagram. The performance improvements on the FSOC system due to the incorporation of BWC control are investigated and discussed in terms of various communication quality assessment key parameters.
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