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An efficient hybrid learning algorithm for neural network-based speech recognition systems on FPGA chip

NEURAL COMPUTING & APPLICATIONS 2014年第7-8期24卷 1879-1885页

作者： Pan, Shing-Tai Lan, Min-Lun Natl Univ Kaohsiung Dept Comp Sci & Informat Engn Kaohsiung 811 Taiwan Shu Te Univ Inst Comp Sci & Informat Engn Kaohsiung 824 Taiwan

This paper implemented an artificial neural network (ANN) on a field programmable gate array (FPGA) chip for Mandarin speech measurement and recognition of nonspecific speaker. A three-layer hybrid learning algorithm (HLA), which combines genetic algorithm (GA) and steepest descent method, was proposed to fulfill a faster global search of optimal weights in ANN. Some other popular evolutionary algorithms, such as differential evolution, particle swarm optimization and improve GA, were compared to the proposed HLA. It can be seen that the proposed HLA algorithm outperforms the other algorithms. Finally, the designed system was implemented on an FPGA chip with an SOC architecture to measure and recognize the speech signals.

关键词： field programmable gate array Genetic algorithm Hybrid learning algorithm Speech recognition

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Analytic Model Predictive Controller for Collision-Free Relative Motion Reconfiguration

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JOURNAL OF GUIDANCE CONTROL AND DYNAMICS 2012年第4期35卷 1069-1079页

作者： Sauter, Luke Palmer, P. Univ Surrey Surrey Space Ctr Surrey GU2 7XH England

Large formations of satellites currently require extensive ground-based planning to enable formation-wide collision-free reconfiguration. Allowing satellite formations the flexibility to execute collision-free reconfiguration operations onboard each spacecraft can significantly reduce the ground operations burden and increase the responsiveness of the formation to reconfiguration events. An analytic model predictive controller for fuel-minimized, collision-free trajectory following is developed. The controller exploits the natural dynamics for relative-motion path-following using minimal fuel and requires a minimal computational burden. Constraints are handled implicitly and performance provides 423 times the fuel savings compared with traditional proportional-integral-derivative-type control at the same computational speed. Through hardware testing and comparison with other approaches, results also show that constraints can also be handled explicitly while still performing significantly faster than similar forms of model predictive control for formation reconfiguration.

关键词： Proportional Integral Derivative Monolithic Satellite Quadratic Programming Time Optimal Control Defense Advanced Research Projects Agencies Formation Flying Path Planning Central Processing Unit Fractionated Satellite Systems field programmable gate array

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Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm

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IET CIRCUITS DEVICES & SYSTEMS 2016年第4期10卷 309-316页

作者： Puthenpurayil, Shiju Padmanabhan Chakrabarti, Indrajit Virdi, Rishi Kaushik, Harsh Indian Inst Technol Elect & Elect Commun Engn Dept Kharagpur 721302 W Bengal India

This study introduces an architecture for motion estimation block of the video encoder using adaptive rood pattern search (ARPS) algorithm. The architecture has been designed for field programmable gate array (FPGA) as well as application specific integrated circuit (ASIC) implementations. Experimental results show that the speed of ARPS algorithm is ahead of several existing fast motion estimation algorithms without compromising the peak signal-to-noise ratio values. The Virtex-4 FPGA implementation of the proposed architecture using Xilinx 14.2 attains a maximum frequency of 103 MHz with <3% usage of slices. ASIC implementation of the proposed architecture with Synopsys design vision tool (0.18 mu m) using 100 MHz frequency involves power consumption of 4.54 mW and occupies 0.073 mm(2). A maximum frequency of 333 MHz has been achieved for the ASIC implementation with 16 x 16 blocks and it can process 651 frames of slow motion video such as Akiyo and 280 frames of fast motion video such as Football of CIF format (352 x 288 resolution) per second. Moreover, the ASIC implementation can process up to 31 frames of HD (1920 x 1080 resolution) video per second. Hence, the proposed architecture fits well in applications such as video conferencing and video phones.

关键词： motion estimation image matching video coding search problems VLSI field programmable gate arrays application specific integrated circuits very large scale integration architecture adaptive rood pattern search algorithm block-matching motion estimation video encoder ARPS algorithm field programmable gate array application specific integrated circuit ASIC peak signal-to-noise ratio Virtex-4 FPGA Xilinx 14 2 Synopsys design vision tool size 0 18 mum frequency 100 MHz power 4 54 mW

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FPGA Implementation of Sparsity Independent Regularized Pursuit for Fast CS Reconstruction

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第4期69卷 1617-1628页

作者： Thomas, Thomas James Rani, J. Sheeba Indian Inst Space Sci & Technol Dept Av Thiruvananthapuram 695547 Kerala India

Sparse recovery algorithms are integral to compressed sensing (CS) as they facilitate the reconstruction of higher dimensional signals from sub-Nyquist measurements. Although Orthogonal Matching Pursuit (OMP) has been ubiquitously adopted in hardware implementations to curb the computational complexity of CS recovery, increasing sparsity levels incur higher reconstruction costs. Sparsity independent regularized pursuit (SIRP) is a recent algorithm that employs parallel index selection and regularization to curtail the number of iterations required to reconstruct the signal and thereby enhance the reconstruction speed. This paper proposes a novel reformulation of the SIRP algorithm from the hardware perspective, incorporating a cheaper regularization strategy and a modified Gram-Schmidt (MGS) based incremental QR decomposition (QRD) approach. The proposed design incorporates an iterative QRD architecture with feedback circuitry to exploit the parallelism of the triangularization step in MGS. Additionally, a fast inverse square block circumvents the need for parallel divider blocks giving considerable hardware and latency savings. The design reuses the iterative QRD block to implement the interdependent computations of the algorithm by sophisticated scheduling techniques. The proposed implementation on a Xilinx Virtex Ultrascale FPGA can recover 1024-dimensional signals from 25% measurements within 77 mu s, which translates to a 37% reduction in processing cycles from state-of-art.

关键词： Matching pursuit algorithms field programmable gate arrays Hardware Indexes Computer architecture Estimation Costs Compressed sensing orthogonal matching pursuit QR decomposition modified Gram Schmidt field programmable gate array

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An accelerator for physics simulations

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COMPUTING IN SCIENCE & ENGINEERING 2007年第5期9卷 16-25页

作者： Danese, Giovanni Leporati, Francesco Bera, Marco Giachero, Mauro Nazzicari, Nelson Spelgatti, Alvaro Univ Pavia Fac Engn Pavia Italy

An accelerator based on field-programmable gate array (FPGA) technology accelerates double-precision floating-point operations present in the energy calculation of Monte Carlo-Metropolis simulations. The accelerator uses COTS components and is scalable in terms of clock frequency, memory capability, and number of computing units. It could also be part of a cluster of accelerated workstations.

关键词： Digital Simulation field programmable gate arrays Floating Point Arithmetic Monte Carlo Methods Physics Computing Workstation Clusters Accelerator Physics Simulations field programmable gate array Floating Point Operations Energy Calculation Monte Carlo Metropolis Simulations Clock Frequency Memory Capability Workstation Cluster COTS Computational Modeling field programmable gate arrays Computer Simulation Clocks Workstations Physics Computing Application Software Acceleration Hardware Circuit Simulation gate arrays Instruction Set Design Parallel Processors Monte Carlo Dynamics

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Low area FPGA implementation of modified histogram estimation architecture with CSAC-DPROM-OBC for medical image enhancement application

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INTERNATIONAL JOURNAL OF NANOTECHNOLOGY 2023年第1-4期20卷 259-280页

作者： Bonagiri, Koteswar Rao Kande, Giri Babu Reddy, P. Chandrasekhar Jawaharlal Nehru Technol Univ Dept Elect & Commun Engn Hyderabad 500085 India Marrilaxman Reddy Inst Technol & Management Domara Pocham Pally 500043 Telangana India Vasireddy Venkatadri Inst Technol Dept Elect & Commun Engn Namburu 522508 Andhrapradesh India

In this work, modified histogram estimation (MHE) architecture is proposed to verify the histogram count in the FPGA platform, and the Basic HE (BHE) architecture is also implemented for comparative purpose. The entire proposed MHE architecture is developed newly so as to reduce the logical elements involved in the HE process. In MHE architecture, dual port read only memory (DPROM), carry select adder based counter (CSAC), and Optimal Bin Counter (OBC) are used to evaluate the HE count with effective accuracy. The amount of percentage reduced by the 256 sample MHE is 17.62%, 15.41% and 23.01% for area, power and delay respectively. Additionally, the performance of the proposed MHE is compared with four existing methods HOG, HBS, MBPA and DMH. The number of flip flops utilised by the MHE architecture is 2177 for Vertex 6 device, which is less compared to the HOG and MBPA.

关键词： area basic histogram estimation CSAC carry select adder based counter delay DPROM dual port read only memory field programmable gate array medical image enhancement MHE modified histogram estimation optimal bin counter power

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Janus: An FPGA-Based System for High-Performance Scientific Computing

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COMPUTING IN SCIENCE & ENGINEERING 2009年第1期11卷 48-58页

作者： Belletti, F. Guidetti, M. Maiorano, A. Mantovani, F. Schifano, S. F. Tripiccione, R. Cotallo, M. Perez-Gaviro, S. Sciretti, D. Velasco, J. L. Cruz, A. Navarro, D. Tarancon, A. Fernandez, L. A. Martin-Mayor, V. Munoz-Sudupe, A. Yllanes, D. Gordillo-Guerrero, A. Ruiz-Lorenzo, J. J. Marinari, E. Parisi, G. Rossi, M. Zanier, G. Univ Ferrara Dept Phys I-44100 Ferrara Italy Univ Zaragoza Elect & Commun Dept E-50009 Zaragoza Spain Univ Complutense Madrid E-28040 Madrid Spain Univ Extremadura E-06071 Badajoz Spain Univ Roma La Sapienza Rome Italy

Janus is a modular, massively parallel, and reconfigurable FPGA-based computing system that's tailored to a class of hard scientific applications. Monte Carlo statistical mechanics simulations provide a good examp... 详细信息

关键词： field programmable gate arrays Mathematics Computing Monte Carlo Methods Scientific Information Systems Statistical Mechanics Ubiquitous Computing Janus FPGA Based System High Performance Scientific Computing Megabits Database Monte Carlo Simulations Statistical Mechanics Scientific Computing Computational Modeling Lattices Monte Carlo Methods Parallel Processing Physics Computing Computer Simulation Pervasive Computing Biology Computing Application Software Nobel Prize Monte Carlo Simulations field programmable gate array FPGA Scientific Computing Janus

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Resource efficient LDPC decoders for multimedia communication

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INTEGRATION-THE VLSI JOURNAL 2015年第1期48卷 213-220页

作者： Chandrasetty, Vikram Arkalgud Aziz, Syed Mahfuzul Univ S Australia Sch Engn Mawson Lakes SA 5095 Australia

Achieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors introduced by the communication channel. This paper presents an innovative flexible architecture for error correction using Low-Density Parity-Check (LDPC) codes. The proposed partially-parallel decoder architecture utilizes a novel code construction technique based on multi-level Hierarchical Quasi-Cyclic (HQC) matrix. The proposed architecture is resource efficient, provides scalable throughput and requires substantially less power compared to other decoders reported to date. The proposed decoder has been implemented on a Xilinx FPGA suitable for WiMAX application and achieves a throughput of 548 Mbps. Performance evaluation of the decoder has been carried out by transmitting JPEG images over a wireless noisy channel and comparing the quality of the reconstructed images with those from other similar decoders. (C) 2014 Elsevier B.V. All rights reserved.

关键词： Image communication Error correction codes Cyclic codes Codecs field programmable gate array

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Speed optimal FPGA implementation of the encryption algorithms for telecom applications

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MICROPROCESSORS AND MICROSYSTEMS 2020年 79卷 103324-103324页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Dept EEE Pilani Rajasthan India Birla Inst Technol & Sci Dept EEE Vidya Vihar Campus Pilani Rajasthan India

The last two decades have seen a revolution in telecom technology with the evolution of three wireless mobile communication standards, namely, GPRS to 3G, 3G to 4G, and 4G to 5G. 5G offers faster download speeds and enables high connectivity between devices such as mobile phones, displays, smart homes, and smart cars because of its high reliability and high bandwidths (up to 10 Gbps). However, at the same time, data and personal information are also more susceptible to theft because of the high connectivity. Such threats can be addressed using electronic data encryption using the advanced encryption standard (AES). Because of their reconfigurable and parallel architectures, field-programmable gate arrays (FPGAs) are getting popular in VLSI design flows to enable the pre-silicon validation of designs faster data rates in real-time. FPGAs also serve as platforms for software development in the pre-silicon environment owing to their faster speeds. The design community is also heavily relying on High-Level Synthesis (HLS) tools in VLSI design flows. HLS platforms enable the new designs to improve the process with sustained authentication between two analytical selections from conventional functional specifications. We propose a high-throughput FPGA implementation based on high-level Synthesis for the AES algorithm. The implementation uses a 128-bit key and is highly suited for telecom applications such as 5G. Researchers have developed and tested the setup and then used the Vivado HLS tool to evaluate various HLS guidelines as per the implementation. The generated Verilog RTL was verified and implemented on Xilinx Kintex 7 and Virtex 6 FPGAs. Since using the same resources, we have seen significant results than existing methods achieved by individual investigators. We have also verified the design for functionality by checking the ciphertext output from our design against a reference design output for the same input plaintext.

关键词： Advanced encryption standard field programmable gate array Register transfer level Telecom Xilinx high-level synthesis

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Fuzzy Logic Control for Solar PV Fed Modular Multilevel Inverter Towards Marine Water Pumping Applications

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IEEE ACCESS 2021年 9卷 88524-88534页

作者： Stonier, Albert Alexander Murugesan, Srinivasan Samikannu, Ravi Krishnamoorthy, Vinoth Subburaj, Senthil Kumar Chinnaraj, Gnanavel Mani, Geetha Kongu Engn Coll Dept Elect & Elect Engn Erode 638060 India Botswana Int Univ Sci & Technol Dept Elect Comp & Telecommun Engn Palapye Botswana Vel Tech Rangarajan Dr Sagunthala Res & Dev Inst Dept Elect & Elect Engn Chennai 600062 Tamil Nadu India New Prince Shri Bhavani Coll Engn & Technol Dept Elect & Elect Engn Chennai 600073 Tamil Nadu India AMET Deemed Univ Dept Elect & Elect Engn Chennai 603112 Tamil Nadu India Vellore Inst Technol Sch Elect Engn Vellore 632014 Tamil Nadu India

This paper presents the design and implementation of Modular Multilevel Inverter (MMI) to control the Induction Motor (IM) drive using intelligent techniques towards marine water pumping applications. The proposed inverter is of eleven levels and has the ability to control the speed of an IM drive which is fed from solar photovoltaics. It is estimated that the energy consumed by pumping schemes in an onboard ship is nearly 50% of the total energy. Considering this fact, this paper investigates and validates the proposed control design with reduced complexity intended for marine water pumping system employing an induction motor (IM) drive and MMI. The analysis of inverter is carried out with Proportional-Integral (PI) and Fuzzy Logic (FL) based controllers for improving the performance. A comparative analysis has been made with respect to better robustness in terms of peak overshoot, settling time of the controller and Total Harmonic Distortion (THD) of the inverter. Simulations are undertaken in MATLAB/Simulink and the detailed experimental implementation is conducted with field programmable gate array (FPGA). The results thus obtained are utilized to analyze the controller performance, improved inverter output voltage, reliable induction motor speed control and power quality improvement by reduction of harmonics. The novelty of the proposed control scheme is the design and integration of MMI, IM drive and intelligent controller exclusively for marine water pumping applications.

关键词： Marine vehicles Induction motors Multilevel inverters Power quality field programmable gate arrays Velocity control Topology field programmable gate array fuzzy logic controller induction motor drive modular multilevel inverter proportional-integral total harmonic distortion

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