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Implementation of a field programmable gate array based transcranial Doppler ultrasound system using pulse compression techniques

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BIOMEDICAL SIGNAL PROCESSING AND CONTROL 2007年第1期2卷 51-58页

作者： Gittins, John Cowe, Joanne Evans, David H. Univ Hosp Leicester Dept Med Phys Leicester LE1 5WW Leics England Univ Leicester Dept Cardiovasc Sci Leicester Leics England

A field programmable gate array (FPGA) based hardware platform that is used to implement a digital, multi-gate pulsed Doppler ultrasound system for transcranial Doppler (TCD) use is described. The Doppler audio signal is extracted from the digitised radio-frequency signal by matched filtering and suitable sampling. The system was configured to acquire Doppler signals from 16 depth locations and to display Doppler signal power versus depth as well as a sonogram from a user specified depth. The signal-to-noise performance of the system was comparable with that of a commercially available TCD unit for equivalent pulse repetition frequency and sample volume settings. The flexibility of the platform was used to demonstrate the feasibility of using coded transducer excitation and pulse compression techniques to improve axial resolution compared to a non-coded implementation. The axial resolution improvement was demonstrated using a flow phantom and measured using a vibrating wire phantom. The measured resolutions were 9.1 and 2.4 mm for the conventional and coded implementations, respectively. The reduction in signal-to-noise ratio of approximately 5 dB associated with the configuration using coded excitation was attributable to the frequency response characteristics of the transducer rather than the processing/technique used. This work demonstrates both the flexibility associated with an FPGA implementation of a Doppler ultrasound system and the potential for coded excitation to improve axial resolution in TCD systems. (c) 2007 Elsevier Ltd. All rights reserved.

关键词： Coded excitation Chirp TCD Axial resolution field programmable gate array

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RISC32-E: field programmable gate array based sensor node with queue system to support fast encryption in Industrial Internet of Things applications

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2020年第8期48卷 1209-1226页

作者： See, Jin-Chuan Mok, Kai-Ming Lee, Wai-Kong Goh, Hock-Guan Univ Tunku Abdul Rahman Fac Informat & Commun Technol Perak Malaysia

Industrial Internet of Things (IIoT) is an emerging technology that relies on the use of massively connected sensor nodes to gather industrial-related data. The collected data are used for postanalysis to generate insights for reducing production down time, cost optimization, and predictive maintenance. One of the key requirements for sensor node in such application is the data confidentiality;as such sensor data may potentially leak the manufacturing and industrial secret to their competitors. In this paper, a field programmable gate array (FPGA)-based sensor node with Advanced Encryption Standard (AES) crypto-processor is proposed to safeguard the sensor data. A novel queue system is proposed to further reduce the data processing time and energy consumption. The proposed queue system is able to achieve 1.48x speed up and similar to 16% energy reduction, which makes it a competitive candidate for Industrial IoT applications. The technique developed in this paper can also be extended to implement FPGA-based gateway with encryption feature, which is very useful for edge computing in IoT applications.

关键词： data acquisition field programmable gate array Industrial Internet of Things security coprocessor sensor node toolchain

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Implementation of a field programmable gate array-based lock-in amplifier

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MEASUREMENT 2015年 69卷 31-41页

作者： Cifuentes, A. Marin, E. Inst Politecn Nacl Ctr Invest Ciencia Aplicada & Tecnol Avanzada Unidad Legaria Mexico City 11500 DF Mexico

A Lock-In Amplifier (LIA), or phase sensitive detector, is an instrument capable of providing high frequency selectivity allowing the user to distinguish a signal of interest from background noise, and has become an important component in the instrumentation for the study of many different physical phenomena. In this work a LIA is implemented using digital signal processing techniques on a field programmable gate array, or FPGA, and is compared against a commercial counterpart with the objective of showing that homebrewed instruments can produce reliable and trustworthy results. For this comparison experimental tests have been performed which are based on the photoacoustic effect, given that LIAs are cornerstones of many techniques based in this and other related effects. (C) 2015 Elsevier Ltd. All rights reserved.

关键词： Lock-in amplifier field programmable gate array Photoacoustic effect

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Effective Suppression of Conducted Electro Magnetic Interference in DC-DC Boost Converter Using field programmable gate array Based Chaotic Pulse Width Modulation Switching

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ELECTRIC POWER COMPONENTS AND SYSTEMS 2014年第5期42卷 471-480页

作者： Natarajan, Sudhakar Natarajan, Rajasekar VIT Univ Sch Elect Engn Vellore 632014 Tamil Nadu India

Abstract-In recent years, electro-magnetic interference on DC-DC converters is seen as serious problem as it limits the capability of the DC-DC converter. It is popular to use analog circuits to suppress electro-magnetic interference;however, a cheap analog circuit suffers from numerous drawbacks, including inaccurate pulse generation, carrier frequency limitation, and degraded performance due to aging. Conversely, high-performance digital circuits are capable of providing accurate pulses compared to analog circuits. In this article, a field-programmable gate array is used to generate accurate chaotic pulse-width modulation pulses for DC-DC converters. A spread spectrum technique based on randomized carrier frequency modulation with fixed duty ratio is proposed for gating pulse generation, implemented using a field-programmable gate array for electro-magnetic interference suppression. A hardware prototype is built in the laboratory for the proposed method and tested. The performance of the proposed method estimated through simulation study is validated via experimental results.

关键词： DC-DC converter randomized carrier frequency modulation with fixed duty ratio electro-magnetic interference chaotic pulse-width modulation field programmable gate array

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Real-time optical character recognition on field programmable gate array for automatic number plate recognition system

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IET CIRCUITS DEVICES & SYSTEMS 2013年第6期7卷 337-344页

作者： Zhai, Xiaojun Bensaali, Faycal Sotudeh, Reza Univ Hertfordshire Sch Engn & Technol Hatfield AL10 9AB Herts England Qatar Univ Coll Engn Dept Elect Engn Doha Qatar Univ Essex Sch Comp Sci & Elect Engn Colchester CO4 3SQ Essex England

The last main stage in an automatic number plate recognition system (ANPRs) is optical character recognition (OCR), where the number plate characters on the number plate image are converted into encoded texts. In this study, an artificial neural network-based OCR algorithm for ANPR application and its efficient architecture are presented. The proposed architecture has been successfully implemented and tested using the Mentor Graphics RC240 field programmable gate arrays (FPGA) development board equipped with a 4M gates Xilinx Virtex-4 LX40. A database of 3570 UK binary character images have been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can meet the real-time requirement of an ANPR system and can process a character image in 0.7 ms with 97.3% successful character recognition rate and consumes only 23% of the available area in the used FPGA.

关键词： field programmable gate arrays neural nets optical character recognition time 0 7 ms UK binary character images 4M gates Xilinx Virtex-4 LX40 Mentor Graphics RC240 FPGA development board ANPR application artificial neural network-based OCR algorithm number plate image number plate characters automatic number plate recognition system field programmable gate array real-time optical character recognition

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A field programmable gate array-based biomedical noise reduction framework using advanced trilateral filter

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TRANSACTIONS OF THE INSTITUTE OF MEASUREMENT AND CONTROL 2021年第16期43卷 3588-3605页

作者： Raja, M. Ramkumar Naveen, R. Palaniswamy, Thangam Mahendiran, T., V Shukla, Neeraj Kumar Verma, Rajesh King Khalid Univ Dept Elect Engn Abha 62529 Saudi Arabia Ashoka Womens Engn Coll Dupadu India King Abdulaziz Univ Fac Engn Dept Elect & Comp Engn Jeddah Saudi Arabia

Filtering is one of the essential tools utilized to remove undesirable features in biomedical images. Most biomedical image denoising systems are used for clinical diagnosis. So, in this paper, we use the advanced trilateral filter in the field programmable gate array (FPGA) for removing noise in the biomedical image. Generally, the trilateral filter is used as an edge preserving smoothing filter. This advanced approach of trilateral filter gives the best noise diminution and enhances the image quality. This paper also proposes the hardware implementation of an efficient FPGA-based advanced trilateral filter on real time execution. In this manuscript, we intend to design and implement the FPGA architecture using an advanced trilateral filter. Biomedical images with different noises are used during implementation and compared with the existing bilateral and trilateral architecture to assess the proposed architecture performance. For evaluating the performance metrics of the proposed advanced trilateral filter on MATLAB platform, peak signal-to-noise ratio (PSNR), mean squared error (MSE) and structured similarity index (SSIM) are calculated for different biomedical images - such as brain (MRI), chest (x-ray) and lungs (CT) - with different noises - such as salt and pepper, Gaussian, Poisson and Speckle noises - compared with existing bilateral filter and trilateral filter, respectively. The proposed advanced trilateral filter implementations are checked on Virtex-6, Virtex-7 and Zynq FPGA development board using Verilog programming language in Xilinx ISE 14.5 design tools. The simulation outcomes display that the FPGA execution of the advanced trilateral filter contains better noise removal efficiency in biomedical images compared with the existing bilateral and trilateral filter.

关键词： field programmable gate array advanced trilateral filter Verilog Xilinx noise MATLAB peak signal-to-noise ratio (PSNR) mean squared error (MSE) and structured similarity index (SSIM)

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High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion

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IET COMPUTERS AND DIGITAL TECHNIQUES 2015年第3期9卷 175-184页

作者： Liu, Qiang Xu, Zhenyu Yuan, Ye Tianjin Univ Sch Elect Informat Engn Tianjin 30072 Peoples R China

Aiming at protection of high speed data, field programmable gate array (FPGA)-based advanced encryption standard (AES) design is proposed here. Deep investigation into the logical operations of AES with regard to FPGA architectures leads to two efficient pipelining structures for the AES hardware implementation. The two design options allow users to make a trade-off among speed, resource usage and power consumption. In addition, a new key expansion scheme is proposed to address the potential issues of existing key expansion scheme used in AES. The proposed key expansion scheme with additional non-linear operations increases the complexity of cracking keys by up to 2((N - 1)) times for N-round AES. The proposed design is evaluated on various FPGA devices and is compared with several existing AES implementations. In terms of both throughput and throughput per slice, the proposed design can overcome most existing designs and achieves a throughput of 75.9 Gbps on a latest FPGA device. Two parallel implementations of the proposed design can meet the real-time encryption/decryption demand for 100 Gbps data rate. Furthermore, the proposed AES design is implemented on the Zynq xc7z020 FPGA platform, demonstrating its application to image encryption.

关键词： cryptography field programmable gate arrays logic design data protection secure advanced encryption standard high throughput advanced encryption standard field programmable gate array enhanced key expansion scheme high speed data protection AES design FPGA architectures pipelining structures power consumption nonlinear operations N-round AES real-time encryption-decryption demand Zynq xc7z020 FPGA platform image encryption bit rate 75.9 Gbit/s bit rate 100 Gbit/s

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Development and experimental validation of a field programmable gate array-based in-cycle direct water injection control strategy for homogeneous charge compression ignition combustion stability

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INTERNATIONAL JOURNAL OF ENGINE RESEARCH 2019年第10期20卷 1101-1113页

作者： Gordon, David Wouters, Christian Wick, Maximilian Lehrheuer, Bastian Andert, Jakob Koch, Charles Pischinger, Stefan Univ Alberta Dept Mech Engn Edmonton AB T6G 2R3 Canada Rhein Westfal TH Aachen Inst Combust Engines Aachen Germany Rhein Westfal TH Aachen Mechatron Syst Combust Engines Aachen Germany

Homogeneous charge compression ignition is a part-load combustion method, which can significantly reduce oxides of nitrogen (NOx) emissions compared to current lean-burn spark ignition engines. The challenge with homogeneous charge compression ignition combustion is the high cyclic variation due to the lack of direct ignition control. A fully variable electromagnetic valve train provides the internal exhaust gas recirculation through negative valve overlap which is required to obtain the necessary thermal energy to enable homogeneous charge compression ignition. This also increases the cyclic coupling as residual gas and unburnt fuel is transferred between cycles through exhaust gas recirculation. To improve combustion stability, an experimentally validated feed-forward water injection controller is presented. Utilizing the low latency and rapid calculation rate of a field programmable gate array, a real-time calculation of residual fuel mass is implemented on a prototyping engine controller. Using this field programmable gate array-based calculation, it is possible to calculate the amount of fuel and the required control interaction during an engine cycle. This controller prevents early rapid combustion following a late combustion cycle using direct water injection to cool the cylinder charge and counter the additional thermal energy from any residual fuel that is transferred between cycles. By cooling the trapped cylinder mass, the upcoming combustion phasing can be delayed to the desired setpoint. The controller was tested at several operating points and showed an improvement in the combustion stability as shown by a reduction in the standard deviation of combustion phasing and indicated mean effective pressure.

关键词： Homogeneous charge compression ignition gasoline-controlled autoignition in-cycle control direct water injection field programmable gate array real-time modeling

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160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA)

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BMC BIOINFORMATICS 2007年第1期8卷 1-7页

作者： Li, Isaac T. S. Shum, Warren Truong, Kevin Univ Toronto Inst Biomat & Biomed Engn Toronto ON M5S 3G9 Canada Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

Background: To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching sequence databases that may contain hundreds of millions of sequences, this algorithm becomes computationally expensive. Results: In this paper, we focused on accelerating the Smith-Waterman algorithm by using FPGA-based hardware that implemented a module for computing the score of a single cell of the SW matrix. Then using a grid of this module, the entire SW matrix was computed at the speed of field propagation through the FPGA circuit. These modifications dramatically accelerated the algorithm's computation time by up to 160 folds compared to a pure software implementation running on the same FPGA with an Altera Nios II softprocessor. Conclusion: This design of FPGA accelerated hardware offers a new promising direction to seeking computation improvement of genomic database searching.

关键词： field programmable gate array Logic Element Custom Instruction Static Random Access Memory Hardware Description Language

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Optimum control of total harmonic distortion in field programmable gate array-based cascaded multilevel inverter

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JOURNAL OF VIBRATION AND CONTROL 2015年第10期21卷 1999-2005页

作者： Maruthupandi, Perumal Devarajan, Nunjundappan Sebasthirani, Kathalingam Jose, Jordy K. Govt Coll Technol Dept Elect & Elect Engn Coimbatore 641013 Tamil Nadu India Sri Ramakrishna Engn Coll Dept Elect & Elect Engn Coimbatore Tamil Nadu India

Nowadays high quality power is essential for medical, research and industrial applications to produce good quality results and analysis. In this work an attempt has been made to improve the power quality by minimizing the harmonic content in the output voltage of a cascaded multilevel inverter using the selective harmonic elimination pulse width modulation technique. Sinusoidal PWM technique is used to generate the switching signals. A single phase nine-level cascaded multilevel inverter with identical DC supply is designed to reduce the harmonic components of the output voltage. Particle swarm optimization technique is applied to determine the optimum switching angles, thereby reducing some higher-order harmonics while maintaining the required fundamental voltage. This generalized technique can be extended to multilevel inverters with any number of levels. The total harmonic distortion is measured accordingly for different modulation indices. A prototype model of a field programmable gate array-based nine-level inverter has been designed, fabricated and tested. The results are presented and analyzed and hence the hardware results are verified with the simulation results.

关键词： field programmable gate array multilevel inverter particle swam optimization selective harmonic elimination total harmonic distortion

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