检索结果-内蒙古大学图书馆

19th IEEE International Symposium on Parallel and Distributed Processing with Applications (IEEE ISPA)

作者： Wang, Jinyu Kang, Yifei Li, Yiwen Wu, Weiguo Liu, Song Wang, Longxiang Xi An Jiao Tong Univ Sch Comp Sci & Technol Xian Peoples R China

ISBN: (纸本)9781665435741

Nowadays, multiple field programmable gate arrays (FPGAs) accelerators have been widely used in stencil computation fields. However, the state-of-the-art hexagonal tiling algorithm that efficiently improves stencil computation performance is mainly designed for CPUs or GPUs, which not suitable to directly process on FPGAs, leading to lower performance. To address this, a hexagonal tiling based multiple FPGAs stencil computation architecture and the corresponding optimization algorithm are proposed in this paper. The architecture uses the on-chip registers to store and carry cells data of a hexagonal tile. In this way, the scale and size of tiles are dramatically increased as well as the intra-FPGA calculation performance. Then, to take full advantage of multiple FPGAs processing ability, a memory shared inter-FPGAs high speed data transfer structure is devised. Finally, the Mixed-Integer Linear Programming (MILP) is used to optimize an objective function which considers the candidate FPGAs costs, computation latency and resources utilization to obtain a desirable tile size and layout result. The proposed method has been validated on the FPGA cluster which consists of two Xilinx Alveo U50 and one Alveo U250 devices. And experimental results show that we achieve performance up to 580 Gflop/s using one U50 device and 2261 Gflop/s using three FPGAs. The proposed optimizer is also tested with state-of-the-art multiple FPGAs stencil computation acceleration method and the performance is increased by 21.8% at most and 20.04% on average.

关键词： hexagonal tiling stencil computation field programmable gate array multiple FPGAs acceleration

来源：评论

学校读者我要写书评

暂无评论

CPU Parallelization and GPU Acceleration of SUAVE: Advancements in Sampling and Optimization

CPU Parallelization and GPU Acceleration of SUAVE: Advanceme...

引用

AIAA Science and Technology Forum and Exposition (AIAA SciTech Forum)

作者： Smart, Jordan T. Alonso, Juan J. Stanford Univ Dept Aeronaut & Astronaut Stanford CA 94305 USA

ISBN: (数字)9781624106095

ISBN: (纸本)9781624106095

This investigation examines the application of two strategies for reducing computation time required by the aircraft design suite SUAVE - CPU parallelization and GPU accereration. Results are shown for the application of between 1 and 24 simultaneous, asynchronous computations and JIT compilation of code for GPU execution via a JAX-XLA-CUDA stack. CPU parallelization is shown to degrade performance, and GPU acceleration to improve it by five orders of magnitude.

关键词： Graphics Processing Unit Aircraft Design Python Scientific Computing Vortex Strength Computational Fluid Dynamics Finite Element Analysis Supersonic Flight field programmable gate array Available Computing Resources

来源：评论

学校读者我要写书评

暂无评论

Motor-Imagery EEGNet-Based Processing on a Low-Spec SoC Hardware 20

Motor-Imagery EEGNet-Based Processing on a Low-Spec SoC Hard...

引用

20th IEEE Sensors Conference

作者： Caren Hernandez-Ruiz, Ana Eneriz, Daniel Medrano, Nicolas Calvo, Belen Univ Zaragoza Fac Sci Zaragoza 50009 Spain

ISBN: (纸本)9781728195018

One of the most popular Brain-Computer Interface (BCI) paradigms is the classification of motor imagery tasks using Electroencephalograph signals (EEG). Recent works suggest the use of Convolutional Neural Networks (CNNs) to both extract the EEG features and classify them in a single compact solution. Since BCIs are meant to be run in embedded hardware, compact models and data reduction strategies are necessary. An EEGNet-based model is presented in this work, which achieves results similar to those of the state-of-the-art of 83.15 %, 75.74 % and 65.75 % in classification accuracy on 2-, 3-, and 4-class MI tasks in global validation on the Physionet Motor Movement/Imagery dataset. Taking advantage of its lower model complexity, a preliminary FPGA processor design using fixed-point datatypes is introduced, to evaluate resources consumption and latency on a low-spec system on chip approach.

关键词： Brain Computer Interface EEG Convolutional Neural Network EEGNet field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

High Power-Efficient and Performance-Density FPGA Accelerator for CNN-Based Object Detection 4th

High Power-Efficient and Performance-Density FPGA Accelerato...

引用

4th Chinese Conference on Pattern Recognition and Computer Vision (PRCV)

作者： Zhang, Gang Zhang, Chaofan Wang, Fan Tang, Fulin Wu, Yihong Yang, Xuezhi Liu, Yong Hefei Univ Technol Hefei Anhui Peoples R China Chinese Acad Sci Hefei Inst Phys Sci Anhui Inst Opt & Fine Mech Hefei Anhui Peoples R China Univ Sci & Technol China Hefei Anhui Peoples R China Chinese Acad Sci Inst Automat Natl Lab Pattern Recognit Beijing Peoples R China

ISBN: (纸本)9783030880040;9783030880033

The field programmable gate array (FPGA) accelerator for CNN-based object detection has been attracting widespread attention in computer vision. For most existing FPGA accelerators, the inference accuracy and speed are affected negatively by the low power-efficient and performance-density. To address this problem, we propose a software and hardware co-designed FPGA accelerator for accurate and fast object detection with high power-efficient and performance-density. To develop the FPGA accelerator on CPU+FPGA heterogeneous platforms, a resource sensitive and energy aware FPGA accelerator framework is designed. In hardware, a hardware sensitive neural network quantization called Dynamic Fixed-point Data Quantization (DFDQ) is proposed to improve the power-efficient. In software, an algorithm-level convolution (CONV) optimization scheme is further proposed to improve the performance-density by paralleling block execution of CONV cores. To validate the proposed FPGA accelerator, a Zynq FPGA is used to build the acceleration platform of You Only Look Once (YOLO) network. Results demonstrate that the proposed FPGA accelerator outperforms the state-of-the-art methods in power-efficient and performance-density. Besides, the speed of object detection is increased by at most 16.5 times along with less than 1.5% accuracy degradation.

关键词： Object detection field programmable gate array Convolution optimization Dynamic Fixed-Point Data Quantization

来源：评论

学校读者我要写书评

暂无评论

Implementation of ANN Training Module on field programmable gate arrays

Implementation of ANN Training Module on Field Programmable ...

引用

Innovations in Intelligent Systems and Applications Conference (ASYU)

作者： Sarvan, Cagla Gunduzalp, Mustafa Yasar Univ Dept Elect & Elect Engn Izmir Turkey

ISBN: (纸本)9781728128689

This study provides an application-specific integrated circuit (ASIC) diagram of Artificial Neural Networks (ANN) with module design for 32-bit floating point operations on field programmable gate array (FPGA). It is aimed that ANNs train operations are moved from software to hardware and calculations are made by using IEEE 754 single precision floating point number format. The proposed architecture is designed with combination of Verilog and Very High Speed Integrated Circuits Hardware Description Language (VHDL). Sigmoidal non-linear function was used as the activation function of the train and look-up table (LUT) was created for process efficiency of the designed circuit. Natural parallelisms were used in the calculation of the operations, which are implemented on FPGA, thus the system operations was accelerated by performing independent operations during the same clock cycle. The results obtained from FPGA were compared with the results obtained from MATLAB R2016b.

关键词： field programmable gate array ANN VHDL Verilog single precision floating point

来源：评论

学校读者我要写书评

暂无评论

Design of digital controlled power conditioning unit for piezoelectric energy harvesting scheme

引用

International Journal of Electronics Letters 2024年第2期12卷 131-143页

作者： Samal, Nilimamayee Prasad, Sheetla School of Electrical Electronics and Communication Galgotias University Uttar Pradesh Greater Noida India

This paper provides design framework of digital controller design for power conditioning unit comprising rectifier and boost converter for piezoelectric energy harvesting system. Complete design of digitally controlled boost converter interfaced with piezoelectric energy harvester has been carried out in this work. Simulation results validate the different theoretical aspects of design. field programmable gate array (FPGA) based hardware implementation of digital controller has been illustrated. © 2023 Informa UK Limited, trading as Taylor & Francis Group.

关键词： digital controller Energy harvesting field programmable gate array piezoelectric power conditioning unit

来源：评论

学校读者我要写书评

暂无评论

Giga-sample Pulse Acquisition and Digital Processing for Photomultiplier Detectors

引用

JOURNAL OF FUSION ENERGY 2022年第1期41卷 8-8页

作者： Walewski, W. Nowakowski, P. Nowak Vel Makowski, D. Lodz Univ Technol Dept Microelect & Comp Sci Lodz Poland

Digital Pulse Processing offers multiple advantages over traditional analogue processing chains. As a disadvantage, produce gigabytes of data every second. Storing and processing such data rates in real-time still remains a challenge. Analogue solutions are not riddled with this issue, however, they offer limited flexibility and modifiability. This work highlights the advantages of Digital Pulse Processing over Analogue Pulse Processing and describes a successful implementation of a digital pulse detection and acquisition system based on field programmable gate arrays. The system is tasked with processing pulses generated by a Photo Multiplier Tube nuclear detector. Incoming signals are sampled at a 1 GS/s rate, so to enable full acquisition resolution, throughput is reduced with digital detection filters and leading-edge triggering or with a derivative zero-crossing detector. Three different fast timing filters are adapted to high-speed real-time acquisition and compared in a simulated scenario. A trapezoidal filter is implemented in firmware alongside the detection channel for pulse height analysis. Thanks to the use of reprogrammable devices, the system remains versatile and can be remotely adapted to different needs with no additional hardware costs.

关键词： Digital pulse processing field programmable gate array Data acquisition Data processing Pulse height analysis Energy resolution

来源：评论

学校读者我要写书评

暂无评论

A high-performance, hardware-based deep learning system for disease diagnosis

引用

PEERJ COMPUTER SCIENCE 2022年 8卷 e1034页

作者： Siddique, Ali Iqbal, Muhammad Azhar Aleem, Muhammad Lin, Jerry Chun-Wei Natl Univ Comp & Emerging Sci Lahore Campus Lahore Pakistan Univ Macau Taipa Macau Peoples R China Univ Lancaster Lancaster England Natl Univ Comp & Emerging Sci Islamabad Pakistan Western Norway Univ Appl Sci Bergen Norway

Modern deep learning schemes have shown human-level performance in the area of medical science. However, the implementation of deep learning algorithms on dedicated hardware remains a challenging task because modern algorithms and neuronal activation functions are generally not hardware-friendly and require a lot of resources. Recently, researchers have come up with some hardware-friendly activation functions that can yield high throughput and high accuracy at the same time. In this context, we propose a hardware-based neural network that can predict the presence of cancer in humans with 98.23% accuracy. This is done by making use of cost-efficient, highly accurate activation functions, Sqish and LogSQNL. Due to its inherently parallel components, the system can classify a given sample in just one clock cycle, i.e., 15.75 nanoseconds. Though this system is dedicated to cancer diagnosis, it can predict the presence of many other diseases such as those of the heart. This is because the system is reconfigurable and can be programmed to classify any sample into one of two classes. The proposed hardware system requires about 983 slice registers, 2,655 slice lookup tables, and only 1.1 kilobits of on-chip memory. The system can predict about 63.5 million cancer samples in a second and can perform about 20 giga-operations per second. The proposed system is about 5-16 times cheaper and at least four times speedier than other dedicated hardware systems using neural networks for classification tasks.

关键词： Activation function Cancer diagnosis Deep learning field programmable gate array Hardware friendly Neural networks Swish

来源：评论

学校读者我要写书评

暂无评论

FPGA-based real-time cloud detection camera for small satellites

FPGA-based real-time cloud detection camera for small satell...

引用

Conference on AOPC - Optical Sensing and Imaging Technology

作者： Chi, Gaojun Wang, Jiejun Shi, Jingjing Sun, Bin Wang, Xiangjing Hu, Yadong Guilin Univ Elect Technol Sch Elect Engn & Automat Guilin 541004 Peoples R China Univ Sci & Technol China Sch Environm Sci & Optoelect Technol Hefei 230026 Peoples R China Chinese Acad Sci Anhui Inst Opt & Fine Mech Hefei 230031 Peoples R China

ISBN: (纸本)9781510650060;9781510650053

Clouds play an important role in weather and climate-related investigations. However, they often influence the quality of images and waste resources of storage and bandwidth in remote sensing. So, it is critical to detect clouds for less cost of payload. In this paper, the design of a real-time cloud detection camera for small satellite platforms is proposed based on field programmable gate array (FPGA). Two MicroBlaze Soft Cores are embedded in the FPGA to accomplish the task without other chips assist. By using this way, the system is highly programmable and integrated, the weight of which also becomes lighter. We implemented the system on a Xilinx Virtex-4 FPGA. The test results show that the signal-to-noise ratio (SNR) is 128.1 at 80% of the saturated exposure. We select Arabian Peninsula-Pakistan-West India area to evaluate the cloud judgment accuracy. Compare with moderate resolution imaging spectroradiometer (MODIS) cloud mask products, the false alarm rate (FAR) is less than 3%. The application of the proposed approach in a simulation and engineering system indicates its effectiveness and practicability.

关键词： Cloud detection camera field programmable gate array MicroBlaze signal-to-noise false alarm rate

来源：评论

学校读者我要写书评

暂无评论

An FPGA-based Real-Time Simulation of a Hybrid Fuel Cell/Battery Source

An FPGA-based Real-Time Simulation of a Hybrid Fuel Cell/Bat...

引用

IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Meddah, Karim Ould-Bachir, Tarek Becherif, Mohamed Benmouna, Amel Polytech Montreal MOTCE Lab Dept Comp Engn Montreal PQ Canada Univ Bourgogne Franche Compte UTBM UMR CNRS 6174 FEMTO ST FCLab F-90010 Belfort France

ISBN: (纸本)9781665448642

This paper presents a new approach for the modeling and real-time simulation of an embedded hybrid power source comprised of a fuel cell (FC) and a battery. The proposed modeling is based on a state-space-like representation of the system equations obtained from the modified-augmented nodal analysis. Systematic formulation of system equations is presented and the solution to the non-linear equations are discussed. The proposed model was implemented on an entry level field programmable gate array (FPGA), and demonstrates sub-microsecond simulation time-step capability. The real-time solution is obtained by precomputing the system equations for all switch state combinations, and using the backward Euler integration scheme for solving differential equations. A fixed point number representation is utilized for speed and reduced configurable resource utilization. Our results show a high fidelity of the proposed model over a wide range of simulation time-steps and switching frequencies.

关键词： Fuel Cell Hardware-in-the-loop Simulation Rapid control prototyping field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：