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Development of main functional modules for MVB and its application in rail transit

APPLIED MATHEMATICS AND NONLINEAR SCIENCES 2022年第1期8卷 2117-2132页

作者： Yang, Changxiu Zheng, Yu Peng, Tiefeng Chongqing Vocat Coll Transportat Dept Rail Transit Chongqing Peoples R China Shenzhen Possibler Technol Co Ltd Shenzhen Peoples R China

In this work, multi-function vehicle bus (MVB) controller-based field programmable gate array (FPGA) and MVB manager based on the real-time multitasking operating system were explored and developed. The function of the MVB controller data link layer was realised by using FPGA. The embedded real-time multitasking operating system uCOS-II was applied to the development of MVB manager's processing data, device state management, message data and bus management function. The network consistency test was performed to validate data communication of MVB link layer control protocol and the management function of MVB manager;the equipment was shown to be compatible with each other and met the requirements of IEC61375-1.

关键词： MVB field programmable gate array rail transport protocol network

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A Pipelined Reduced Complexity Two-Stages Parallel LMS Structure for Adaptive Beamforming

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第12期67卷 5079-5091页

作者： Akkad, Ghattas Mansour, Ali ElHassan, Bachar A. Inaty, Elie Ayoubi, Rafic Srar, Jalal A. ENSTA Bretagne UMR 6285 Lab STICC F-29200 Brest France Lebanese Univ Fac Engn Tripoli Lebanon Univ Balamand Dept Comp Engn Koura Lebanon Misurata Univ Elect & Elect Dept Misratah Libya

In this paper, we propose a reduced complexity parallel least mean square structure (RC-pLMS) for adaptive beamforming and its pipelined hardware implementation. RC-pLMS is formed by two least mean square (LMS) stages operating in parallel (pLMS), where the overall error signal is derived as a combination of individual stage errors. The pLMS is further simplified to remove the second independent set of weights resulting in a reduced complexity pLMS (RC-pLMS) design. In order to obtain a pipelined hardware architecture of our proposed RC-pLMS algorithm, we applied the delay and sum relaxation technique (DRC-pLMS). Convergence, stability and quantization effect analysis are performed to determine the upper bound of the step size and assess the behavior of the system. Computer simulations demonstrate the outstanding performance of the proposed RC-pLMS in providing accelerated convergence and reduced error floor while preserving a LMS identical O(N) complexity, for an antenna array of N elements. Synthesis and implementation results show that the proposed design achieves a significant increase in the maximum operating frequency over other variants with minimal resource usage. Additionally, the resulting beam radiation pattern show that the finite precision DRC-pLMS implementation presents similar behavior of the infinite precision theoretical results.

关键词： Complexity theory Convergence Hardware array signal processing Computer architecture Adaptive arrays Delays LMS parallel LMS adaptive beamforming field programmable gate array sensor array

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The PreProcessor module for the ATLAS Tile Calorimeter at the HL-LHC

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2020年第0期958卷 162487-000页

作者： Carrio, F. Valero, A. UV CSIC Inst Fis Corpuscular C Catedratico Jose Beltran 2 Paterna 46980 Spain

The Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC). In 2026, the LHC will be upgraded to the High Luminosity LHC (HL-LHC) allowing it to deliver up to 7 times the nominal instantaneous design luminosity. The Phase-II TileCal Upgrade will accommodate the detector and data acquisition system to the HL-LHC requirements. The on- and off-detector electronics will be completely redesigned using a new readout architecture with a full-digital trigger system. The upgraded on-detector electronics will transfer digitized data for every bunch crossing (similar to 25 ns) to the Tile PreProcessor system in the counting rooms, requiring a total data bandwidth of 40 Tbps. The TilePPr will store the detector data in pipeline memories to meet the new ATLAS Trigger and Data Acquisition architecture requirements, and will interface with the FELIX system and the first level trigger system.

关键词： DAQ system High energy physics ATLAS CERN field programmable gate array ATCA

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Optimal fault resilient autonomous quadcopter control based on dynamic partial reconfigurable FPGA

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COGENT ENGINEERING 2023年第2期10卷

作者： Bhat, Harish Chokkadi, Shreesha Shenoy, Satish Manipal Inst Technol Manipal Acad Higher Educ Ctr Excellence Avion & Nav Dept Instrumentat & Control Engn Manipal India Manipal Inst Technol Manipal Acad Higher Educ Ctr Excellence Avion & Nav Dept Aeronaut & Automobile Engn Manipal India Manipal Inst Technol Manipal Acad Higher Educ Dept Instrumentat & Control Engn Manipal India Manipal Inst Technol Manipal Acad Higher Educ Dept Aeronaut & Automobile Engn Manipal India

Quadcopters are in enormous demand in mission-critical applications where there is a large risk to human life, such as border patrolling, emergency rescue, and production monitoring in chemical industries. Autonomously flying quadcopters can ensure higher levels of safety than remotely controlled quadcopters. Due to the complexity of autonomous quadcopters, there is a risk of failure, posing an enormous challenge to successful mission completion. Additionally, due to space constraints and the need for extended operation, the controller area and propulsion power are to be lower along with higher speeds of tracking for reaching the destination as early as possible. With these conflicting requirements, these metrics can be optimized in stages by reconfiguring the controllers on FPGA-based systems. Different controllers and suitable references are chosen and brought into action based on the metric that is lagging once they are found suitable to operate safely. This combination of control and reference reconfiguration and switching of main/auxiliary controllers is expected to ensure speed, area, and power optimization with improved fault resilience, ensuring better mission completion possibilities. This has been verified with Simulink-based algorithms of both continuous systems and fixed point-based digital systems and FPGA-based system co-simulation with the Simulink-based quadcopter model. Finally, the synthesis and implementation of the FPGA-based system is also taken up on Zynq Ultrascale +/- based devices with Vivado v2018.3-based IDE.

关键词： optimal control field programmable gate array dynamic partial reconfiguration fault resilient control autonomous control

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Embedded Bayesian Network Contribution for a Safe Mission Planning of Autonomous Vehicles

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ALGORITHMS 2020年第7期13卷 155页

作者： Dezan, Catherine Zermani, Sara Hireche, Chabha Univ Brest Lab Sci & Technol Informat Commun & Connaissance Natl Ctr Sci Res CNRS F-29200 Brest France Univ Guyane Espace Dev Espace Dev F-97300 Cayenne France

Bayesian Networks (BN) are probabilistic models that are commonly used for the diagnosis in numerous domains (medicine, finance, transport, robotics, horizontal ellipsis ). In the case of autonomous vehicles, they can contribute to elaborate intelligent monitors that can take the environmental context into account. We show in this paper some main abilities of BN that can help in the elaboration of fault detection isolation and recovery (FDIR) modules. One of the main difficulty with the BN model is generally to elaborate these ones according to the case of study. Then, we propose some automatic generation techniques from failure mode and effects analysis (FMEA)-like tables using the pattern design approach. Once defined, these modules have to operate online for autonomous vehicles. In a second part, we propose a design methodology to embed the real-time and non-intrusive implementations of the BN modules using FPGA-SoC support. We show that the FPGA implementation can offer an interesting speed-up with very limited energy cost. Lastly, we show how these BN modules can be incorporated into the decision-making model for the mission planning of unmanned aerial vehicles (UAVs). We illustrate the integration by means of two models: the Decision Network model that is a straightforward extension of the BN model, and the BFM model that is an extension of the Markov Decision Process (MDP) decision-making model incorporating a BN. We illustrate the different proposals with realistic examples and show that the hybrid implementation on FPGA-SoC can offer some benefits.

关键词： Bayesian networks fault detection isolation and recovery failure mode and effects analysis embedded diagnosis error mitigation unmanned aerial vehicles mission planning Markov Decision Process high level synthesis design tool field programmable gate array System-On-Chip

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Single Image Haze Removal from Image Enhancement Perspective for Real-Time Vision-Based Systems

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SENSORS 2020年第18期20卷 5170.-5170.页

作者： Dat Ngo Lee, Seungmin Quoc-Hieu Nguyen Tri Minh Ngo Lee, Gi-Dong Kang, Bongsoon Dong A Univ Dept Elect Engn Busan 49315 South Korea Univ Sci & Technol Univ Danang Fac Elect & Telecommun Engn Danang 550000 Vietnam

Vision-based systems operating outdoors are significantly affected by weather conditions, notably those related to atmospheric turbidity. Accordingly, haze removal algorithms, actively being researched over the last decade, have come into use as a pre-processing step. Although numerous approaches have existed previously, an efficient method coupled with fast implementation is still in great demand. This paper proposes a single image haze removal algorithm with a corresponding hardware implementation for facilitating real-time processing. Contrary to methods that invert the physical model describing the formation of hazy images, the proposed approach mainly exploits computationally efficient image processing techniques such as detail enhancement, multiple-exposure image fusion, and adaptive tone remapping. Therefore, it possesses low computational complexity while achieving good performance compared to other state-of-the-art methods. Moreover, the low computational cost also brings about a compact hardware implementation capable of handling high-quality videos at an acceptable rate, that is, greater than 25 frames per second, as verified with a field programmable gate array chip. The software source code and datasets are available online for public use.

关键词： haze removal real-time processing detail enhancement multiple-exposure image fusion adaptive tone remapping field programmable gate array

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An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor System

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ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING 2020年第8期45卷 6649-6660页

作者： Mariyappan, Isaivani Veluchamy, Malathi Ramachandradurai, Sowmya Anna Univ Reg Campus Madurai Madurai Tamil Nadu India SASTRA Deemed Be Univ Thanjavur Tamil Nadu India

In recent years, field programmable gate array (FPGA) has different, and novel combinations of soft and hard cores embedded with accelerators in the same chip. At present, "Heterogeneous Multiprocessor System-on-Chip" technology meets the needs of the FPGA architecture as it not only consumes less space but also its design is implemented to enhance the performance resulting in decreased power consumption. However, traditional approaches can work within a limited range of values incurring high-power consumption, and they need substantial hardware resources involving complex procedures. In our proposed work, the combination of Graph Theory Estimator and Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) is introduced. The principle notion of this proposed scheme is to optimize the required area resources and power consumption of the overall architecture by exploring the design space in a minimal time. The architecture uses a less number of hardware resources with a better outcome. The performances such as the latency, power consumption, delay, area and data rate are achieved better than the traditional works, and it is also application-aware with a multitask system. While comparing the outcome with the conventional asymmetric heterogeneous MPSoC method, the new DSEBBO design exhibits the performance improvement of 26.87% in data rate, and 37.18% reduction in average power consumption and 63.61% reduction in delay analysis under various traffic scenarios.

关键词： Heterogeneous Multiprocessor System-on-Chip Graph theory estimator Biogeography-based optimization field programmable gate array

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Research on Automatic Driving Lidar Ranging Method Based on TDC

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CHINESE JOURNAL OF LASERS-ZHONGGUO JIGUANG 2024年第4期51卷 193页

作者： Yu, Huijuan Wang, Yubing Zhao, Shuhua Zhang, Mingshi Song, Yue Qiu, Cheng Lei, Yuxin Jia, Peng Liang, Lei Qin, Li Wang, Lijun Chinese Acad Sci State Key Lab Luminescence & Applicat Changchun Inst Opt Fine Mech & Phys Changchun 130033 Peoples R China Univ Chinese Acad Sci Coll Optoelect Beijing 100049 Peoples R China

Objective The most critical technique of the phase -modulated continuous -wave (PhMCW) ranging method is to measure the pulse width of the intermediate frequency (IF) signal to obtain the optical time -of -flight. Time -to -digital converter (TDC) is used to measure the time interval (i. e., pulse width). The range and accuracy of the time interval measurement by a high -precision TDC module essentially determine the range and accuracy of the PhMCW lidar. The aim of this paper is to develop a large -range and high -precision TDC chip for time -of -flight measurement to support the development of high-performance PhMCW lidar for its application in the field of autonomous driving. Methods In this paper, we utilize Xilinx s Artix-7 series field programmable gate array (FPGA) chips to implement the TDC module design through the strict counting chain technique by utilizing the on -chip CARRY4 carry chain as the fundamental delay unit. This approach allows an expansion of the time measurement range by increasing only the number of bits in the first counter, achieving higher precision while utilizing fewer resources. The performance of the TDC module is tested by generating gate signals of varying lengths from the signal source, followed by experimental testing and data analysis. Finally, an actual lidar system is constructed for experimental demonstration. Results and Discussions Using the signal source to generate the measured signals with different pulse widths for practical testing, a time measurement range of 1.24 mu s is achieved. The optimal value of measurement accuracy is 26.42 ps, corresponding to a ranging accuracy of 3.96 mm (Figs. 7 and 8), which is better than the existing commercial lidar metrics (50 mm). In order to further analyze the correlation factors of the measurement accuracy, we take the 200 ns pulse width measurement data as an example in the frequency domain for analysis, and find that the TDC test results are affected by the switching power suppl

关键词： remote sensing lidar field programmable gate array time-to-digital converter (TDC) phase-modulated continuous wave intermediate frequency signal

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Performance and energy-efficient implementation of a smart city application on FPGAs

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2020年第3期17卷 729-743页

作者： Arif, Arslan Barrigon, Felipe A. Gregoretti, Francesco Iqbal, Javed Lavagno, Luciano Lazarescu, Mihai Teodor Ma, Liang Palomino, Manuel Segura, Javier L. L. Politecn Torino Turin Italy ACCIONA Infrastruct SA Madrid Spain

The continuous growth of modern cities and the request for better quality of life, coupled with the increased availability of computing resources, lead to an increased attention to smart city services. Smart cities promise to deliver a better life to their inhabitants while simultaneously reducing resource requirements and pollution. They are thus perceived as a key enabler to sustainable growth. Out of many other issues, one of the major concerns for most cities in the world is traffic, which leads to a huge waste of time and energy, and to increased pollution. To optimize traffic in cities, one of the first steps is to get accurate information in real time about the traffic flows in the city. This can be achieved through the application of automated video analytics to the video streams provided by a set of cameras distributed throughout the city. Image sequence processing can be performed both peripherally and centrally. In this paper, we argue that, since centralized processing has several advantages in terms of availability, maintainability and cost, it is a very promising strategy to enable effective traffic management even in large cities. However, the computational costs are enormous, and thus require an energy-efficient High-Performance Computing approach. field programmable gate arrays (FPGAs) provide comparable computational resources to CPUs and GPUs, yet require much lower amounts of energy per operation (around 6x for the application considered in this case study). They are thus preferred resources to reduce both energy supply and cooling costs in the huge datacenters that will be needed by Smart Cities. In this paper, we describe efficient implementations of high-performance algorithms that can process traffic camera image sequences to provide traffic flow information in real-time at a low energy and power cost.

关键词： Smart city Image processing Background subtraction Lucas-Kanade High-level synthesis field programmable gate array Graphical processing unit

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Improving FPGA-Based Logic Emulation Systems through Machine Learning

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2020年第5期25卷 1–20页

作者： Agnesina, Anthony Lim, Sung Kyu Lepercq, Etienne Del Cid, Jose Escobedo Georgia Inst Technol North Ave NW Atlanta GA 30332 USA Synopsys Inc 690 East Middlefield Rd Mountain View CA 94043 USA

We present a machine learning (ML) framework to improve the use of computing resources in the FPGA compilation step of a commercial FPGA-based logic emulation flow. Our ML models enable highly accurate predictability of the final place and route design qualities, runtime, and optimal mapping parameters. We identify key compilation features that may require aggressive compilation efforts using our ML models. Experiments based on our large-scale database from an industry's emulation system show that our ML models help reduce the total number of jobs required for a given netlist by 33%. Moreover, our job scheduling algorithm based on our ML model reduces the overall time to completion of concurrent compilation runs by 24%. In addition, we propose a new method to compute "recommendations" from our ML model to perform re-partitioning of difficult partitions. Tested on a large-scale industry system on chip design, our recommendation flow provides additional 15% compile time savings for the entire system on chip. To exploit our ML model inside the time-critical multi-FPGA partitioning step, we implement it in an optimized multi-threaded representation.

关键词： field programmable gate array SoC verification emulation flow optimization with machine learning

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