检索结果-内蒙古大学图书馆

10th Electrical Power, Electronics, Communications, Controls and Informatics Seminar (EECCIS)

作者： Abidin, Zainul Aryawiratama, Nauval Muttaqin, Adharul Arisandi, Effendi Dodi Martineac, Corina Univ Brawijaya Dept Elect Engn Malang Indonesia Natl Inst Aeronaut & Space Indonesia Ctr Rocket Technol Bogor Indonesia Tech Univ Cluj Napoca Elect Engn Fac Cluj Napoca Romania

ISBN: (数字)9781728171098

ISBN: (纸本)9781728171098

In this paper, design of data parser based on field programmable gate array (FPGA) for Global Positioning System (GPS) is presented. The FPGA system consists of Universal Asynchronous Receiver/Transmitter (UART) receiver, data parser, and UART transmitter. The data parser was designed using brute-force string matching algorithm. Simulation results show that GPS raw data of National Marine Electronics Association (NMEA) sentences were successfully parsed to $GPGGA sentence only. Finally, data of latitude, longitude, number of satellite, and altitude from $GPGGA sentence can be obtained and transmitted for further processing.

关键词： Global Positioning System field programmable gate array data parser $GPGGA

来源：评论

学校读者我要写书评

暂无评论

An Asynchronous FPGA THx2 programmable Cell for Mitigating Side-Channel Attacks 63

An Asynchronous FPGA THx2 Programmable Cell for Mitigating S...

引用

63rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Emmert, John M. Perumalla, Anvesh Concha, Luis Univ Cincinnati Dept EECS Cincinnati OH 45221 USA

ISBN: (纸本)9781728180588

One approach to mitigate side-channel attacks (SCAs) is to use clockless, asynchronous digital logic. To simplify this process, we propose a unique asynchronous FPGA based on a new THx2 programmable threshold cell. At a minimum, FPGAs require a programmable logic cell that can implement a complete set of logic so that it can be connected through the programmable interconnect network to form any digital system. To meet that criteria, we take advantage of CMOS transistors to implement a programmable THx2 threshold cell capable of performing both TH12 and TH22 asynchronous operations. Our complete sixteen transistor FPGA cell includes eight transistors to implement the base THx2 threshold operation, three transistors to switch between the TH12 and TH22 modes, and five memory cell transistors for mode storage. Our unique minimal transistor, programmable THx2 implementation enables formation of a complete set of asynchronous threshold gates and a complete set of standard combinational logic functions. The symmetric nature of the FPGA cell, in regard to the number of transistors (eight NMOS and eight PMOS), makes it ideal for a four row by four column transistor grid with a nearly square, easily array-able layout. It should be noted our THx2 cell is highly compact and suitable for implementing a clockless, asynchronous FPGA.

关键词： asynchronous security assurance trust side-channel attacks FPGA field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

An FPGA-based Application-Specific Processor for Implementing the Exponential Function

An FPGA-based Application-Specific Processor for Implementin...

引用

Annual IEEE SoutheastCon Conference

作者： Jadhav, Shrikant S. Gloster, Clay Naher, Jannatun Doss, Christopher Kim, Youngsoo North Carolina A&T State Univ Dept Comp Syst Technol Greensboro NC 27411 USA North Carolina A&T State Univ Dept Elect & Comp Engn Greensboro NC 27411 USA Bradley Univ Dept Elect Engn Peoria IL 61625 USA

ISBN: (数字)9781728168616

ISBN: (纸本)9781728168616

In this paper, we present a pipelined, high throughput single precision floating point implementation of the exponential function with a latency of 19 cycles. We also present the Application Specific Processor (ASP), a multiple memory architecture that increases memory bandwidth and overall performance of a computationally intensive application. The exponential function hardware unit is used as a function core or arithmetic unit of the ASP. Our experimental results show that executing a hardware implementation of the exponential function on a field programmable gate array (FPGA) is significantly faster than executing a software implementation on a multi-core processor. While the maximum clock rate of our FPGA board (200 MHz) is an order-of-magnitude slower than our multi-core processor (3.4 GHz), the FPGA-based hardware implementation of the exponential function is 29X and 8X faster than the multi-core processor-based software implementation and OpenMP implementation respectively.

关键词： reconfigurable computing field programmable gate array exponential function multi-memory architecture

来源：评论

学校读者我要写书评

暂无评论

Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm 24

Custom-IP for Gradient Descent Optimization based on Hardwar...

引用

24th International Symposium on VLSI Design and Test (VDAT)

作者： Shabarinath, B. B. Muralidhar, P. Natl Inst Technol Warangal Telangana India

ISBN: (纸本)9781728193694

field programmable gate arrays (FPGA's) are being deployed in cloud data centers like Amazon Elastic compute cloud F1 instances for algorithmic acceleration to leverage the advantage of reconfigurability combined with high throughput and low power consumption of FPGA's and hence balancing the dynamic workloads. Gradient Descent is one such algorithm that is extensively used in core computation kernels to train the Machine Learning (ML) models. This paper proposes a custom-IP (Intellectual Property) for hardware acceleration of Gradient Descent Algorithm (GDA) which is designed by exploring the inherent concurrency of GDA. The IP incorporates the Very High-Speed Integrated Circuit Hardware Description Language (VHDL) based description of GDA and AXI4 stream interface for connectivity. The Custom-IP is flexible and reusable by tuning generics defined in the VHDL code. The IP is interfaced to a 32-bit MicroBlaze soft-core processor which acts as host and manages run-time along with other peripherals to form a System on Chip (SoC) in which the design is partitioned into fixed hardware and flexible software. The Hardware/Software Co-design results show the 5x improvement in performance when implemented on Artix XC7A100T-CSG324 FPGA when compared to software implementation.

关键词： Amazon Elastic compute cloud F1 instance field programmable gate array Gradient Descent Algorithm Hardware/Software Co-design System on Chip

来源：评论

学校读者我要写书评

暂无评论

Finite Impulse Response Filter Design using Grasshopper Optimization Algorithm and Implementation on FPGA

Finite Impulse Response Filter Design using Grasshopper Opti...

引用

IEEE Applied Signal Processing Conference (ASPCON)

作者： Dutta, Tanay Aich, Raina Modak Dhabal, Supriya Venkateswaran, Palaniandavar Jadavpur Univ Dept Elect & Telecommun Engn Kolkata India Techno Int Batanagar Dept ECE Maheshtala W Bengal India Netaji Subhash Engn Coll Dept ECE Kolkata India

ISBN: (纸本)9781728168821

This paper establishes an efficient design style of Type-1 FIR filter using Grasshopper Optimization Algorithm (GOA) and its implementation on FPGA. GOA is a newly developed population-based meta-heuristic optimization algorithm motivated by the swarming activities of grasshoppers. GOA with its better problem-solving capability has revolutionized the contemporary era. Minimization of faults in the optimum response and the estimated response in digital filters are the main feature of meta-heuristic optimization algorithms. Therefore, this algorithm has been broadly accepted in various fields due to its high efficiency in solving problem sets. Further, to emphasis the usefulness of the suggested algorithm, the simulated outcomes have been compared with the results of the well-established algorithms such as Parks McClellan (PM) Algorithm and Sine Cosine Algorithm (SCA) and it has been found that Grasshopper Optimization Algorithm (GOA) outperform PM and SCA in terms of stop-band attenuation and pass-band ripple. Additionally, this paper also explains the hardware function of the concept being contemplated within the FPGA platform.

关键词： Finite Impulse Response Filter Grasshopper Optimization Algorithm Parks McClellan Algorithm Sine Cosine Algorithm field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Grid Impedance Estimation with Oversampling for Grid-Connected Converters 22

Grid Impedance Estimation with Oversampling for Grid-Connect...

引用

22nd European Conference on Power Electronics and Applications (EPE ECCE Europe)

作者： Himker, Niklas Strunk, Robin Mertens, Axel Leibniz Univ Hannover Inst Drive Syst & Power Elect Welfengarten 1 Hannover Germany

ISBN: (纸本)9789075815368

This paper presents a computationally simple estimation method of the grid impedance with the usage of a harmonic signal. To minimise the interference with the grid, an algorithm to define the start of the measurement is presented. Furthermore, oversampling of the current and voltage at the point of common coupling (PCC) is used to reduce the amplitude of the injected signal while still guaranteeing a high signal-to-noise ratio.

关键词： Converter Control Impedance Measurement field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

A Hardware-Oriented Echo State Network and its FPGA Implementation

引用

JOURNAL OF ROBOTICS NETWORKING AND ARTIFICIAL LIFE 2020年第1期7卷 54-58页

作者： Honda, Kentaro Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Wakamatsu Ku 2-4 Hibikino Kitakyushu Fukuoka 8080196 Japan

This paper proposes implementation of an Echo State Network (ESN) to field programmable gate array (FPGA). The proposed method is able to reduce hardware resources by using fixed-point operation, quantization of weights, which includes accumulate operations and efficient dataflow modules. The performance of the designed circuit is verified via experiments including prediction of sine and cosine waves. Experimental result shows that the proposed circuit supports to 200 MHz of operation frequency and facilitates faster computing of the ESN algorithm compared with a central processing unit. (c) 2020 The Authors. Published by Atlantis Press SARL. This is an open access article distributed under the CC BY-NC 4.0 license (http://***/licenses/by-nc/4.0/).

关键词： Reservoir computing echo state network field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

field programmable gate array-based sensorless control of a brushless synchronous starter generator for aircraft application

引用

IET ELECTRIC POWER APPLICATIONS 2011年第1期5卷 181-192页

作者： Maalouf, A. Idkhajine, L. Le Ballois, S. Monmasson, E. Thales Avion Elect Syst Elect Dev Dept F-78400 Chatou France Univ Cergy Pontoise Elect Engn & Ind Data Proc Dept F-95031 Cergy Pontoise France

Sensorless control of synchronous machine (SM) is a well-investigated research topic. However, avionics manufacturers still have restrictions about its applications due to the complexity of the on-board systems. This study presents a study investigating the use of an extended Kalman filter (EKF) to estimate the position and speed of a brushless exciter synchronous starter/generator. In spite of the machine complexity and the critical choice of the EKF covariance matrices, the EKF observer presents satisfying simulation results in estimating the position and the velocity of the mentioned motor during the start-up. Experimental results performed on an SM with an EKF implemented on a field programmable gate array are also shown to prove the efficiency of this type of implementation.

关键词： Spatial variables control brushless synchronous starter generator Control of electric power systems avionics Kalman filters Logic and switching circuits Aerospace control Avionics velocity control sensorless control Logic circuits extended Kalman filter sensorless machine control field programmable gate arrays Velocity, acceleration and rotation control Synchronous machines synchronous generators field programmable gate array position control starting observers

来源：评论

学校读者我要写书评

暂无评论

The Research and Implementation of Sobel Calculatory based on FPGA

World Scientific Research Journal

引用

World Scientific Research Journal 2021年第4期7卷 444-447页

作者： Xi Gao Liyan Zhang

The edge of the image carries a lot of important image information. When extracting the edge of the image, it can effectively reduce the amount of data while retaining most of the graphic information. And edge recognition is also the basic technology of image processing and machine vision, especially in the field of image feature extraction. The Sobel operator is an important processing method in the field of image processing, which is mainly used to obtain a degree of digital image. This article uses the dual-core ARM Cortex-A9 processor embedded in the ZYNQ platform to perfectly combine the software programmability with the hardware programmability of the FPGA, uses HLS to achieve Sobel detection, and introduces a new VDMA operation method. The image is displayed in the memory mode, and the system advantages of low power consumption and low cost realize the unparalleled system performance, flexibility, and scalability of a single chip, and accelerate the time to market of graphics processing products.

关键词： Sobel operator field programmable gate array HLS

来源：评论

学校读者我要写书评

暂无评论

A Stochastic Computing Method For Generating Activation Functions in Multilayer Feedforward Neural Networks

ELECTRICA

引用

ELECTRICA 2021年第3期21卷 376-+页

作者： Ersoy, Durmus Erkmen, Burcu Istanbul Esenyurt Univ Dept Elect & Elect Engn Istanbul Turkey Yildiz Tech Univ Dept Elect & Commun Engn Istanbul Turkey

Stochastic computing using basic arithmetic logic elements based on stochastic bit sequences provides very beneficial solutions in terms of speed and hardware cost, relative to deterministic calculation. Studies for the realization of tangent hyperbolic and exponential functions used in the development of activation functions in Artificial Neural Networks by stochastic methods exist in the literature. The techniques presented using state transitions on finite state machines were constructed on the basis of two different forms of finite state machines, one-dimensional (Linear) and two-dimensional. In this analysis, in terms of both error rate and circuit cost, the advantageous two-dimensional finite state machines based stochastic computing approach for tangent hyperbolic and exponential functions is presented. The presented approach is implemented on field programmable gate array and the results are given for hardware simulation. The dataset used for the classification process in a decentralized smart grid control has been applied to the multilayer feedforward neural network and deterministic computing, for the stability classification which is carried out separately with the linear finite state machines based stochastic computing and the proposed 2D finite state machines based stochastic computing methods.

关键词： field programmable gate array finite state machine multilayer feedforward neural networks stochastic activation function stochastic computing

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：