检索结果-内蒙古大学图书馆

The Synthesis Method of High-Speed Finite State Machines in FPGA 1

19th International Conference on Computer Information Systems and Industrial Management

作者： Salauyou, Valery Borecki, Damian Grzes, Tomasz Bialystok Tech Univ Wiejska 45A PL-15351 Bialystok Poland

ISBN: (数字)9783030476793

ISBN: (纸本)9783030476786;9783030476793

The synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. Estimations of the number of LUT levels are presented for an implementation of FSM transition functions in the case of sequential and parallel decomposition. Split algorithms of FSM internal states for the synthesis of high-speed FSMs are described. The method can be easily included in designing the flow of digital systems in FPGA. The experimental results showed a high efficiency of the offered method. FSM performance increased by 1.73 times. In conclusion, the experimental results were considered, and prospective directions for designing high-speed FSMs are specified.

关键词： Synthesis Finite state machine High-speed High performance State splitting field programmable gate array Look up table

来源：评论

学校读者我要写书评

暂无评论

Root Cause Analysis and Classification of Single Point Failures in Designs Applying Triple Modular Redundancy in SRAM FPGAs

Root Cause Analysis and Classification of Single Point Failu...

引用

作者： Swift, James D. Brigham Young University

学位级别：M.Sc.

Radiation effects encountered in space or aviation environments can affect the configuration bits in field programmable gate arrays (FPGA) causing errors in FPGA output. One method of increasing FPGA reliability in radiation environments includes adding redundant logic to mask errors and allow time for repair. Despite the redundancy added with triple modular redundancy (TMR) and configuration scrubbing there exist some configuration bits that individually affect multiple TMR domains causing errors in FPGA output. A new tool called DeBit is introduced that identifies hardware resources associated with a single bit failure. This tool identifies a novel failure mode involving global routing resources and the failure mode is verified through a series of directed tests on global routing resources. Lastly, a mitigation strategy is proposed and tested on a single error in a triple modular redundancy (TMR) design.

关键词： Single Event Upset field programmable gate array Triple Modular Redundancy Reliability SEU FPGA TMR James D. Swift Thesis

来源：评论

学校读者我要写书评

暂无评论

Hardware and software integrated coursework as a way of engineering ability training in the learning of digital electronics

引用

INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING EDUCATION 2019年第3期58卷 726-742页

作者： Zhang, Chengchang Gong, Yuwen Luo, Yuan Zhang, Huayu Yan, Dangui Chongqing Univ Posts & Telecommun Coll Electroning Engn 2 Chongwen Rd Chongqing 400065 Peoples R China

A new way oriented to engineering ability training by field programmable gate array-based hardware and software integrated coursework in the learning of digital electronics course in communication engineering is presented. This coursework is implemented in two stages during six weeks, the task of the first stage is hardware design, and the second stage task is the software design;all students are divided into several small teams with three or four persons in the process. A scheme for storing and configuring four different programs by a single programmable read-only memory (PROM)is given in hardware design. In the software design, it emphasizes the selection of the optimization scheme for different design schemes. Through competitive and engineering oriented design evaluation, the students are guided to combine theory with practice more closely to solve the actual engineering problems in the design.

关键词： Digital electronics education coursework field programmable gate array sequence signal generator

来源：评论

学校读者我要写书评

暂无评论

FPGA-based synchronising control system design for spinning disk confocal image scanning microscope

引用

ELECTRONICS LETTERS 2019年第23期55卷 1224-+页

作者： Qin, S. Georg August Univ Gottingen Inst Phys 3 Friedrich Hund Pl 1 D-37077 Gottingen Germany

In this Letter, a field programmable gate array (FPGA)-based synchronising control system design for spinning disk confocal image scanning microscope is described. Based on the analysis on the condition of laser triggering, the author simplifies the design by transforming the floating-point calculation formula to a very simple form of integer calculation, which can then be implemented by fixed-point calculation on FPGA without trimming any bit, for which there is no computational precision loss. The testing of simulation and experiment shows that the design is very accurate and reliable.

关键词： field programmable gate arrays synchronisation floating point arithmetic image scanners microscopes floating-point calculation formula fixed-point calculation field programmable gate array synchronising control system design FPGA spinning disk confocal image scanning microscope laser triggering integer calculation

来源：评论

学校读者我要写书评

暂无评论

Multi-objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs

引用

IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第4期13卷 273-281页

作者： Wang, Yuan Trefzer, Martin A. Bale, Simon J. Walker, James A. Tyrrell, Andy M. Univ Hertfordshire Sch Engn & Technol Hatfield Herts England Univ York Dept Elect Engn York N Yorkshire England

Circuit clustering algorithms fit synthesised circuits into field programmable gate array (FPGA) configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g. power and delay. In this study, the authors present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. They address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. The authors' new approach has been validated using the 'Golden 20' MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this study achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. The key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance.

关键词： field programmable gate arrays logic design genetic algorithms network routing integrated circuit design timing circuits electronic design automation flexible EDA flow interconnect minimisation place-and-route process configurable logic blocks field programmable gate array timing driven circuit clustering multiobjective optimisation algorithm real-world circuit design FPGA-related literature Golden 20 MCNC benchmark circuits CLB utilisation CLB input bandwidth constraints multiobjective genetic algorithm time optimising circuit performance parameters FPGA CAD flow

来源：评论

学校读者我要写书评

暂无评论

MPC based Controller Design of Battery Integrated Modular Multilevel Converter

MPC based Controller Design of Battery Integrated Modular Mu...

引用

第40届中国控制会议

作者： Fang Xu Zhongyi Guo Qifang Liu Hong Chen Yali Qu State Key Laboratory of Automotive Simulation and Control Jilin University College of Communication Engineering Jilin University Department of control science and engineering Tongji University Huawei Technologies Co. Ltd.

The control performance of converter directly affects the drive efficiency of electric vehicle（EV）.This paper studies on the model predictive control（MPC） based controller design of battery integrated modular multilevel converter（B-MMC）.Aiming at the goal of three-phase current tracking and battery balancing control of B-MMC,three-layer controllers are *** first controller is the finite control set model predictive control（FCS-MPC）,which realizes the motor drive by tracking the phase *** second controller is the circulation controller for the active balance control of *** is composed of multiple proportional controllers to realize the battery balance between the bridge *** third controller is the battery sorting algorithm to achieve the passive balance control of the battery in the same bridge *** the same time,field programmable gate array（FPGA） is used to accelerate the controller to meet the real-time requirements of ***,the simulation results of the B-MMC control system validates the effectiveness of the control algorithm.

关键词： Electric Vehicle Battery Integrated Modular Multilevel Converter Finite Control Set Model Predictive Control field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Experience of how to build an MRI machine from scratch

引用

Progress in Nuclear Magnetic Resonance Spectroscopy 2025年

作者： Shaoying Huang José Miguel Algarín Joseba Alonso R. Anieyrudh Jose Borreguero Fabian Bschorr Paul Cassidy Wei Ming Choo David Corcos Teresa Guallart-Naval Heng Jing Han Kay Chioma Igwe Jacob Kang Joe Li Sebastian Littin Jie Liu Gonzalo Gabriel Rodriguez Eddy Solomon Li-Kuo Tan Rui Tian Bernhard Blümich Singapore University of Technology and Design Singapore Instituto de Instrumentación para Imagen Molecular Valencia Spain Department of Internal Medicine II University Ulm Medical Center Ulm Germany Institute of Molecular and Cell Biology Agency for Science Technology and Research (A*STAR) Singapore Engineering Product Development Singapore University of Technology and Design Singapore Agile MRI ltd Tel Aviv Israel Department of Biomedical Engineering Columbia University New York USA Jiangsu LiCi Medical Device Co. Ltd China Division of Medical Physics Department of Diagnostic and Interventional Radiology University Medical Center Freiburg Faculty of Medicine University of Freiburg Freiburg Germany NingBo ChuanShanJia Electrical and Mechanical Co. Ltd China Max-Planck Institute for Multidisciplinary Sciences Göttingen Germany Biomedical Engineering Technion - Israel Institute of Technology Haifa Israel Department of Biomedical Imaging Faculty of Medicine Universiti Malaya Malaysia Rui Tian High-Field MR center Max Planck Institute for Biological Cybernetics Tübingen Germany Institut für Technische Und Makromolekulare Chemie RWTH Aachen University Aachen Germany

Nuclear magnetic resonance instruments are becoming available to the do-it-yourself community, and there is increasing interest in the practical aspects of building a magnetic resonance imaging instrument from scratch. This review is focused on the different steps involved in such an endeavour, the challenges encountered and their solutions; it is based on experience gained at a four-day “hackathon” (named “ezyMRI”) at Singapore University of Technology and Design in spring 2024. One day of this event was devoted to educational lectures and three days to system construction and testing; seventy young researchers from all parts of the world formed six teams focusing respectively on magnet, gradient coil, RF coil, console, system integration, and design, which together produced a working MRI instrument in three days.

关键词： NMR Low-field MRI DIY Hackathon ezyMRI CAD Computer aided design EPI Echo planar imaging FHDO Fachhochschule Darmstadt FPGA field programmable gate array GPA Gradient power amplifier LNA Low noise amplifier MaRCoS Magnetic resonance control system MaRGE MaRCoS graphical environment MRI Magnetic resonance imaging NMR Nuclear magnetic resonance OCRA Open-source console for real-time acquisition PM Permanent magnet PMA Permanent magnet array RF Radio frequency RFPA Radio frequency power amplifier Rx Receiver SmCo Samarium cobalt STL Stereolithography Tx Transmitter

来源：评论

学校读者我要写书评

暂无评论

Comparison of practical methods for an efficient FPGA implementation of STAP

引用

INTERNATIONAL JOURNAL OF ELECTRONICS 2019年第9期106卷 1320-1331页

作者： Hasanikhah, Narjes Amin-Nejad, Siavash Darvish, Ghafar Moniri, M. R. Islamic Azad Univ Dept Elect & Comp Engn Sci & Res Branch Tehran Iran Univ Guilan Dept Elect Engn Rasht *** Iran Islamic Azad Univ Dept Elect Engn Yadegar E Emam Branch Tehran Iran

This study investigated and compared the practical methods used for the efficient field- programmable gate array (FPGA) implementation of space-time adaptive processing (STAP). The most important part of calculating the STAP weights is the QR decomposition (QRD), which can be implemented using the modified Gram-Schmidt (MGS) algorithm. The results show that the method that uses QRD with less computational burden leads to a more effective implementation. Its structure was parameterised with the vector size to create a trade-off between the hardware and performance factors. For this purpose, QRD-MGS algorithm was first modified to increase the speed, and then the STAP weight vector was calculated. The implementation results show that decreasing the vector size decreases the resource utilisation, computational burden and the consumption power. While the computation time increases slightly, the updated rate of the STAP weights is maintained. For example, the STAP weights in a system with 6 antenna arrays, 10 received pulses and 200 range samples computed in 262 mu s using a vector size of 17 on the Arria10 FPGA that has a maximum of 155 mu s correlates to the QRD-MGS algorithm and 107 mu s correlates to the other parts. Therefore, QRD-MGS algorithm is the most important component of the calculation of the STAP weight vector, and its simplification leads to efficient implementation.

关键词： Computation time field programmable gate array QR decomposition Space time adaptive processing

来源：评论

学校读者我要写书评

暂无评论

Infrared Target Detection and Recognition Method in Airborne Photoelectric System

引用

JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2019年第3期16卷 94-106页

作者： Ding, Meng Sun, Zhejun Wei, Li Cao, Yunfeng Yao, Yuheng Nanjing Univ Aeronaut & Astronaut Coll Civil Aviat Nanjing 210016 Jiangsu Peoples R China Nanjing Univ Aeronaut & Astronaut Jin Cheng Coll Nanjing 210016 Jiangsu Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Astronaut Nanjing 210016 Jiangsu Peoples R China Univ Southern Calif Viterbi Sch Engn 649 W 34th St Los Angeles CA 90089 USA

Infrared target detection and recognition are investigated by considering the wide application requirements of an airborne photoelectric system. The proposed algorithm can be divided into three parts. First, on the basis that the target of infrared images dominates the background in the frequency domain, this paper presents a method of candidate region detection. The detection algorithm first generates a saliency map using the discrete cosine transform and then identifies candidate regions by computing and comparing saliency scores of different regions. Second, to extract the features of each candidate region for recognition, the paper presents a local descriptor and subsequently uses locality-constrained linear coding and a pooling operator to obtain the feature vector of the target, and then further completes target recognition via a simple linear classifier. Finally, as preliminary research on the engineering application of related algorithms, the detection and recognition algorithms are transplanted to an embedded platform. The paper conducts experiments on six test sequences to evaluate the performance of the proposed algorithms and the computing efficiency on the embedded platform. An evaluation experiment and comparison experiment verify the effectiveness and practicability of the proposed algorithms.

关键词： Computing Frequency Domain field programmable gate array Convolutional Neural Network Airport Towers Sensor Technology Unmanned Aerial Vehicle Graphics Processing Unit Support Vector Machine Focal Plane arrays

来源：评论

学校读者我要写书评

暂无评论

Low power VLSI implementation of real fast Fourier transform with DRAM-VM-CLA

引用

MICROPROCESSORS AND MICROSYSTEMS 2019年第Sep.期69卷 92-100页

作者： Turaka, Rajasekhar Ram, Satya Sai M. Velagapudi Ramakrishna Siddhartha Engn Coll Dept Elect & Commun Engn Vijayawada Andhra Pradesh India RVR & JC Coll Engn Dept Elect & Commun Engn Guntur 522019 Andhra Pradesh India

In recent years, Fast Fourier Transform (FFT) plays a vital role in signal processing application for converting time domain to frequency domain. This paper presents Real FFT architecture which is implemented in radix-2 Decimation- in-Frequency (DIF). Instead of using more number of Random Access Memory (RAM), single Dual port RAM (DRAM) is used to store the intermediate data results. In Processing Element (PE), normal multiplier and adder has been used in previous works. In this paper, Vedic Multiplier (VM) and Carry Lookahead Adder (CLA) is used for improving the Real FFT operation and it is implemented in Verilog code. Application Specified Integrated Circuits (ASIC) and field programmable gate array (FPGA) performances are evaluated for all the architectures. In DRAM-VM-CLA architecture, LUT, flip flop, slices, and frequency are improved in FPGA performance as well as area, power, and delay are improved in ASIC performance. In ASIC 180 nm technology, 81.14% of area, 45.98% of delay, and 89.77% of Area Delay Product (ADP) is minimized in DRAM-VM-CLA as well as 72.64% of area, 5.44% of delay, and 74.10% of ADP is reduced in ASIC 45 nm technology. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Application specified integrated circuits Carry lookahead adder Dual port RAM field programmable gate array Real FFT Vedic multiplier

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：