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Design and FPGA Implementation of a Novel Efficient FRM-Based Channelized Receiver Structure

IEEE ACCESS 2019年 7卷 114778-114787页

作者： Zhang, Wenxu Yao, Yushuang Zhao, Zhongkai Zhao, Wentong He, Junxi Harbin Engn Univ Coll Informat & Commun Engn Harbin 150001 Peoples R China

The main application of the filter bank in radar signal processing is the wideband digital channelized receiver. In order to save hardware resources of the field programmable gate array (FPGA), the efficient channelized receiver structure using polyphase filter has been designed. However, when the number of channels is greatly increased or the transition bandwidth of the filter bank (FB) becomes very narrow, it still consumes large amounts of hardware resources. Therefore, a novel efficient channelized receiver structure based on frequency response masking (FRM) and modulation filter bank is proposed in this paper. The proposed novel structure has less computational complexity in implementing FB with narrow transition bandwidth (NTB). Compared with other efficient FRM-based structures, the proposed novel structure is more suitable for wideband digital channelization receiver. The proposed novel structure is verified correctly by Matlab simulation. The FPGA implementation of the polyphase channelized receiver structure and the proposed novel efficient FRM-based channelized receiver structure are completed by Xilinx System Generator. The result shows that the proposed novel efficient FRM-based channelized receiver structure can save 48.09% of the DSP48E1 hardware resources compared with the polyphase channelized receiver structure and has low group delay characteristic.

关键词： Frequency response masking narrow transition bandwidth channelized receiver field programmable gate array

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Parallel-Pipelined-Memory-Based Blowfish Design with Reduced FPGA Utilization for Secure ZigBee Real-Time Transmission

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WIRELESS PERSONAL COMMUNICATIONS 2019年第1期104卷 471-489页

作者： Ahmad, Rafidah Kho, Daniel Abd Manaf, Asrulnizam Ismail, Widad Univ Sains Malaysia Collaborat Microelect Design Excellence Ctr CEDEC Engn Campus Nibong Tebal 14300 Penang Malaysia Multimedia Univ Persiaran Multimedia Fac Engn Cyberjaya 63100 Selangor Malaysia Univ Sains Malaysia Sch Elect & Elect Engn AutoID Lab Engn Campus Nibong Tebal 14300 Penang Malaysia

Data security is currently become a serious concern in wireless communication system for both the users and providers. Without a secure medium, the data transmission is exposed to various types of wireless attacks. Therefore, this paper focuses on the development of a high performance parallel-pipelined-memory-based ((PM)-M-2) Blowfish as a security design with reduced field programmable gate array (FPGA) utilization, which is the best security design to be embedded in the mobile devices. Through FPGA platform, the performance of the proposed Blowfish shows that a throughput increases by 10.5%, with the hardware utilization and power consumption decrease by 3.5% and 21%, respectively. The (PM)-M-2 Blowfish was validated in two-way communication channel by using FPGA-based radio platform together with ZigBee technology and the real-time transmission was measured in terms of bit-error-rate, received power and communication range. These characteristics have proven that the proposed (PM)-M-2 Blowfish possesses the ability to replace the advanced encryption standard which is known as a complex algorithm employed by most of the wireless communication standards.

关键词： Power-throughput Blowfish field programmable gate array ZigBee Bit-error-rate

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Hardware co simulation of LTE physical layer for mobile network applications

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2019年 99卷 124-133页

作者： Venkataramanan, V. Lakshmi, S. Sathyabama Inst Sci & Technol Sch Elect & Elect Engn Dept Elect & Commun Chennai 119 Tamil Nadu India

Due to the rapid growth of wireless technology, it has become possible to provide solutions for fading, interference, and multipath. Long term evolution and Long term evolution Advanced systems describe the standards based on 3rd Generation partnership project to overcome issues related to wireless technology. These techniques mitigate the latency and improves the system capacity. The Long term evolution physical layer uses orthogonal frequency division multiple access for downlink, and Single carrier-frequency division multiple access for uplink. Therefore this study provides a comprehensive investigation of orthogonal frequency division multiple access and Single carrier-frequency division multiple access transmission model and investigate physical layer performance of Long term evolution system using MATLAB - Simulink - Xilinx system generator platform based on releases, simulation implementation;results may be discussed in terms of Register transfer level design, power estimation, and resource estimation. For synthesis and implementation of the above architecture Plan ahead tool on Virtex, device board is used. (C) 2018 Published by Elsevier B.V.

关键词： field programmable gate array Hardware co-simulation Long term evolution Multiple input multiple output Orthogonal frequency division multiplexing The 3rd generation partnership project

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Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs

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IEEE ACCESS 2019年 7卷 57527-57538页

作者： Adhikari, Prottay M. Hooshyar, Hossein Vanfretti, Luigi Rensselaer Polytech Inst Dept Elect Comp & Syst Engn Troy NY 12180 USA Elect Power Res Inst 3412 Hillview Ave Palo Alto CA 94304 USA

Phasor Measurement Units (PMUs) are becoming intrinsic components of modern power systems. The synchrophasor estimation algorithms in PMUs pose stringent computational demands, which makes the application of field programmable gate arrays (FPGA) highly attractive. Previous works reported the implementation of PMU algorithms on specific FPGA-targets using a particular PMU design. This paper explores the implementation of different PMU designs on multiple FPGA targets using Xilinx and NI software and hardware infrastructures and toolsets. In this process, a metric has been formulated to predict FPGA-target hardware requirements. The metric allows predicting if an FPGA-target meets the needs to deploy a given PMU design resulting in significant engineering design time savings. Since the compilation/synthesis on FPGAs is a time-consuming job, this metric can reduce the implementation time for FPGA-based PMUs drastically and can help in determining if additional functionalities can be added.

关键词： Phasor measurement unit field programmable gate array

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FPGA-based implementation of cuckoo search

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第1期13卷 28-37页

作者： Alfailakawi, Mohammad Gh. El-Shafei, Mohammed Ahmad, Imtiaz Salman, Ayed Kuwait Univ Comp Engn Dept Khaldiyah POB 5969 Safat 13060 Kuwait

Cuckoo search (CS) is a recent swarm intelligence-based meta-heuristic optimisation algorithm that has shown excellent results for a broad class of optimisation problems in diverse fields. However, CS is generally compute intensive and slow when implemented in software requiring large number of fitness function evaluations to obtain acceptable solutions. In this study, the authors present a problem specific parallel pipelined field programmable gate array-based accelerator to reduce execution time when solving complex optimisation problems. Experiments conducted on a large number of well-known benchmark functions revealed that the hardware approach offers a promising average speedup of 75x and 53x than software and GPU implementations, respectively.

关键词： swarm intelligence search problems optimisation field programmable gate arrays parallel processing mathematics computing pipeline processing FPGA-based implementation cuckoo search CS swarm intelligence-based meta-heuristic optimisation algorithm fitness function evaluations parallel pipelined FPGA-based accelerator field programmable gate array execution time reduction complex optimisation problems benchmark functions

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Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

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IEEE ACCESS 2019年 7卷 103938-103947页

作者： Guerrieri, Andrea Kashani-Akhavan, Sahand Asiatic, Mikhail Ienne, Paolo Ecole Polytech Fed Lausanne Architecture Lab CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne Very Large Scale Comp Lab VLSC CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing such HAs in an embedded Linux environment involves handling Linux kernel source code and creating custom device drivers specific to a target platform, therefore negatively impacting development costs, portability and time-to-market. To address this issue, we present LEOSoC, a snap-on user-space manager for dynamically reconfigurable SoCs. Using LEOSoC does not require any specific version of the Linux kernel, nor to rebuild a custom driver for each new kernel *** consists of a base hardware system and a software layer which run on SoCs from various vendors. The system identifies the SoC on which it is running and auto-adapts its communication channels to the HAs accordingly. Furthermore, LEOSoC allows applications to partially or completely change the structure of the HAs at runtime without rebooting the system by leveraging the underlying SoC support for dynamic full/partial FPGA reconfiguration. The system has been tested on multiple commercial off the shelf (COTS) boards from different vendors, each one running different versions of Linux, therefore proving the real portability and usability of LEOSoC in a custom industrial design. Finally, we use a cloud detection algorithm for multispectral image processing as a showcase for LEOSoC's capabilities and performance.

关键词： Adaptive systems field programmable gate array multithreading reconfigurable architectures system-on-chip

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High-speed distance relaying using least error squares method and testing with FPGA

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IET GENERATION TRANSMISSION & DISTRIBUTION 2019年第16期13卷 3591-3600页

作者： Liu, Shenyi Jin, Xingxing (Shane) Gokaraju, Ramakrishna (Rama) Univ Saskatchewan Dept Elect & Comp Engn 57 Campus Dr Saskatoon SK Canada

The demand for high-speed protective relaying in modern power grids is growing. A relay's fast and secure operation to clear faults is critical, especially for EHV/UHV transmission systems (400 kV and above). This research proposes a sub-cycle distance relaying, which is based on the least error squares (LES) method, and with a data interface module implemented on field programmable gate array (FPGA). Taking advantage of inherent parallelism and pipelined architecture of the FPGA, the proposed relay design can support real-time data communications. Also, the flexible and reliable feature of the LES algorithm allows the proposed relay to make a fast and secure trip decision in different scenarios. The case studies demonstrate the effectiveness of the LES-based relay.

关键词： power transmission lines relay protection power transmission protection power grids power transmission faults data communication field programmable gate arrays least squares approximations parallel architectures sub-cycle distance relaying data interface module field programmable gate array FPGA relay design real-time data communications LES algorithm fast trip decision secure trip decision LES-based relay high-speed protective relaying modern power grids EHV-UHV transmission systems least error squares method high-speed distance relaying LES method pipelined architecture parallelism architecture voltage 400 0 kV

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Adaptive direct power control based on ANN-GWO for grid interactive renewable energy systems with an improved synchronization technique

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INTERNATIONAL TRANSACTIONS ON ELECTRICAL ENERGY SYSTEMS 2019年第3期29卷 e2766.1-e2766.15页

作者： Djema, Mohamed Amine Boudour, Mohamed Agbossou, Kodjo Cardenas, Alben Doumbia, Mamadou Lamine Univ Sci & Technol Houari Boumediene Dept Elect Engn Lab Elect & Ind Syst Algiers 16111 Algeria Univ Quebec Trois Rivieres Dept Elect & Comp Engn Trois Rivieres PQ Canada Univ Quebec Trois Rivieres Hydrogen Res Inst Trois Rivieres PQ Canada

This paper investigates the improvement of synchronization technique for single-phase inverter. Specifically, the paper proposes a modified structure of second-order generalized integrator with frequency-locked loop (SOGI-FLL) with FLL gain normalization. The proposed structure enhances the frequency detection, which makes it a powerful technique under distorted grid voltage. The validation of the proposed synchronization method includes simulations and experimental tests using Xilinx field programmable gate array (FPGA) as the target device. Moreover, time domain simulations using the direct power control (DPC) with the proposed structure are performed. The decoupled active and reactive powers are controlled using the artificial neural networks (ANNs) trained by the mean of a metaheuristic algorithm. In this paper, the grey wolf optimizer (GWO) is proposed to train the multilayer perceptron (MLP). The proposed approach shows better generation of synchronization signals and smooth power quality, making it suitable for grid-tied and microgrids (MGs) power systems control.

关键词： adaptive control direct power control for single-phase inverter field programmable gate array frequency-locked loop neural networks second-order generalized integrator

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Multi-Node All-Optical Interconnect Network Routing for Data-Center Parallel Computers

IEEE PHOTONICS JOURNAL

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IEEE PHOTONICS JOURNAL 2019年第2期11卷 1-8页

作者： Yang, Shuailong Yang, Liu Luo, Fengguang You, Biyu Ni, Yao Chen, Danhui Huazhong Univ Sci & Technol Natl Engn Lab Next Generat Internet Access Syst Sch Opt & Elect Informat Wuhan 430074 Hubei Peoples R China

A multi-node all-optical interconnect network-routing architecture scheme and implementation technology are designed to improve high-speed and large-capacity data transmission in data centers. In the design of the optical interconnect routing electro-optic printed circuit board (EOPCB), the signal generated by the FPGA is directly modulated by the VCSEL arrays, and through the coupler into the parallel optical waveguide. The transmission link and optical switch are operated in optical domain. The designed optical waveguide comprises 12 waveguide arrays with the space of 250 mu m. The all-optical interconnection routing system, which is based on the EOPCB high-speed chip multi-node waveguide, is designed, and a 4 x 4 EOPCB is fabricated. The performance of the waveguide and the entire optical interconnection network is tested. Based on 10 Gb/s VCSEL arrays, the optical interconnect network system can reach a bandwidth of 640 GHz for 4 x 4 networks. The best bit error rate for the switching system can reach 9.0 x 10(-12) with no transmission error.

关键词： Optical interconnection waveguide and optical communications field programmable gate array electro-optic printed circuit board

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SoC implementation of a photovoltaic reconfiguration algorithm by exploiting a HLS-based architecture

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MATHEMATICS AND COMPUTERS IN SIMULATION 2019年 158卷 520-537页

作者： Petrone, G. Serra, F. Spagnuolo, G. Monmasson, E. Univ Salerno DIEM Fisciano SA Italy Univ Cergy Pontoise SATIE Paris France

The dynamic reconfiguration of photovoltaic arrays is a promising technique for reducing the power drops due to partial shadowing. Some approaches for determining the optimal electrical configuration of the photovoltaic array have been presented in literature. The most encouraging solution is based on the use of stochastic algorithms that can be fruitfully implemented in a system on chip. The computation time takes profit from the available field programmable gate array fabric, where multiple instances of the fitness function can be run in parallel. The use of Vivado High Level Synthesis, to create a Register Transfer Level implementation from C/C++ sources, allows achieving satisfactory results. Coding the algorithm by taking into account the synthesis process, thus resource allocation, scheduling and binding, helps in obtaining a further performance improvement. In this paper a High Level Synthesis approach is used for the systematic exploration of the possible architectures that can be used for implementing the reconfiguration algorithm. Some solutions that differ in terms of computation time and hardware resources used are compared. The target system on chip is a low cost one from Xilinx. (C) 2019 International Association for Mathematics and Computers in Simulation (IMACS). Published by Elsevier B.V. All rights reserved.

关键词： High Level Synthesis field programmable gate array Hardware accelerator Photovoltaic

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