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19th Polish Control Conference (KKA)

作者： Wojtulewicz, Andrzej Warsaw Univ Technol Inst Control & Computat Engn Ul Nowowiejska 15-19 PL-00665 Warsaw Poland

ISBN: (纸本)9783319606996

This paper describes implementation of the Dynamic Matrix Control (DMC) algorithm performed on an Altera field programmable gate array (FPGA) with the Cyclone IV chip. The DMC algorithm is implemented in its analytical (explicit) version which requires computationally simple matrix and vector operations in real time, no on-line optimisation is necessary. The test-bench application is prepared for fast comparison between C and HDL versions of code. A large number of independent logic cells can provide multi-parallel operations to achieve very fast operations. As a result, the algorithm may be used for controlling very fast dynamic processes characterised by sampling periods of millisecond order. Preliminary results of real experiments are demonstrated. The discussed control structure provides possibility to fast change of algorithm.

关键词： Dynamic Matrix Control Model Predictive Control field programmable gate array

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Optical Fiber Sensor System Design Utilizing The field programmable gate array 14

Optical Fiber Sensor System Design Utilizing The Field Progr...

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2017 14th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)

作者： Ong, Yong Sheng Grout, Ian Lewis, Elfed Mohammed, Waleed Univ Limerick Dept Elect & Comp Engn Limerick Ireland Bangkok Univ BU CROCCS Sch Engn Rangsit Campus Bangkok Thailand

ISBN: (纸本)9781538604496

This paper presents the design of a system that is aimed to provide a flexible, portable and low cost solution for optical fiber based sensor systems. The field programmable gate array (FPGA) provides the digital logic to implement the system and ability to reconfigure the system operation. It aims to support different optical fiber sensing requirements by the ability to reconfigure the digital circuitry used. It is therefore a hardware configured alternative to a software programmed processor based approach. The work discussed in this paper focuses on the architecture of the FPGA based system with additional circuitry to implement the light source using a light emitting diode (LED), sensor signal sampling using a photodiode and the digital functions implemented using the Xilinx Artix-7 FPGA. The system also includes serial communications to an external computer that allows the system to be used as part of a larger sensor network. In this paper, system control and sensor data visualization on a personal computer (PC) is undertaken using the Python open source programming language.

关键词： field programmable gate array optical fiber sensor flexibility design Python

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REAL-TIME SIMULATION AND VISUALIZATION ARCHITECTURE WITH field programmable gate array (FPGA) SIMULATOR

REAL-TIME SIMULATION AND VISUALIZATION ARCHITECTURE WITH FIE...

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2nd ASME 2010 World Conference on Innovative Virtual Reality

作者： Karkee, Manoj Monga, Madhu Steward, Brian L. Zambreno, Joseph Kelkar, Atul G. Iowa State Univ Dept Agr & Biosyst Engn Ames IA 50011 USA

ISBN: (纸本)9780791849088

Real-time simulation of dynamic vehicle system models is essential to facilitate advances in operator and hardware in the loop simulation and virtual prototyping. Real-time virtual reality-based simulation enables users to visualize and perceive the effect of their actions during the simulation. As model complexity is increased to improve the model fidelity, the computational requirements will also increase, thus increasing the challenge to meet real-time constraints. A distributed simulator architecture was developed for off-road vehicle dynamic models and 3D graphics visualization to distribute the overall computational load across multiple computational platforms. This architecture consisted of three major components: a dynamic model simulator, a virtual reality simulator, and an interface to controller and input hardware devices. The dynamic model simulator component was developed using Matlab/Simulink Real Time Workshop on a PC and also using field programmable gate arrays (FPGA), which offered a highly parallel hardware platform. The simulator architecture reduced the computational load to an individual platform and increased the real-time simulation capability with complex off-road vehicle system models and controllers. The architecture was used to develop, simulate and visualize a tractor and towed implement steering dynamics model. The model also included a steering valve subsystem which contained very high frequency hydraulic dynamics and required 10 mu s integration time step for numerical stability. The real-time simulation goal was not achievable for the model with this level of complexity when the PC-based simulator was used. However, the FPGA-based simulator achieved a real-time goal taking only 2 mu s to complete one integration time step.

关键词： Real-time Simulation Distributed Architecture Virtual Reality Vehicle Dynamics Models field programmable gate array

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Implementation of Multiple-Input Multiple-Output Dynamic Matrix Control Algorithm for Fast Processes Using field programmable gate array

Implementation of Multiple-Input Multiple-Output Dynamic Mat...

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15th IFAC/IEEE Conference on programmable Devices and Embedded Systems (PDeS)

作者： Wojtulewicz, Andrzej Lawrynczuk, Maciej Warsaw Univ Technol Inst Control & Computat Engn Ul Nowowiejska 15-19 PL-00665 Warsaw Poland

The objective of this paper is to describe an implementation of a Dynamic Matrix Control (DMC) algorithm for a field programmable gate array (FPGA). The DMC algorithm is implemented in a universal version for multiple-input multiple-output dynamic processes. The results of real experiments are presented in which the DE2i-150 development board produced by Terasic with Intel Cyclone IV GX chip is used. As the controlled process a laboratory stand especially developed for this work is used, which is a dynamic system with two manipulated inputs and two controlled outputs. The implemented DMC controller is very fast, it may be used for controlling processed which need sampling periods of a millisecond order. (C) 2018, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Model Predictive Control Dynamic Matrix Control field programmable gate array

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Implementation of Digital PID controller in field programmable gate array (FPGA)

Implementation of Digital PID controller in Field Programmab...

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3rd India International Conference on Power Electronics

作者： Subasri, V. Lavanya, K. Umamaheswari, B. Anna Univ Coll Engn Guindy Tamil Nadu India

ISBN: (纸本)9781424434503

Proportional Integral Derivative (PID) controller is the most preferable controller in industries that does not require precise analytical model of the system to be controlled. Implementation of PID controllers has gone through several stages of evolution from the early mechanical and pneumatic designs to the microprocessor based systems. Recently "field programmable gate array" has become an alternative solution for the realization of Digital PID controllers. This work is aimed at the implementation of serial, parallel and mixed PID controller architectures using FPGA. The digital PID so designed is based essentially in architectures including multipliers, adders and some other logic circuits.

关键词： field programmable gate array Digital PID Architecture

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Systematic realization of a fully connected deep and convolutional neural network architecture on a field programmable gate array

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COMPUTERS & ELECTRICAL ENGINEERING 2022年 97卷 107628-107628页

作者： Mukhopadhyay, Anand Kumar Majumder, Sampurna Chakrabarti, Indrajit Indian Inst Technol Kharagpur Dept Elect & Elect Commun Engn Kharagpur W Bengal India

A detailed methodology for implementing a fully connected (FC) deep neural network (DNN) and convolutional neural network (CNN) inference system on a field programming gate array (FPGA) is presented. Minimal computational units are used for the DNN. For the CNN, systolic array (SA) architecture endowed with parallel processing potential is utilized. Algorithmic analysis determines the optimum memory requirement for the fixed point trained parameters. The size of the trained parameters and the available memory on the target FPGA device govern the choice of on-chip memory to utilize. Experimental results indicate that the choice of block over distributed memory saves approximate to 62% look-up-tables (LUTs) for the DNN ([784-512-512-10]), and the choice of distributed over block memory saves approximate to 30% block random access memory (BRAM) for the LeNet-5 CNN unit. This study provides insights for developing FPGA-based digital systems for applications requiring DNN and CNN.

关键词： Deep neural network Fully connected Convolutional neural network Systolic array Inference system Very large scale integration Architecture field programmable gate array

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Accelerating object detection via a visual-feature-directed search cascade: algorithm and field programmable gate array implementation

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JOURNAL OF ELECTRONIC IMAGING 2016年第4期25卷 041013-041013页

作者： Kyrkou, Christos Theocharides, Theocharis Univ Cyprus KIOS Res Ctr Intelligent Syst & Networks Dept Elect & Comp Engn Kallipoleos 75 CY-1678 Nicosia Cyprus

Object detection is a major step in several computer vision applications and a requirement for most smart camera systems. Recent advances in hardware acceleration for real-time object detection feature extensive use of reconfigurable hardware [field programmable gate arrays (FPGAs)], and relevant research has produced quite fascinating results, in both the accuracy of the detection algorithms as well as the performance in terms of frames per second (fps) for use in embedded smart camera systems. Detecting objects in images, however, is a daunting task and often involves hardware-inefficient steps, both in terms of the datapath design and in terms of input/output and memory access patterns. We present how a visual-feature-directed search cascade composed of motion detection, depth computation, and edge detection, can have a significant impact in reducing the data that needs to be examined by the classification engine for the presence of an object of interest. Experimental results on a Spartan 6 FPGA platform for face detection indicate data search reduction of up to 95%, which results in the system being able to process up to 50 1024 x 768 pixels images per second with a significantly reduced number of false positives. (C) 2016 SPIE and IS&T

关键词： object detection depth extraction edge detection motion detection field programmable gate array hardware architecture

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High-efficiency low-power microdefect detection in photovoltaic cells via a field programmable gate array-accelerated dual-flow network

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APPLIED ENERGY 2022年 318卷

作者： Wang, Haoxuan Chen, Huaian Wang, Ben Jin, Yi Li, Guiqiang Kan, Yan Univ Sci & Technol China Sch Engn Sci Hefei 230026 Anhui Peoples R China Univ Sci & Technol China Innovat Lab WuHu State Owned Factory Machining Hefei 230026 Anhui Peoples R China

Harvesting solar energy through photovoltaic (PV) power systems plays an important role in achieving the goal of carbon neutrality. However, the early microdefects in PV cells considerably affect the efficiencies of PV power systems. In addition, the growing number of PV power systems require more efficient and economic detection methods to ensure the long-term efficiency of PV power systems. To address this problem, recent state-of-the-art methods have attempted to use a convolutional neural network (CNN) model. However, these methods involve large amounts of parameters and require too many calculations, considerably affecting the efficiency, economy, and flexibility in real applications. In this work, we propose a lightweight dual -flow defect detection network (DDDN) and accelerate it with a field programmable gate array (FPGA) based on the developed dual-flow parallel computing architecture (DPCA). The DDDN can accurately detect early microdefects in PV cells with low calculations and storage costs, while the DPCA optimizes the data access and computation process to improve detection efficiency and reduce power consumption. Benefiting from the designed DDDN and DPCA, the proposed system achieves a high detection accuracy (88.26%), low power consumption (22 W), and competitive detection efficiency, making it more suitable than previous methods for ensuring the long-term efficiency of PV power systems.

关键词： Photovoltaic modules Defect detection Deep learning Convolutional neural network field programmable gate array Electroluminescence imaging

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Hologram synthesis accelerated in field programmable gate array by partial quadratic interpolation

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OPTICAL ENGINEERING 2009年第8期48卷 085802-085802页

作者： Hanak, Ivo Zemcik, Pavel Zadnik, Martin Herout, Adam Univ W Bohemia Plzen 30614 Czech Republic Brno Univ Technol Dept Comp Graph & Multimedia Brno 61266 Czech Republic

Numerical models of holograms are available but their evaluation is a very computationally intensive task. We present an acceleration algorithm for optical field synthesis suitable for the reduced occlusion method of hologram synthesis. The acceleration uses an approximation that is designed for a field programmable gate array (FPGA) and therefore it mostly uses fixed point numbers. The work describes the approximation, its fixed-point modification, and the resulting FPGA structure. The results presented show that the solution produces high-quality holograms in a significantly reduced time due to efficient FPGA implementation. (C) 2009 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3205081]

关键词： field programmable gate array digital hologram optical field synthesis point light source

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Embedding an Electrical System Real-Time Simulator with Floating-Point Arithmetic in a field programmable gate array

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ENERGIES 2021年第24期14卷 8404页

作者： Queiroz, Janailson Carvalho, Sarah Barros, Camila Barros, Luciano Barbosa, Daniel Univ Fed Rio Grande do Norte Elect & Comp Engn Grad Program BR-59078970 Natal RN Brazil Univ Fed Paraiba Comp Syst Dept BR-58055000 Joao Pessoa Paraiba Brazil Univ Fed Bahia Elect & Comp Engn Dept BR-40170115 Salvador BA Brazil

Real-Time Digital Simulation (RTDS) is a powerful tool in modeling and analyzing electrical and drive systems because it provides an efficient and accurate process. There are several hardware devices for this type of simulation;however, their high costs have led to the increasing use of more affordable and reconfigurable technologies. In this context, many logic blocks and storage elements make the field programmable gate array (FPGA) an ideal device to perform RTDS. This work proposes a technique to embed a real-time digital simulator in an FPGA through Hardware Description Language (HDL) since it provides liberty in the architecture choice and no dependency on commercial ready-made hardware-software packages. The approach proposed focuses on system design developing with expression tree graph, synthesizing and verifying, prioritizing the performance and design accuracy concerning area and power consumption. Thus, the result acquisition occurs at a time step considered in real-time. A simulation of a direct current (DC) motor speed control has been incorporated into this work as an example of application, which includes the embedding and simulation of the electric machine and its drive system. Performance tests have shown that the developed simulator is real-time and makes possible realistic analysis of the interaction between the plant and its control. In addition, an idea of the hardware requirement for real-time simulation is proposed based on the number of mathematical operations.

关键词： real-time simulation field programmable gate array reconfigurable computing dynamic systems hardware description language

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