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field programmable gate-array-based real-time optical Doppler tomography system for in vivo imaging of cardiac dynamics in the chick embryo

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OPTICAL ENGINEERING 2009年第2期48卷 023201-1-023201-1页

作者： Thrane, Lars Larsen, Henning E. Norozi, Kambiz Pedersen, Finn Thomsen, Jakob B. Trojer, Maja Yelbuz, Talat Mesud Tech Univ Denmark Dept Photon Engn DTU Fotonik DK-4000 Roskilde Denmark Hannover Med Sch Dept Pediat Cardiol & Intens Care Med D-30625 Hannover Germany Lund Inst Technol Dept Phys SE-22100 Lund Sweden

We demonstrate a field programmable gate-array-based real-time optical Doppler tomography system. A complex-valued bandpass filter is used for the first time in optical coherence tomography signal processing to create the analytic signal. This method simplifies the filter design, and allows efficient and compact implementation by combining the conversion to an analytic signal with a pulse shaping function without the need for extra resources as compared to the Hilbert transform method. The conversion of the analytic signal to amplitude and phase is done by use of the coordinate rotation digital computer (CORDIC) algorithm, which is an efficient algorithm that maps well to the field programmable gate array. Flow phantom experiments, and the use of this system for in vivo imaging of cardiac dynamics in the chick embryo, are presented. We demonstrate the visualization of blood flow in the early embryonic heart as well as in the aorta, small peripheric vitelline vessels, and coronary arteries of fully formed chick hearts. (c) 2009 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3081062]

关键词： optical coherence tomography optical Doppler tomography digital signal processing field programmable gate array complex-valued bandpass filter

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Increasing Radiation Tolerance of field-programmable-gate-array-Based Computers Through Redundancy and Environmental Awareness

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JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2014年第2期11卷 61-74页

作者： Hane, Jennifer S. LaMeres, Brock J. Kaiser, Todd Weber, Raymond Buerkle, Todd SEAKR Engn Inc Radiat Hardened Elect Grp Centennial CO 80111 USA Montana State Univ Dept Elect & Comp Engn Bozeman MT 59718 USA Micron Technol Inc DRAM Test Grp Boise ID 83707 USA

Radiation-tolerant computing is of great importance to the aerospace community because future missions demand more computational power. Of special interest to the aerospace community are flight computers implemented on static random-access-memory-based field-programmable gate arrays. Such computer systems allow the in-flight reconfiguration of hardware that enables the practical deployment of truly reconfigurable computers. However, commercial static random-access-memory-based field-programmable gate arrays are uniquely susceptible to ionizing radiation. This paper introduces a computer architecture for static random-access-memory-based field-programmable gate arrays that resists failures caused by ionizing radiation. The approach extends the widely accepted fault mitigation practice of triple modular redundancy and configuration memory scrubbing by adding spare circuitry and environmental awareness through an ionizing radiation sensor. This paper describes the design of the system in addition to a theoretical analysis of its reliability using a Markov model and empirical analysis using a fault injector. A full system prototype is presented that includes a custom radiation sensor and a computer system implemented on a Xilinx Virtex-6 field-programmable gate array. Both the theoretical analysis and laboratory testing show the approach to be significantly more reliable than field-programmable-gate-array-based computers using only triple modular redundancy and scrubbing.

关键词： field programmable gate array Sensor Systems Radiation Tolerant Computing Random Access Memory Flight Computer Fault Tolerance Commercial off the Shelf Fault Injection Graphical User Interface CubeSat

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A scalable arbitrary waveform generator for atomic physics experiments based on field-programmable gate array technology

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REVIEW OF SCIENTIFIC INSTRUMENTS 2019年第4期90卷 043101-043101页

作者： Donnellan, Sean Hill, Ian R. Bowden, William Hobson, Richard Natl Phys Lab Hampton Rd Teddington TW11 0LW Middx England Imperial Coll Dept Phys London SW7 2AZ England

We present a field-programmable gate array (FPGA) based control system that has been implemented to control a strontium optical lattice clock at the National Physical Laboratory, UK. Bespoke printed circuit boards have been designed and manufactured, including an 8-channel, 16-bit digital to analog converter board with a 2 mu s update rate and a 4-channel direct-digital synthesis board clocked at 1 GHz. Each board includes its own FPGA with 28 digital output lines available alongside the specialized analog or radio frequency outputs. The system is scalable to a large number of control lines by stacking the individual boards in a master-slave arrangement. The timing of the digital and analog outputs is based on the FPGA clock and is thus very predictable and exhibits low jitter. A particular advantage of our hardware is its large data buffers that, when combined with a pseudoclock structure, allow complex waveforms to be created. A high reliability of the system has been demonstrated during extended atomic clock frequency comparisons. Published under license by AIP Publishing.

关键词： Atomic and molecular physics Digital-to-analog converter Optical lattices Programming languages field programmable gate array Chemical elements Direct digital synthesis Printed circuit board Control equipment

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Phase-locking particle image velocimetry measurement of unsteady flow behaviors: Online dynamic mode decomposition using field-programmable gate array

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PHYSICS OF FLUIDS 2019年第2期31卷 025109-025109页

作者： Deng, Yifan Wang, Peng Liu, Yingzheng Shanghai Jiao Tong Univ Sch Mech Engn Key Lab Educ Minist Power Machinery & Engn 800 Dongchuan Rd Shanghai 200240 Peoples R China Shanghai Jiao Tong Univ Gas Turbine Res Inst 800 Dongchuan Rd Shanghai 200240 Peoples R China

A novel online dynamic mode decomposition (DMD) approach using a field-programmable gate array (FPGA), which takes full advantage of the DMD to extract multiple unsteady events and the FPGA system for signal sampling and fast computation, was developed for phase-locking particle image velocimetry (PIV) measurements of unsteady flow behaviors. The turbulent separated and reattaching flow around a finite blunt plate with a length-to-height-ratio L/D = 6.0 was examined to demonstrate this novel approach. The wall-pressure field and the velocity field were measured using arrayed microphones and the conventional planar PIV setup, respectively. Offline DMD analysis of the wall-pressure fluctuation field was first used to identify the dominant modes corresponding to the energetically unsteady events. For each mode, the eigenmode and its mode coefficient reflected the spatial footprint pattern and temporal strength of the unsteady event, respectively. Next, trained machine learning of the mode coefficient was used to establish a phase prediction strategy. Finally, in the online analysis, the relevant eigenmode was cast into the FPGA device to serve as the reference mode for reconstruction with the sampled wall-pressure data, determining the phase signal to fire the PIV setup. High-resolution spatiotemporal evolutions of the dominant flow structures (i.e., the flapping separation bubble, the impinging leading-edge vortex, and the trailing-edge vortex street) were separately assembled. Further measurements demonstrated a clear panoramic view of the synchronous behavior of the enlarging separation bubble and the impinging leading-edge vortex. The proposed online FPGA-DMD approach can serve as a sophisticated strategy for phase-locking PIV measurements of unsteady flow behaviors. Published under license by AIP Publishing.

关键词： field programmable gate array Vortex dynamics Microphone array Flow instabilities Modal analysis Flow visualization

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Complex network knowledge-based field programmable gate arrays routing congestion prediction

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2025年 168卷

作者： Nie, Tingyuan Liu, Pengfei Zhao, Kun Wang, Zhenhao Qingdao Univ Technol Sch Informat & Control Engn Qingdao 266520 Peoples R China

Routing congestion occurs due to the unprecedented complexity of FPGA (field programmable gate array) designs. Accurately predicting the congestion of today's FPGAs at an early stage helps to reduce the burden of later design and optimization. This paper proposes an innovative complex network knowledge-based approach to predict FPGA routing congestion during the placement stage. The complex network features and circuit features highly correlated with routing congestion are mapped into RGB (red-green-blue) images according to the pre-perceived importance of the features to feed to the proposed model. A patched EDM (elucidating the design space of a diffusion-based generative model) with a patch transformation is introduced to focus on the most significant features. Experimental results show the remarkable achievements of the approach with an average SSIM (structural similarity) of 85.01 %, PSNR (peak signal-to-noise Ratio) of 27.85 dB (decibels), NRMS (normalized root mean square) of 12.91 %, and PIX (pixel accuracy) of 18.73 %, outperforming the recent state-of-the-art models like pix2pix, pix2pixHD, FCN (fully convolutional networks), and Lay-Net, improved by 4.87 %, 2.83 %, 5.77 %, and 18.56 % on key metric SSIM, respectively. The ablation validation highlights the efficiency of complex network features in routing congestion prediction. The outcome enables the identification of potential routing congestion in early design stages, facilitating the optimization solution of subsequent tractable routing problems.

关键词： field programmable gate array Routing congestion Complex network Machine learning Diffusion model

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A New Design and VLSI Implementation of Symmetric Daubechies Wavelet Filter Bank for Image Processing Applications

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2025年第5期44卷 3625-3640页

作者： Samantaray, Aswini K. Rahulkar, Amol D. Sahoo, Satyajeet Gorre, Pradeep Manipal Inst Technol Bengaluru Manipal Inst Higher Educ Dept ECE Manipal India Natl Inst Technol Dept EEE Veroda Goa India Vignans Fdn Sci Technol & Res Dept ECE Guntur India

Due to the irrational coefficients, the orthogonal wavelet filter banks (FBs) need a lot of resources when implemented on hardware. As a result, there is a decrease in operating speed, a significant memory requirement, and an increase in power consumption. This paper proposes an orthogonal low complex symmetric Daubechies-2 (4-tap) wavelet filter bank (FB) to address these problems. This is accomplished by obtaining dyadic filter coefficients and making the suggested FB symmetric by marginally modifying the perfect reconstruction (PR) criterion. By using fewer adders and shifters, the suggested wavelet FB achieves a significant reduction in dynamic power consumption without the need for multipliers. This is confirmed by implementing the suggested wavelet FB on the Zedboard ZYNQ-7000 AP-SoC (Zynq FPGA from Xilinx) field programmable gate array (FPGA). The suitability of the suggested FB is tested in medical image retrieval and image compression applications. Results from simulations demonstrate that, when compared to state-of-the-art techniques, the suggested wavelet FB performs better in terms of retrieval accuracy (ARP, ARR) for medical image retrieval and PSNR for image compression on the benchmark image datasets.

关键词： Orthogonal wavelets Perfect reconstruction field programmable gate array Image compression Image retrieval

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An efficient XOR-free implementation of polar encoder for reconfigurable hardware

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INTEGRATION-THE VLSI JOURNAL 2025年 100卷

作者： Kumar, Navin Kedia, Deepak Purohit, Gaurav GJUS &T Dept ECE Hisar Haryana India CSIR CEERI Adv Informat Technol Grp Pilani Rajasthan India

This paper presents a novel approach to implementing an XOR-Free architecture of the non-systematic polar encoder (NSPE) for 5G radio. The optimization of XOR logic for hardware (HW) implementation is essential to reduce delay and power consumption. The proposed architecture for NSPE replaces XOR operations with combinational logical patterns, and some redundant patterns are removed with the help of bit manipulation to make it more efficient. The design infers multiplexers (2:1 or 4:1) and inverters as its functional units, making the design adequate and effective in alleviating HW complexity. The XOR-Free encoder performs the same functionality as the XOR-based conventional encoder. We have written a MATLAB script that generates Verilog hardware description language (HDL) code for fully or partially parallel polar encoders tailored to specific code lengths (N) and degrees of parallelism (M). A comparative analysis of various fully and partially parallel encoders with the XOR-Free algorithm is presented. The implementation results show that the proposed architectures are more efficient in terms of HW cost, power consumption, throughput, and latency.

关键词： Non-systematic polar encoder Permutation Bit fixing field programmable gate array Parallelism Hardware

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A power-awareness routing protocol for sustainable low-power wireless networks: FPGA vs. microcontroller implementation

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INTERNATIONAL JOURNAL OF AD HOC AND UBIQUITOUS COMPUTING 2025年第2期48卷 75-93页

作者： Telgote, Aparna M. Mande, Sudhakar S. Ramrao Adhik Inst Technol Navi Mumbai India Don Bosco Inst Technol Mumbai India

Wireless networks play a vital role in our daily lives;however, addressing the energy efficiency challenge in low-power wireless networks requires innovative strategies. This research explores deploying a centralised power-aware routing protocol (CPARP) on field programmable gate arrays (FPGAs), presenting a promising alternative to traditional microcontroller-based devices. The CPARP enhances power efficiency by strategically selecting data routing paths based on metrics such as transceiver power, delay, and link quality. Comparative analysis shows that the FPGA-based approach achieves up to 47% power savings, reducing current draw from 80 mA to 20 mA while maintaining network performance metrics like latency and packet delivery success rates. Real-time testing reveals that individual microcontroller-based nodes consume only 101 mW. This study not only demonstrates the practical applications and benefits of CPARP but also advocates for exploring alternative hardware platforms. The insights gained contribute to the advancement of wireless network technologies, promoting sustainability and energy efficiency.

关键词： field programmable gate array FPGA ESP32 Spartan 6 Zigbee S2C X-CTU

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Removing ghost markers in trinocular optical tracking using convolutional neural network

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SIGNAL IMAGE AND VIDEO PROCESSING 2025年第6期19卷 1-14页

作者： Gu, Xiumin Zhang, Lintong Guan, Peifeng Lin, Qinyong Yang, Rongqian South China Univ Technol Sch Elect & Informat Engn Guangzhou 510641 Guangdong Peoples R China South China Univ Technol Guangdong Prov Key Lab Millimeter Wave & Terahertz Guangzhou 510641 Guangdong Peoples R China South China Univ Technol Guangdong Hong Kong Macao Joint Lab Millimeter Wav Guangzhou 510641 Guangdong Peoples R China Aimooe Technol Co Ltd Guangzhou 512623 Guangdong Peoples R China Zhongkai Univ Agr & Engn Sch Automat Guangzhou 510225 Guangdong Peoples R China

Surgical instruments are tracked by the near-infrared binocular optical tracking system through the locating of reflective markers. However, during binocular optical tracking, misidentified ghost markers may appear, significantly affecting the accuracy of surgical tracking. In this paper, a trinocular optical tracking system (TOTS) is constructed, and an intelligent method is proposed to remove these misidentified ghost markers by utilizing the color image features of reflective markers. A convolutional neural network is designed to recognize markers, achieving a recognition accuracy of 97.9% through training and testing on a homemade dataset. Subsequently, a data transmission architecture is designed to deploy the network on the TOTS's field programmable gate array, optimized through 12-bit integer quantization, resource multiplexing, and parallel processing. The final recognition accuracy reaches 95.0%, with an average recognition time of 0.231 ms and an on-chip power consumption of 3.327 W. The CNN's processing time is 0.110 ms, which is 2.45 times faster than that on a graphics processing unit and 9.31 times faster than that on a central processing unit. Compared to other methods presented in the relevant literature, this method offers a faster rate and broader applicability in the removal of ghost markers.

关键词： Convolutional neural network(CNN) field programmable gate array Optical tracking system (OTS) Ghost markers

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Design and HDL Implementation of Pulse-Arrival-Time Estimation Using XGBoost Regression With Tree-Recycling Architecture

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IEEE ACCESS 2025年 13卷 27596-27609页

作者： Choi, Hyo-Jeong Um, Ji-Yong Kumoh Natl Inst Technol Dept Med IT Convergence Engn Gumi Si 39253 South Korea

This paper presents a pulse-arrival-time (PAT) estimation scheme using Extreme Gradient Boosting (XGBoost) regression and its implementation with hardware description language (HDL). PAT is a significant metric for the estimation of pulse wave velocity (PWV) and blood pressure. We leverage morphological features of single photoplethysmogram (PPG) waveforms and subject-specific parameters to estimate PAT values through a decision tree ensemble regression model. XGBoost regression is adopted for PAT estimation through a comparative study conducted in software. To enable the integration of the regression model into a single chip, we propose a tree-recycling architecture for an area-efficient implementation of the decision tree ensemble model. The proposed PAT estimation has been implemented on a field-programmable gate array (FPGA, Artix7, Xilinx) for real-time verification using a dataset. Additionally, the active area of the proposed scheme in an integrated circuit was estimated after the place-and-route (PnR) procedure, resulting in an area of 1.44 mm2. We utilized the Vital Signs DataBase (VitalDB) for training and testing the proposed PAT estimation in a software-hardware co-design framework. Validation on 80 subjects yielded a determination coefficient (R2) of 0.983 in the linear regression analysis after implementing the HDL on an FPGA.

关键词： Estimation Hardware Biomedical monitoring Regression tree analysis field programmable gate arrays Elasticity Hardware design languages Computer architecture Boosting Training Pulse arrival time decision tree ensemble model extreme gradient boosting regression field programmable gate array tree-recycling architecture hardware description language

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